PhaseLink Offices www.phaselink.com PhaseLink Corporation, USA US Headquarters 47745 Fremont Boulevard Fremont, CA 94538 + 1.510.492.0990 (phone) + 1.510.492.0991 (fax) [email protected] PhaseLink Company, Ltd., Taiwan Asia Pacific Headquarters 5F-2, No. 94, Pao Chung Road. Hsin Tien, Taipei, Taiwan, R.O.C. + 886.2.2910.0248 (phone) + 886.2.2910.0249 (fax) [email protected] PhaseLink Technology Inc., China No. 2101, Building 3, Caoxi Rd Xuhui Qu, Shanghai, China + 86.21.54261068 (phone) [email protected] Product Selector Guide 2006 Copyright©2006, PhaseLink Corporation PhaseLink and AFM are trademarks of PhaseLink Corporation 3/06 www.phaselink.com Product Contents About PhaseLink Founded in 1991, PhaseLink has established itself as a leading global supplier of high performance Frequency Generation and Signal Conditioning solutions for broadband communication, storage network, consumer electronics and personal computing markets. Our expertise resides in analog intensive mixed signal integrated circuits for frequency synthesis, multiplication and conditioning. Through our proprietary technology, we provide unequalled performance in frequency multiplication for optical, Gigabit and telecommunication applications. Our constant efforts for innovation and simplification also deliver affordable clock generation products for the personal electronic, home electronic, portable device, storage network, and wireless system markets. Through our advanced design, manufacturing, and packaging capabilities, coupled with our responsiveness to shifting market trends, we have established a track record of producing highperformance, low-cost products. Our design methodology enables rapid prototyping of both standard and custom solutions, available for sampling in just a few weeks. Our worldwide manufacturing information system ensures ontime delivery. Furthermore, PhaseLink and its suppliers are ISO 9001-certified. Frequency Generation Voltage Controlled Frequency Source 14 15 12 13 Reference Frequency Clock 10 11 12 13 16 Crystal Oscillator (XO) ICs General Purpose PLL Multiplier Clocks Analog Frequency Multiplier Clocks PhasorV Frequency Multiplier Clocks Multimedia and Network Clocks Quick Turn Programmable Clock 16 Low Cost Programmable Clocks Clock Distribution 18 Non-PLL Fanout Buffers 18 Zero Delay Buffers 18 Translator Buffers Signal Conditioning 17 EMI Reduction ICs Featured Products 4 5 6-9 19 2 VCXO ICs VCXO with PLL Multiplier ICs VCXO with Analog Frequency Multiplier IC VCXO with PhasorV Frequency Multiplier IC Analog Frequency Multiplier (AFM) PhasorV Frequency Multiplier Quick Turn Programmable Clocks (QTC) 622.08MHz Phase Noise Comparison 3 Featured Product Featured Product < 0.4ps Phase Jitter (12Khz-20Mhz) < 20ps PK-PK Jitter < 0.25ps Phase Jitter (12Khz-20Mhz) < 2.5ps RMS Period Jitter < 20ps PK-PK Jitter 0 Phase Noise Comparison at 155.52Mhz -20 -40 155.52Mhz Jitter Comparison -60 -80 -100 PhasorV (blue) =38.88x4 -120 -140 -160 AFM (red) =77.76x2 10 100 1K 10K 100K 1M 10M 100M 8 9 L(f) [dBc/Hz] vs f [Hz] Practically, No Accumulated Jitter PhasorV Long Term Jitter Industry’s first CMOS Non-PLL multiplier utilizing analog multiplication of a high frequency fundamental or 3rd overtone crystal input. Our patent pending AFM technology can generate up to 800MHz in LVPECL, LVDS or CMOS without using a phased lock loop. This is achieved with practically no jitter or phase noise deterioration. See page 12 for detailed product selector guide. RMS Jitter (ps) (Crystal=38.88MHz, Output=155.52MHz) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0.0 0 1 2 3 4 5 6 Interval (us) 7 10 For detail product selector guide, please refer to page 13. 4 5 Featured Product Tiny Package, Big Benefits World’s Smallest Programmable Clock Applications Unlimited Supports 1.8v, 2.5v, 3.3v 30~70ps Peak-Peak Jitter Low Power Consumption Fast Turnaround Unit: mm 6x5 11.5X 3x3 3.5X 3x3 3.5X 2.2x2.3 2x1.3 2X 1X PhaseLink’s QTC programmable clock family is a general purpose frequency synthesizer with the key features of low jitter, low power and tiny package. This low cost frequency source solution is designed to fit almost any application where high performance, space saving and time to market is crucial. 6 Device Family Input (MHz) Output (MHz) # of Outputs Voltage Package PL611s Fundamental: 10 - 50 Reference : <200 <200 up to 2 1.8V, 2.5V, 3.3V 6 DFN-2x1.3 6 SC70 6 SOT23 8 SOP PL611 Fundamental: 10 - 30 Reference : <200 <200 <375 (diff) up to 3 2.5V, 3.3V 6 SOT23 8 SOP PL612 Fundamental: 10 - 50 or 32.768Khz Reference : <200 <200 up to 8 1.8V, 2.5V, 3.3V 8 SOP 16 QFN3x3 16 TSSOP Programming Box Available Evaluation Board, Samples Request, visit http://www.phaselink.com/qtc.htm phaselink.com/qtc.htm 7 Featured Product Design Ideas using Programmable Clocks Generate up to 3 programmable output clocks Ideal for Programmable VCXO with Selectable Frequency • Set-top-box • LCD-TV • Printer • Projector • Network Switch • Digital Camera • Multiple oscillators or crystals replacement Low-cost PECL/LVDS Differential Clock Ideal for • Set-top-box • Network Switch • HDTV • Video Generate up to 5 clocks from 32.768Khz crystal Ideal for • Set-top-box • Network Switch • Video • HDTV • Communication Configured as multiple fan out Oscillator Ideal for • xDSL Modem • Network Switch • Set-top-box • Multiple Oscillators replacement 8 Ideal for • Hand-held devices • PDA/Smart Phone • Cell Phone • Digital Camera • DV • Set-top-box Generate up to 8 clocks Ideal for • Set-top-box • LCD-TV • Printer • Projector • Network Switch • Multiple oscillators or crystals replacement 9 Crystal Oscillator (XO) ICs General Purpose PLL Multiplier Clocks PhaseLink’s crystal oscillator ICs provide the best level of negative impedance, lowest jitter, and lowest phase noise up to the 200MHz range. Our best in class buffer outputs (CMOS, LVDS, LVPECL) make them suitable for all types of applications, including low current clock reference, low jitter, low phase noise system clock reference, and small ceramic based SMD crystal oscillators. Integrating with the best in class PLL multiplier, this high performance clock family products offer very low jitter output frequency from 750KHz to 800MHz using a low-cost crystal input. Ideas for all types of applications to replace multiple expensive crystals and/or crystal oscillators. Part Number Function Input (MHz) Output (MHz) Output Type Operating Voltage Package Part Number Function Input (MHz) Multiplier Output (MHz) Output Type Voltage Package PLL600-27B XO 10 - 52 10 - 52 CMOS Low Current 1.8V - 3.3V 6 SOT23 8 SOP PLL602-00 XO+PLL 12 - 25 1,2,4,8 12 - 200 CMOS (Hi Drive) 3.3V DIE PLL600-37 XO 10 - 52 10 - 52 Clipped CMOS Ultra Low Current 1.8V - 3.3V 8 SOP PLL602-01 XO+PLL 12 - 25 2 24 - 50 CMOS 3.3V 8 SOP/TSSOP PLL600-27T XO 10 - 52 10 - 52 3 CMOS Ultra Low Current 1.8V - 3.3V 8 SOP PLL602-03 XO+PLL 12 - 25 4 48 - 100 CMOS 3.3V 8 SOP/TSSOP PLL602-04 XO+PLL 12 - 25 8 96 - 200 CMOS 3.3V 8 SOP/TSSOP PLL600-27F XO 10 - 52 10 - 52 5 CMOS Ultra Low Current 1.8V - 3.3V 14 SOP PLL602-35 XO+PLL 12 - 25 /16 to x32 0.75 - 800 PECL, Inverted OE 3.3V 16 TSSOP, 16 QFN3x3 PLL600-27M Dual XO 10 - 52 10 - 52 4 CMOS Ultra Low Current 1.8V - 3.3V 14 SOP XO+PLL 12 - 25 /16 to x32 0.75 - 800 16 TSSOP, 16 QFN3x3 XO 12 - 27 12 - 27 1 LVDS, 1 CMOS 2.5V, 3.3V 8 SOP CMOS (-37) PECL (-38) LVDS (-39) 3.3V PLL602-89 PLL602-37 PLL602-38 PLL602-39 PLL602-89C XO 12 - 27 12 - 27 1 LVDS, 2 CMOS 2.5V, 3.3V 8 SOP PLL620-00 XO+PLL 100200 1,2,4 100 - 800 3.3V DIE PLL602-89D XO 12 - 27 12 - 27 2 LVDS 2.5V, 3.3V 8 SOP CMOS PECL LVDS PLL602-89T XO 12 - 27 12 - 27 3 LVDS, 1 CMOS 2.5V, 3.3V 16 SSOP XO+PLL 100 - 800 100 - 200 (or 3rd OT) 100 - 200 Differential outputs: PECL/LVDS 2.5V, 3.3V DIE CMOS (-07) PECL (-08) 3.3V XO 100200 1,2,4 PLL620-20 PLL620-07 PLL620-08 16 TSSOP, 16 QFN3x3 PLL620-09 XO+PLL 1,2,4,8 3.3V XO 100 - 200 (or 3rd OT) 100 - 200 Differential outputs: PECL (-28) LVDS (-29) 2.5V, 3.3V 16 TSSOP 100 - 1GHz LVDS PLL620-28 PLL620-29 100200 16 TSSOP, 16 QFN3x3 PLL601-01 XO+PLL 10-27 10 - 160 CMOS 3.3V 16 SOP/TSSOP PLL620-30 XO 65 - 130 (or 3rd OT) 32.5 - 130 Differential outputs: PECL/LVDS or CMOS 2.5V, 3.3v DIE 1,2,3,4,5, 6,7,8,9, 10,11,12,16 PLL601-02 XO+PLL 10-27 4,8 20-160 CMOS 3.3V 16 SOP/TSSOP PLL620-38 PLL620-39 XO 65 - 130 (or 3rd OT) 32.5 - 130 Differential outputs: PECL (-38) LVDS (-39) (with selectable /2) 2.5V, 3.3V 16 TSSOP PLL620-80 XO 19 - 65 (or 3rd OT) 9.5 - 65 Differential outputs: PECL, LVDS or two CMOS 2.5V, 3.3V DIE PLL620-88 PLL620-89 XO 19 - 65 (or 3rd OT) 9.5 - 65 Differential outputs: PECL (-88) LVDS (-89) (with selectable /2) 2.5V, 3.3V 16 TSSOP 10 11 Analog Frequency Multiplier (AFMTM) PhasorVTM Frequency Multiplier PhaseLink’s low phase noise and low jitter Analog Frequency Multiplier products provide the most cost efficient clocking solutions for high speed applications. The multiplication of two (X2) or four (X4) times the input crystal frequency significantly lower the cost of expensive crystals to achieve the most stringent performance requirements of telecommunications, Storage networking, and high speed networking LAN systems. The PhasorV is a low jitter and low phase noise frequency multiplier, capable of 0.4ps RMS phase jitter and less than 25ps peak to peak jitter, with practically no Accumulated Jitter. Using a low-cost crystal of 19-40MHz, the PhasorV enables output frequencies of 2X, 4X, 8X, or 16X, up to 640MHz. It supports CMOS, LVDS, and PECL outputs. Jitter(ps) - Typical Part Number Input Range (MHz) Output Range (MHz) Output Type Voltage RMS Period Peak to Peak Period Phase Jitter 12K20MHz Jitter(ps) - Typical Package VCXO ICs (AFM) 75 - 200 300 - 800 (4X) PECL (-08) LVDS (-09) 2.5V, 3.3V 4 25 0.08 @622M DIE, Wafer 16 QFN3x3 16 TSSOP PL560-37 PL560-38 PL560-39 30 - 80 120 - 320 (4X) CMOS (-37) PECL (-38) LVDS (-39) 2.5V, 3.3V 4.7 25 0.25 @155M DIE, Wafer 16 QFN3x3 16 TSSOP PL560-47 PL560-48 PL560-49 30 - 80 60 - 160 (2X) CMOS (-47) PECL (-48) LVDS (-49) 2.5V, 3.3V 2.5 18 0.25 @155M DIE, Wafer 16 QFN3x3 16 TSSOP PL560-68 PL560-69 75 - 200 150 - 400 (2X) PECL (-68) LVDS (-69) 2.5V, 3.3V 2.5 18 0.10 @311M DIE, Wafer 16 QFN3x3 16 TSSOP XO ICs (AFM) CMOS (-07) PECL (-08) LVDS (-09) 2.5V, 3.3V 2.5 PL663-17 CMOS (-17) 75 - 140 150 - 280 PL663-18 PECL (-18) (or 3rd OT) (2X) PL663-19 LVDS (-19) 2.5V, 3.3V 2.5 PL663-28 140 - 160 280 - 320 PL663-29 (or 3rd OT) (2X) 2.5V, 3.3V 2.5 60 - 160 (2X) Input Range (MHz) Output Range (MHz) Output Type CMOS, PECL, LVDS # Of Voltage Output RMS Period Peak to Peak Period Phase Jitter 12K20MHz Package VCXO ICs PL560-08 PL560-09 PL663-07 30 - 80 PL663-08 (or 3rd OT) PL663-09 Part Number PECL (-28) LVDS (-29) 18 18 18 0.29 @106M DIE, Wafer 16 QFN3x3 16 TSSOP 0.14 @212M DIE, Wafer 16 QFN3x3 16 TSSOP 0.13 @311M DIE, Wafer 16 QFN3x3 16 TSSOP PL580-30 19 - 40 38 - 640 (2X, 4X, 8X,16 X) PL580-37 PL580-38 PL580-39 19 - 40 PL580-68 PL580-69 1 2.5V, 3.3V 3 20 0.4 DIE @155M Wafer 38 - 640 CMOS (-37) (2X, 4X, PECL (-38) 8X,16 X) LVDS (-39) 1 2.5V, 3.3V 3 20 0.4 16 QFN3x3 @155M 16 TSSOP 20 - 40 320 - 640 PECL (-68) (16X) LVDS (-69) 1 2.5V, 3.3V 6 40 0.4 16 QFN3x3 @622M 16 TSSOP PL680-37 PL680-38 PL680-39 19 - 40 38 - 640 CMOS (-37) (2X, 4X, PECL (-38) 8X,16 X) LVDS (-39) 1 2.5V, 3.3V 3 20 0.4 16 QFN3x3 @155M 16 TSSOP PL681-37 19 - 40 76 - 200 (4X, 5X) CMOS 4 2.5V, 3.3V TBD TBD TBD 16 QFN3x3 16 TSSOP PL681-39 19 - 40 76 - 320 (4X, 8X) LVDS 2 2.5V, 3.3V TBD TBD TBD 16 QFN3x3 16 TSSOP XO ICs Note1: Phase Noise was obtained using Agilent E5500 data. Note2: No Filtering was used in Jitter Calculations. Note1: Phase Noise was obtained using Agilent E5500 data. Note2: No Filtering was used in Jitter Calculations. 12 13 VCXO (Voltage Controlled Crystal Oscillator) ICs VCXO with PLL Multiplier ICs PhaseLink’s integrated low phase noise VCXO products provide cost efficient solutions with high linearity, wide pull-range, and very high temperature stability. They are available in die form or in small form factor packaged chips. Our products meet performance requirements of SONET, ADSL, VDSL, Set top box, and many more applications. This high performance VCXO family of products offers very low jitter and phase noise with integrated PLL multipliers as high as 32X and generates output frequency from 750KHz to 800MHz, using a low-cost crystal input. These VCXO’s high linearity, wide pull range, and high temperature stability make them ideal for Video, SONET, VDSL, ADSL, etc. applications. Part Number Function Input (MHz) Output (MHz) Output Type Pull Range (ppm)1 Operating Voltage Package Part Number Function Input Range (MHz) Multiplier Output Range (MHz) Output Type Pull Range (ppm)2 Voltage Package PLL500-17 PLL500-17B VCXO 17 - 36 17-36 CMOS +/-200 2.5V, 3.3V 6 SOT-23, 8 SOP or DIE PLL502-00 VCXO+PLL 12-25 1,2,4,8 12 - 200 CMOS +/- 200 3.3V DIE PLL502-02 VCXO+PLL 12-25 2 24 - 50 CMOS +/- 200 3.3V 8 SOP PLL500-27B VCXO 27 - 65 27 - 65 CMOS +/-200 2.5V, 3.3V 8 SOP or DIE PLL502-03 VCXO+PLL 12-25 4 48 - 100 CMOS +/- 200 3.3V 8 SOP PLL500-37 VCXO 40 - 80 40 - 80 CMOS +/-120 2.5V, 3.3V 8 SOP or DIE PLL502-04 VCXO+PLL 12-25 8 96 - 200 CMOS +/- 200 3.3V 8 SOP PLL500-37B VCXO 65 - 130 65 - 130 CMOS +/-120 2.5V, 3.3V 8 SOP or DIE 12-25 8 96 - 200 3.3V 16 TSSOP 12 - 27 12 - 27 CMOS +/- 200 2.5V, 3.3V 8 SOP PECL (-11) LVDS (-12) +/- 200 VCXO PLL502-11 PLL502-12 VCXO+PLL PLL502-05 PLL502-25 PLL502-30 VCXO+PLL 12-25 3.3V DIE 27 27 + Audio Clock CMOS +/- 250 3.3V 16 SOP CMOS PECL LVDS +/- 200 VCXO + Audio PLL /16 to x32 0.75 - 800 PLL502-26 PLL502-50 VCXO 20 - 50 2.5 - 50 CMOS +/- 200 2.5V, 3.3V DIE PLL502-35 VCXO+PLL 12-25 0.75 - 800 3.3V VCXO 20 - 52 20 - 52 CMOS +/- 200 2.5V, 3.3V 8 SOP PECL (~OE) +/- 200 PLL502-51 /16 to x32 16 QFN3x3 16 TSSOP PLL502-52 VCXO 20 - 40 10 - 20 CMOS +/- 200 2.5V, 3.3V 8 SOP VCXO+PLL 12-25 /16 to x32 0.75 - 800 3.3V 16 QFN3x3 16 TSSOP VCXO 120 - 200 120 - 200 CMOS PECL LVDS +/-110 2.5V, 3.3V DIE CMOS (-37) PECL (-38) LVDS (-39) +/- 200 PLL520-20 PLL502-37 PLL502-38 PLL502-39 PLL520-00 VCXO+PLL 100200 1,2,4,8 100 - 1GHz CMOS PECL LVDS +/- 110 3.3V DIE PLL520-07 PLL520-08 VCXO+PLL 100200 1,2,4 100 - 800 +/- 110 3.3V 16 TSSOP, 16 QFN3x3 PLL520-09 VCXO+PLL 100200 1,2,4,8 100 - 1GHz LVDS +/- 110 3.3V 16 TSSOP, 16 QFN3x3 PLL520-10 VCXO+PLL 65-130 1,2,4,8 65 - 800 CMOS PECL LVDS +/- 110 3.3V DIE PLL520-17 PLL520-18 PLL520-19 VCXO+PLL 65-130 1,2,4,8 65 - 800 CMOS (-17) PECL (-18) LVDS (-19) +/- 110 3.3V 16 TSSOP PLL520-28 VCXO 120 - 200 120 - 200 PECL +/-110 2.5V, 3.3V 16 TSSOP, 16 QFN3x3 PLL520-29 VCXO 120 - 200 120 - 200 LVDS +/-110 2.5V, 3.3V 16 TSSOP, 16 QFN3x3 PLL520-30 VCXO 65 - 130 65 - 130 PECL LVDS +/-120 2.5V, 3.3V DIE PLL520-38 VCXO 65 - 130 65 - 130 PECL +/-120 2.5V, 3.3V 16 TSSOP PLL520-39 VCXO 65 - 130 65 - 130 LVDS +/-120 2.5V, 3.3V 16 TSSOP PLL520-40 VCXO 65 - 130 65 - 130 CMOS +/-120 2.5V, 3.3V DIE PLL520-80 VCXO 19 - 65 9.5 - 65 PECL LVDS +/-200 2.5V, 3.3V DIE PLL520-88 VCXO 19 - 65 9.5 - 65 PECL +/-200 2.5V, 3.3V 16 TSSOP PLL520-89 VCXO 19 - 65 9.5 - 65 LVDS +/-200 2.5V, 3.3V 16 TSSOP PLL521-23 VCXO 100 – 200 100 – 200 PECL +/-110 2.5V, 3.3V 16 TSSOP, DIE CMOS (-07) PECL (-08) Note 1: Pull measurement was obtained using a typical crystal within target frequency range. Typical Low frequency crystal has C1=16 fF, C0=4 pF (C0/C1=250), High frequency mesa crystal has C1=6 fF, C0=1.8 pF (C0/C1=300). Note 1: Pull measurement was obtained using a typical crystal within target frequency range. Typical Low frequency crystal has C1=16 fF, C0=4 pF (C0/C1=250), High frequency mesa crystal has C1= 6 fF, C0=1.8 pF (C0/C1=300). 14 15 Low Cost Programmable Clocks EMI Reduction ICs Quick-Turn Clock (QTC) is PhaseLink’s line of programmable, Low-cost clock ICs. Accepting a single crystal or reference clock input and producing up to 8 outputs, the QTC family is designed to reduce system cost and fit almost any application where high performance, space saving, cost sensitivity and time to market are crucial. PhaseLink’s proprietary Spread Spectrum Timing (SST) technology can efficiently suppress EMI without requiring expensive enclosures or system redesign. These EMI reduction ICs with very low Cycle to Cycle jitter (Typical meaured at 100ps) are suitable for clock generation from a single crystal or a signal reference. Part Number Input (MHz) Output (MHz) # of Outputs Voltage Other Features Package Part Number Function Input (MHz) Output (MHz) SST Modulation Magnitude Voltage /Output Package PL611-01 10 - 30 <200 up to 3 2.5V, 3.3V Programmable OE/PDB/ FSEL 8 SOP 6 SOT23 PLL702-01 Fixed Freq. output + SST 14.318 7 outputs out of 9 freq, <133 -0.5% to -1.25% Down Spread 3.3V 28 SSOP PL611-05 PL611-06 10 - 30 <35 up to 2 2.5V, 3.3V 6 DFN (-06) 6 SOT23 PLL702-06 Fixed Freq. output + SST 14.318 1 CPU (<133) 1 USB clock -0.5% to -1.25% Down Spread 3.3V 16 SSOP PL611-07 PL611-08 10-30 <75 up to 2 2.5V, 3.3V FSEL 6 DFN (-08) 6 SOT23 PLL702-07 Fixed Freq. output + SST 14.318 -0.5% to -1.25% Down Spread 3.3V 16 SSOP PL611-31 10 - 30 <200 Diff+1 2.5V, 3.3V 1 Differential pair + 1 Single ended ( or FSEL or PDB) 8 SOP 3 [email protected] 1 [email protected] 1 USB clock <200 up to 2 1.8V, 2.5V, 3.3V Programmable REF/PDB/ FSEL/OE 6 SOT23 6 SC70-6 10 - 30 Crystal or Clock Input 10 - 30 (-01) 20 - 60 (-02) 40 - 120 (-04) 60 - 180 (-06) 0.50% to 3.50% A, C, D Spread* PL611S-26 REF <200 <200 1 1.8V, 2.5V, 3.3V PDB and FSEL 6 SOT23 1X (-01) 2X (-02) 4X (-04) 6X (-06) PLL + SST 8 SOP 10 - 30 PLL701-01 PLL701-02 PLL701-04 PLL701-06 3.3V PL611S-02 PLL701-10 up to 8 1.8V, 2.5V, 3.3V PDB and FSEL 16 QFN3x3 16 TSSOP 0.25% to 3.75% A, C, D Spread* 16 SSOP < 200 10 - 30 Crystal or Clock input 3.3V 10 - 50 (1,2,3,4,5,6, 7,8)X PLL + SST 10 - 240 PL612-01 PL612-32 32.768KHz <200 up to 6 1.8V, 2.5V, 3.3V PDB and FSEL 16 QFN3x3 16 TSSOP PLL701-50 (1,2,3,4,5,6, 7,8)X PLL + SST 10 - 30 Crystal or Clock input 10 - 240 0.25% to 3.75% A, C, D Spread* 3.3V DIE LAN and Multimedia Clocks Source PLL701-11 (1,2,4)X PLL + SST 24 - 120 Clock input 24 - 240 0.50% to 2.50% Center Spread* 3.3V 8 SOP PhaseLink’s LAN Networking Clocks provide the most commonly required frequencies in switches, hubs, and other LAN systems, from a single reference crystal. The Multimedia Clocks are designed to provide the necessary video or audio clocking requirements. PLL701-13 (1,2,4)X PLL + SST 24 - 120 Clock input 24 - 240 -0.50% to -3.0% Down Spread* 3.3V 8 SOP PLL701-17 (1,2,4,2.94) X PLL+SST 12 - 60 Crystal or Clock input 12 - 240 0.25% to 1.25% Center Spread* 3.3V 8 SOP Part Number Input (MHz) [Output Frequencies (MHz)] X number of outputs Output Type Voltage Package PLL701-21 1X PLL + SST 24 - 200 Clock input 24 - 200 0.25% to 2.5% Center Spread* 3.3V 8 SOP PLL650-02 25 50x4, [25 or 125]x2, [25 or 100]x1, [66.6 or 75 or 83.3 or 100]x2, Spread Spectrum CMOS 3.3V 24 SSOP PLL701-25 1X PLL + SST 33 - 90 Clock input 33 - 90 5 outputs +/- 0.50% Center Spread 3.3V 8 SOP PLL650-03 25 50x4, [25 or 100]x1, [66.6 or 75 or 83.3 or 100]x1, Spread Spectrum CMOS 3.3V 16 SOP PLL701-26 1X PLL + SST 33 - 90 Clock input 33 - 90 5 outputs +/- 1.0% Center Spread 3.3V 8 SOP PLL650-04 25 25x1, 50x1, [90 or 100 or 125 or 133 or 145 or 150] x5, Spread Spectrum CMOS 3.3V 20 SSOP PLL701-31 1X PLL + SST 10 - 30 Crystal or Clock input 10 - 30 3.25% to 3.75% A, C, D Spread* 3.0V 8 SOP PLL601-22 27 27x2, 1x Selectable Audio: [8.192, 11.2896, 12.288, 16.9344, 18.432, 22.5792, 8, 24.576] CMOS 3.3V 16 SOP *Note: C: Center Spread. A: Asymmetric Spread. D: Down Spread. General SST spread is at .25% increments. Please refer to the datasheet for detail features. PLL601-26 PLL601-27 27 27x1, (-26: Selectable Audio [12.288, 24.576]) (-27: Selectable [8.192,11.2896,12.288, 24.576]) CMOS 3.3V 8 SOP PLL603-27 27 27x2, 83.3x1, 12.28x1, 3.38x1, 1.53x1, 48Kx1 CMOS 3.3V 28 SSOP 16 17 Benchmark Clock Distribution Phase Noise Comparison (622.08Mhz PECL) PhaseLink’s clock distribution products consist of Translator buffers, Zero delay buffers and Non-PLL fanout buffers. These general purpose buffer products will reproduce a master clock frequency up to 1GHz with low skew between the outputs. Our Zero Delay buffers use a Phase Locked Loop to ensure a zero-delay between the outputs and the master signal. PhaseLink makes no compromise when it comes to performance. Achieving the best phase noise performance in an affordable solution is no exception. The chart shown below is the Phase Noise comparison among PhaseLink’s products Translator Buffers Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL130-05 Translator to PECL DC to 1.0 GHz 1 PECL Single ended to PECL, OE (Low) 2.5V, 3.3V 16 QFN3x3 PLL130-07 Translator to CMOS DC to 200 CMOS Singled ended to CMOS 2.5V, 3.3V 8 SOP, 16 QFN3x3 PLL130-08 Translator PLL130-09 to PECL or LVDS DC to 1.0 GHz 1 PECL (-08) 1 LVDS (-09) Single ended to PECL (-08), LVDS (-09) 2.5V, 3.3V 8 SOP, 16 QFN3x3 • • • • 4X AFM with high frequency mesa fundamental crystal input (560-08) SAW oscillator (570-00) Phasor-V multiplier (16X) with 38.88Mhz fundamental crystal input (580-38) PLL multiplier (32X) with low frequency crystal input (502-38) Note: All OE functions are “Logic High” Enabled unless indicated otherwise. Zero Delay Buffers Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL102-03 PLL102-04 PLL102-05 5 outputs 75-180 (-03) 50-120 (-04) 25- 60 (-05) CMOS High Performance Low Skew Buffer 3.3V 8 SOP PLL102-10 3 outputs 10-220 CMOS High Performance Low Skew Buffer 2.5V 3.3V 6 SOT23 8 SOP Non-PLL Fanout Buffers Part Number Function Input/Output (MHz) Output Type Description Voltage Package PLL103-02 12 Differential outputs for DDR SDRAM 66 - 170 Diff. CMOS < 5ps delay < 100ps skew I2C interface 2.5V, 3.3V 48 SSOP PLL600-27F 5 Outputs 10-52 CMOS Low Jitter: 2.5 ps 1.8V, 2.5V, 3.3V 14 SOP PLL600-27T 3 Outputs 10-52 CMOS Low Jitter: 2.5 ps 1.8V, 2.5V, 3.3V 8 SOP PL611-01 3 Outputs DC-200 CMOS Programmable Drive Strength for High fanout 2.5V, 3.3V 8 SOP 18 19