PLL PL560

Analog Frequency Multiplier
PL560-xx VCXO Family
PRODUCT DESCRIPTION
FEATURES
PhaseLink’s Analog Frequency Multiplier TM (AFM) is
the industry’s first ‘Balanced Oscillator’ utilizing
analog multiplication of the fundamental frequency
(at double or quadruple frequency), combined with
an attenuation of the fundamental of the reference
crystal, without the use of a phase-locked loop
(PLL), in CMOS technology.
•
•
•
•
PhaseLink’s patent pending PL560-xx family of AFM
products can achieve up to 800 MHz output
frequency with little jitter or phase noise
deterioration. In addition, the low frequency input
crystal requirement makes the AFMs the most
affordable high-performance timing-source in the
market.
•
PL560-xx family of products utilize low-power CMOS
technology and are housed in GREEN/ RoHS
compliant 16-pin TSSOP, and 16-pin 3x3 QFN
packages.
•
•
•
•
•
•
•
•
Non-PLL frequency multiplication
Input frequency from 30-200 MHz
Output frequency from 60-800 MHz
Low phase noise and jitter (equivalent to fundamental
crystal at the output frequency)
Ultra-low jitter
o RMS phase jitter < 0.25 ps (12kHz-20MHz)
o RMS period jitter < 2.5 ps
Low phase noise
o -142 dBc/Hz @100kHz offset from 155.52 MHz
o -150 dBc/Hz @10MHz offset from 155.52 MHz
High linearity pull range (typ. 5%)
+/- 120 PPM pullability VCXO
Low input frequency eliminates the need for expensive
crystals
Differential output levels (PECL, LVDS), or singleended CMOS
Single 2.5V or 3.3V +/- 10% power supply
Optional industrial temperature range (-40°C to +85°C)
Available in 16-pin GREEN/RoHS compliant TSSOP,
and 3x3 QFN
Figure 1: 2x AFM Phase Noise at 311.04MHz
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Analog Frequency Multiplier
PL560-xx VCXO Family
L2X
VCON
OE
X IN
O s c illa to r
A m p lifie r
XOUT
QBAR
F re q u e n c y
X2
F re q u e n c y
X4
Q
O n ly r e q u ir e d in x 4 d e s ig n s
L4X
Figure 2: Block Diagram of VCXO AFM
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 311.04 MHz, while Figure 4 shows the very
low rejection levels of sub-harmonics that correspond to the exceptionally low jitter performance.
Figure 3: Period Jitter Histogram at 311.04 MHz
Analog Frequency Multiplier (2x)
with 155.52MHz crystal
Figure 4: Spectrum Analysis at 311.04 MHz
Analog Frequency Multiplier (2x)
with sub-harmonics below –72 dBc
OE LOGIC SELECTION
OUTPUT
OESEL
0 (Default)
PECL
1
0 (Default)
LVDS or CMOS
1
OE
Output State
0 (Default)
Enabled
1
Tri-state
0
Tri-state
1 (Default)
Enabled
0
Tri-state
1 (Default)
Enabled
0 (Default)
Enabled
1
Tri-state
OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. Internally set to default through pull-down / -up.
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Analog Frequency Multiplier
PL560-xx VCXO Family
PRODUCT SELECTION GUIDE
FREQUENCY VERSUS PHASE NOISE PERFORMANCE
Phase Noise at Frequency Offset From Carrier (dBc/Hz)
Input
Frequency
Range (MHz)
Analog
Frequency
Multiplication
Factor
Output
Frequency
Range (MHz)
Output
Type
PL560-08
75 - 200
4
300 - 800
PL560-09
75 - 200
4
PL560-37
30 - 80
PL560-38
30 - 80
PL560-39
Part
Number
Carrier
Freq.
(MHz)
10 Hz
100 Hz
1 KHz
10
KHz
100
KHz
1 MHz
10
MHz
PECL
622.08
-55
-85
-110
-130
-137
-148
-150
300 - 800
LVDS
622.08
-55
-85
-110
-130
-137
-148
-150
4
120 - 320
CMOS
155.52
-50
-82
-110
-128
-142
-148
-150
4
120 - 320
PECL
155.52
-50
-82
-110
-128
-142
-148
-150
30 - 80
4
120 - 320
LVDS
155.52
-50
-82
-110
-128
-142
-148
-150
PL560-47
30 - 80
2
60 - 160
CMOS
155.52
-65
-95
-122
-138
-142
-148
-149
PL560-48
30 - 80
2
60 - 160
PECL
155.52
-65
-95
-122
-138
-142
-148
-149
PL560-49
30 - 80
2
60 - 160
LVDS
155.52
-65
-95
-122
-138
-142
-148
-149
PL560-68
75 - 200
2
150 - 400
PECL
311.04
-60
-85
-112
-135
-142
-150
-151
PL560-69
75 - 200
2
150 - 400
LVDS
311.04
-60
-85
-112
-135
-142
-150
-151
Phase noise was measured using Agilent E5500.
FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
Part
Number
Output.
Freq.
(MHz)
RMS Period
Jitter
(ps)
Peak to Peak
Period Jitter
(ps)
RMS Accumulated
(L.T.) Jitter (ps)
Min. Typ. Max. Min. Typ. Max. Min. Typ.
RMS Phase Jitter
(12 KHz-20MHz)
(ps)
Max. Min.
Typ.
Spectral Specifications / Sub-harmonic Content
(dBc), Frequency (MHz)
Carrier @
@
@
@
@
@
Max. Freq. -75%
-50% -25% +25% +50% +75%
(Fc)
(Fc)
(Fc) (Fc)
(Fc) (Fc) (Fc)
PL560-08
622
4
6
25
30
6
0.09
622
-50
-50
-45
-47
-47
-55
PL560-09
622
4
6
25
30
6
0.09
622
-50
-50
-45
-47
-47
-55
PL560-37
155
2.5
3
18
20
3
0.25
155.52
-75
-62
-65
-75
PL560-38
155
2.5
3
18
20
3
0.25
155.52
-75
-62
-65
-75
PL560-39
155
2.5
3
18
20
3
0.25
155.52
-75
-62
-65
-75
PL560-47
155
2.5
3
18
20
3
0.25
155.52
-68
-68
PL560-48
155
2.5
3
18
20
3
0.25
155.52
-68
-68
PL560-49
155
2.5
3
18
20
3
0.27
155.52
-68
-68
PL560-68
311
2.5
3
18
20
3
0.18
311.04
-72
-85
PL560-69
311
2.5
3
18
20
3
0.18
311.04
-72
-85
Note: Wavecrest data 10,000 hits. No filtering was used in jitter calculations.
Agilent 5500 was used for phase jitter measurements.
Spectral specifications were obtained using Agilent E7401A.
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Rev.:02-09-07 Page 3
Analog Frequency Multiplier
PL560-xx VCXO Family
CRYSTAL SPECIFICATIONS AND BOARD LAYOUT CONSIDERATIONS
BOARD LAYOUT CONSIDERATIONS
AFM IC
AFM IC
XTAL
XIN (Pin # 4)
XIN (Pin # 4)
XTAL
XOUT (Pin # 5)
XOUT (Pin # 5)
Ceramic
SMD
To minimize parasitic effects, and improve performance:
• Place the crystal as close as possible to the IC.
• Make the board traces that are connected to the crystal pins symmetrical.
• The board trace symmetry is important, as it reduces the negative parasitic effects to produce a clean frequency multiplication with
low jitter. Parasitic effects reduce frequency pulling of the VCXO and increase jitter.
CRYSTAL SPECIFICATIONS & TUNING PERFORMANCE
CRYSTAL SPECIFICATIONS
PART
NUMBER
TUNING PERFORMANCE
CL (xtal)
CRYSTAL
RESONATOR
FREQUENCY
(FXIN)
MODE
75~200MHz
Fundamental
CONDITIONS
ESR
(RE)
TYP.
Max.
5pF
30 Ω
At
PL560-08/09
PL560-68/69
PL56037/38/39
PL56047/48/49
VCON
=
1.65V
At
30~80MHz
Fundamental
VCON
=
1.65V
5pF
30 Ω
CRYSTAL
TUNING (Typical)
CRYSTAL
FREQ
(MHz)
C0
C1
C0/C1
VC:
1.65V
0V
VC:
1.65V 3.4V
155.52
3.0pF
12.2fF
245
-145 ppm
+108 ppm
155.52
1.8pF
5.7fF
316
-134 ppm
+87 ppm
30.72
2.8pF
12.4fF
228
-167ppm
+176 ppm
30.72
4.5pF
19.1fF
236
-163 ppm
+167 ppm
38.88
5.1pF
20.9fF
242
-131 ppm
+98 ppm
38.88
5.3pF
25.6fF
207
-157 ppm
+141 ppm
77.76
2.0pF
6.7fF
305
-92 ppm
+110 ppm
Note: Non specified parameters can be chosen as standard values from crystal suppliers.
CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink.
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Analog Frequency Multiplier
PL560-xx VCXO Family
VOLTAGE CONTROL SPECIFICATION
PARAMETERS
VCXO Stabilization Time
SYMBOL
TVCXOSTB
CONDITIONS
MIN.
TYP.
MAX.
UNITS
10
ms
From power valid
VCXO Tuning Range
XTAL C 0 /C 1 <300
200
CLK Output Pullability
VCON= 1.65V ± 1.65V
XTAL C 0 /C 1 <300
±100
Linearity
0V < VCON < 3.3V, -3dB
ppm
±120
5
VCON Input Impedance
VCON Modulation BW
ppm
10
%
130
kΩ
25
kHz
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board
layout specifications. The listed values in this datasheet are based on the calculated parasitic values from
PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine
the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution.
To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software.
You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second
worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink’s board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their
design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor
values. Please use the following fine tuning procedure:
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Analog Frequency Multiplier
PL560-xx VCXO Family
Figure 5: Diagram Representation of the Related System Inductance and Capacitance
DIE SIDE
- Cinternal = Based on AFM device
- Cpad = 2.0 pF, Bond pad and its ESD circuitry
- C11 = 0.4 pF, The following amplifier stage
PCB side
- LWB1 = 2 nH, (2 places), Stray inductance
- Cstray = 1.0 pF, Stray capacitance
- L2X (L4X) = 2x or 4x inductor
- C2X (C4X) = range (0.1 to 2.7 pF), Fine tune
inductor if used
• There are two default variables that normally will not need to be modified. These are Cpad, and C11 and
are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively.
• LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a
leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of
these and they are assumed to be approximately symmetrical so you only need to enter this inductance
once in cell B23.
• Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a
leaded part is used.
• Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM
Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency.
• For 4X AFMs, repeat the same procedure in the L4X worksheet.
• See the examples in the following section.
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Analog Frequency Multiplier
PL560-xx VCXO Family
DETERMINING STRAY L’s AND C’s IN A LAYOUT
Figure 6: Diagram Representation of the Board Layout
Lets take the PL560-38 (4x VCXO) for example. This takes a crystal input in the range of 30 to 80 MHz and
multiplies it to an output of 120 to 320 MHz. To determine the stray L’s and C’s of the layout we will assemble
two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the upper
range of the device (320 MHz).
120 MHz AFM Tuning: Using the “AFM Tuning Assistant” find the PL560-3x in the L2X worksheet. Enter the
Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft
0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for
L4X at 120 MHz.
Results: L2X = 180 nH, L4X = 82 nH.
320 MHz AFM tuning: Repeat the previous procedure for L2X at 120 MHz and L4X at 320 MHz.
Results: L2X = 24 nH, L4X = 10 nH.
Proceed and assemble the test units.
Measuring 120 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6, above. While
power is applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the
2x port, the scope will show 60 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 30 MHz until
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Analog Frequency Multiplier
PL560-xx VCXO Family
the amplitude on the scope is maximum and record the generator frequency. For example, the peak is recorded
at 29.8x2 or 59.6 MHz.
Measuring 320 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6, above. While
power is applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the
2x port the scope will show 160 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 80 MHz
until the amplitude on the scope is maximum and record the generator frequency. For example, the peak is
recorded at 78.0 x 2 = 156 MHz
In the AFM Tuning Assistant, add the scope’s probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0
pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the
L2X value with 180 nH and see if it peaks at 59.6 MHz. If it does not, adjust Cstray until 59.4 MHz is achieved.
Again enter 24 nH for L2X and fine tune LWB1 for 156 MHz.
Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray capacitance)
Repeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH
peaks at 304 MHz.
Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray capacitance)
Internal Capacitor Selection by Device
Cinternal (pF)
Device Number
P560-0x
P560-3x
P560-4x
P560-6x
2X
4X
7.625
34.125
34.125
7.625
6.250
16.500
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Analog Frequency Multiplier
PL560-xx VCXO Family
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
Supply Voltage
MIN.
V DD
MAX.
UNITS
4.6
V
Input Voltage, DC
VI
GND-0.5
V DD +0.5
V
Output Voltage, DC
VO
GND-0.5
V DD +0.5
V
Storage Temperature
TS
-65
150
°C
Ambient Operating Temperature, Industrial Temperature
T A_I
-40
+85
°C
Ambient Operating Temperature, Commercial Temperature
T A_C
0
+70
°C
125
°C
260
°C
2
kV
Junction Temperature
TJ
Lead Temperature (soldering, 10s)
Input Static Discharge Voltage Protection
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent
damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the
device at these or any other conditions above the operational limits noted in this specification is not implied.
PECL ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
CONDITIONS
Supply Current (with loaded outputs)
IDD
Fout = 622 MHz
Operating Voltage
VDD
MIN.
TYP.
MAX.
UNITS
75
80
mA
3.63
V
55
%
2.25
Output Clock Duty Cycle
@ Vdd – 1.3V
45
50
Short Circuit Current
mA
±50
Output High Voltage
VOH
Output Low Voltage
VOL
RL = 50 Ω to
(VDD – 2V)
VDD – 1.025
V
VDD – 1.620
V
Clock Rise Time
tr
@20/80%
0.25
0.45
ns
Clock Fall Time
tf
@80/20%
0.25
0.45
ns
PECL Transition Time Waveform
DUTY CYCLE
PECL Levels Test Circuit
OUT
PECL Output Skew
VDD
45 - 55%
55 - 45%
OUT
OUT
50Ω
2.0V
80%
50%
20%
50Ω
OUT
OUT
tR
OUT
tF
tSKEW
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Analog Frequency Multiplier
PL560-xx VCXO Family
LVDS ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
Supply Current (with loaded outputs)
IDD
Operating Voltage
VDD
CONDITIONS
MIN.
Fout = 622 MHz
TYP.
MAX.
UNITS
55
60
mA
3.63
V
55
%
2.25
Output Clock Duty Cycle
@ 1.25V (LVDS)
45
50
Short Circuit Current
mA
±50
Output Differential Voltage
VDD Magnitude Change
VOD
247
∆VOD
-50
Output High Voltage
VOH
Output Low Voltage
VOL
Offset Voltage
355
454
mV
50
mV
1.6
V
1.4
RL = 100 Ω
(see figure)
0.9
1.1
VOS
1.125
1.2
1.375
V
Offset Magnitude Change
∆VOS
0
3
25
mV
Power-off Leakage
IOXD
±1
±10
µA
Output Short Circuit Current
IOSD
-5.7
-8
mA
Differential Clock Rise Time
tr
0.2
0.5
0.7
ns
Differential Clock Fall Time
tf
0.2
0.5
0.7
ns
Vout = VDD or GND
VDD = 0V
RL = 100 Ω
CL = 10 pF
(see figure)
V
LVDS Transition Time Waveform
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
0V (Differential)
OUT
CL = 10pF
50Ω
VOD
OUT
VOS
VDIFF
RL = 100Ω
80%
VDIFF
80%
0V
50Ω
CL = 10pF
OUT
20%
20%
OUT
tR
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Rev.:02-09-07 Page 10
Analog Frequency Multiplier
PL560-xx VCXO Family
CMOS ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
Supply Current, Dynamic, with
Loaded Outputs
I DD
Operating Voltage
V DD
CONDITIONS
MIN.
At 100MHz, load=15pF
TYP.
MAX.
UNITS
16
20
mA
3.63
V
2.25
Output High Voltage (LVTTL)
V OH3.3
I OH = -8.5mA, 3.3V Supplies
Output Low Voltage (LVTTL)
V OL3.3
I OL = 8.5mA, 3.3V Supplies
Output High Voltage (LVCMOS)
V OHC3.3
I OH = -4mA, 3.3V Supplies
V DD – 0.4
V
Output High Voltage
V OH2.5
I OH = 1mA, 2.5V Supplies
V DD – 0.2
V
Output Low Voltage
V OL2.5
I OL = 1mA, 2.5V Supplies
Output drive current
I OSD3.3
V OL = 0.4V, V OH = 2.4V
(per output), 3.3V Supplies
8.5
T r ,T f
10% ~ 90% VDD with 10 pF
load
1.2
1.6
ns
50
55
%
Output Clock Rise/Fall Time
Output Clock Duty Cycle
Short Circuit Current
Measured @ 50% VDD
IS
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2.4
V
0.4
0.2
45
±50
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V
V
mA
mA
Rev.:02-09-07 Page 11
Analog Frequency Multiplier
PL560-xx VCXO Family
BOARD DESIGN AND LAYOUT CONSIDERATIONS
L2X and L4X: Try to reduce the PCB trace
inductance to a minimum by placing L2X and L4X as
physically close to their respective pins as possible.
Also be sure to bypass each Vdd connection
especially taking care to place a 0.01 uF bypass at
the Vdd side of L2X and L4X (see recommended
layout).
Crystal connections: Be sure to keep the ground
plane under the crystal connections continuous so
that the stray capacitance is consistent on both
crystal connections. Also be sure to keep the crystal
connections symmetrical with respect to one another
and the crystal connection pins of the IC. If you
chose to use a series capacitance and or inductor to
fine tune the crystal frequency be sure to put
symmetrical pads for this cap on both crystal pins
(see Cadj in recommended layout), even if one of
the capacitors will be a 0.01 uF and the other is
used to tune the frequency. To further maintain a
symmetrical balance on a crystal that may have
more internal Cstray on one pin or the other, place
capacitor pads (Cbal) on each crystal lead to ground
(see recommended layout). R3rd is only required if
a 3 rd overtone crystal is used.
2X Layout (TSSOP)
V DD and GND: Bypass VDDANA and VDDBUF with
separate bypass capacitors and if a V DD plane is
used, feed each bypass cap with its own via. Be
sure to connect any ground pin including the bypass
caps with short via connections to the ground plane.
OESEL: J1 is recommended so the same PCB
layout can be used for both OESEL settings.
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Analog Frequency Multiplier
PL560-xx VCXO Family
6
DNC
GNDANA
13
VDDANA
OESEL
VDDOSC
12
VDDBUF
11
QBAR
7
10
Q
8
9
GNDBUF
L2X
9
8
14
7
P560-4X
15
16
6
1
2
3
4
5
3
14
OESEL
DNC
XIN
4
XOUT
5
OE
XOUT
13
OESEL
14
13
VDDANA
VDDOSC
15
12
VDDBUF
L2X
16
OE
6
11
QBAR
L4X
7
10
Q
VDDOSC
8
9
GNDBUF
2X AFM Package Pin Out
12
VDDANA
11
10
GNDBUF
VCON
QBAR
VDDOSC
GNDANA
Q
L2X
15
VDDBUF
GNDBUF
QBAR
Q
10
16
2
9
P560-0X
1
2
3
4
XIN
5
OE
OESEL
11
1
GNDOSC
VCON
XOUT
14
12
13
OSCOFFSEL
OSCOFF
SEL
GNDOSC
4
VDDANA
XIN
XIN
PLL560-4X
3
VDDOSC
VCON
15
2
VCON
L2X
16
PLL560-0X
GNDOSC
1
OSCOFF
SEL
GNDOSC
OSCOFFSEL
VDDBUF
PACKAGE PIN DESCRIPTION AND ASSIGNMENT
8
VDDOSC
7
L4X
6
OE
5
XOUT
4X AFM Package Pin Out
PIN ASSIGNMENTS
Pin#
Type
Product
OSCOFFSEL
1
I
2X & 4X
GNDOSC
2
P
2X & 4X
VCON
3
I
2X & 4X
XIN
4
I
2X & 4X
Set to “0” (GND) to choose to turn off the oscillator when outputs are disabled (OE). Default (no
connect) is OSC always on.
GND connection for oscillator circuitry.
Control Voltage input. Use this pin to change the output frequency by varying the applied Control
Voltage.
Input from crystal oscillator circuitry.
XOUT
5
O
2X & 4X
Output from crystal oscillator circuitry.
OE
6
I
2X & 4X
Output Enable input (see "OE LOGIC SELECTION TABLE").
Name
DNC
L4X
2X
7
I
8
P
GNDANA
VDDOSC
4X
Description
Do Not Connect.
External inductor connection. The inductor is recommended to be a high Q small
size 0402 or 0603 SMD component, and must be placed between L4X and adjacent
VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects
and to maintain inductor Q. This inductor is used with 4X AFMs.
2X
GND connection.
4X
VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other
VDDs whenever possible.
GNDBUF
9
P
2X & 4X
GND connection for output buffer circuitry.
Q
10
O
2X & 4X
PECL/LVDS or CMOS output.
QBAR
11
O
2X & 4X
VDDBUF
12
P
2X & 4X
VDDANA
13
P
2X & 4X
OESEL
14
I
2X & 4X
VDDOSC
15
P
2X & 4X
L2X
16
I
2X & 4X
Complementary PECL/LVDS output or in phase CMOS.
VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other
VDDs whenever possible.
VDD connection for analog circuitry. VDDANA should be separately decoupled from other VDDs
whenever possible.
Selector input to choose the OE control logic (see “OE SELECTION TABLE”). Internal pull-down.
VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other
VDDs whenever possible.
External inductor connection. The inductor is recommended to be a high Q small
size 0402 or 0603 SMD component, and must be placed between L2X and adjacent
VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects
and to maintain inductor Q.
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:02-09-07 Page 13
Analog Frequency Multiplier
PL560-xx VCXO Family
PACKAGE INFORMATION
16 PIN TSSOP
16 PIN TSSOP ( mm )
Symbol
A
A1
B
C
D
E
H
L
e
Min.
Max.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.40 BSC
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
e
L
B
16 PIN 3x3 QFN
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:02-09-07 Page 14
Analog Frequency Multiplier
PL560-xx VCXO Family
ORDERING INFORMATION
For part ordering, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Device number, Package type and Operating temperature range
PL560-XX X X X X
NONE= TUBE
R= TAPE AND REEL
PART NUMBER
NONE= NORMAL PACKAGE
L= GREEN PACKAGE
TEMPERATURE
C=COMMERCIAL
I=INDUSTRIAL
PACKAGE TYPE
O=TSSOP
Q= QFN 3x3
Order Number
PL560-XXOC
PL560-XXOC-R
PL560-XXOCL
PL560-XXOCL-R
PL560-XXQC
PL560-XXQC-R
PL560-XXQCL
PL560-XXQCL-R
Marking
P560-XX
P560-XX
P560-XX
P560-XX
P560-XX
P560-XX
P560-XX
P560-XX
OC
OC
OC
OC
QC
QC
QC
QC
Package Option
TSSOP – Tube
TSSOP – Tape and Reel
TSSOP (GREEN)– Tube
TSSOP (GREEN)– Tape and Reel
QFN – Tube
QFN – Tape and Reel
QFN (GREEN)– Tube
QFN (GREEN)– Tape and Reel
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, CA 94538 TEL (510) 492-0990, FAX (510) 492-0991
www.phaselink.com
Rev.:02-09-07 Page 15