(Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO FEATURES VDDOSC VDDANA VDDANA VDDDIG SEL0^ SEL1^ OUTSEL1^ • • • • • • • • 65 mil OUTSEL0v • DIE CONFIGURATION Less than 0.4ps RMS (12KHz-20MHz) phase jitter for all frequencies . Low phase noise output (@ 1MHz frequency offset ∗ -140dBc/Hz for 311.04MHz, ∗ -131dBC/Hz for 622.08MHz 19MHz-40MHz crystal input. 38MHz-640MHz output. Selectable PECL, LVDS, or CMOS outputs. No external varicap required. Output Enable selector. Wide pull range (+/-200ppm). 3.3V operation. Available in 3x3 QFN or 16-pin TSSOP packages. 25 24 23 22 21 20 19 18 XIN 26 XOUT 27 SEL2 28 DNC 29 OE_CTRL 30 VCON 31 62 mil • Die ID: 2222-22A C502A 3 4 5 6 7 8 LP LM DNC DNC GNDDIG GNDBUF X 2 GNDANA (0,0) Y 1 GNDOSC DESCRIPTION The PL580-30 is a monolithic low jitter and low phase noise VCXO, capable of 0.4ps RMS phase jitter and PECL, LVDS, or CMOS outputs, covering a wide frequency output range up to 640MHz. It allows the control of the output frequency with an input voltage (VCON), using a low cost crystal. The PL580-30 is designed to address the demanding requirements of high performance applications such as SONET, GPS, XDSL, etc. (1550,1475) 17 GNDBUF 16 CMOS 15 LVDSB 14 PECLB 13 VDDBUF 12 VDDBUF 11 PECL 10 LVDS 9 OE_SEL^ Note1: ^ Denotes internal pull up resistor. DIE SPECIFICATIONS Name Value Size Reverse side Pad dimensions Thickness 62 x 65 mil GND 80 micron x 80 micron 10 mil BLOCK DIAGRAM VCON VARICAP XIN XOUT XTAL OSC VCO Divider Phase Detector Charge Pump + Loop Filter VCO (F XiN x16) Perform ance Tuner Output Divider (1,2,4,8) QBAR Q OE 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 1 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO OUTPUT ENABLE LOGICAL LEVELS v OUTSEL0 (Pad #25) OUTSEL1^ (Pad #18) Selected Output 0 0 LVDS 0 1 PECL (Default) 1 0 High Drive CMOS 1 1 Standard Drive CMOS Note: For bonding convenience, ‘OUTSEL0’ incorporates an internal pull down resistor while ‘OUTSEL1’ incorporates an internal pull up resistor. OUTPUT SELECTION AND ENABLE OE_SEL^ (Pad #9) 0 1 (Default) OE_CTRL (Pad #30) State 0 (Default) Output enabled 1 Tri-state 0 Tri-state 1 (Default) Output enabled Pad #9: Bond to GND to set to “0”, bond to VDD to set to “1”, Pad #30: Logical states defined by PECL levels if OE_SELECT is “0” Logical states defined by CMOS levels if OE_SELECT is “1” FREQUENCY SELECTION TABLE SEL2 SEL1 SEL0 Selected Multiplier/Output Frequency 0 0 0 VCO Max* 0 0 1 VCO Min* 0 1 0 Reserved 0 1 1 Reserved 1 0 0 Fin x 2 1 0 1 Fin x 8 1 1 0 Fin x 16 1 1 1 Fin x 4 All SEL pads have internal pull-ups (default value is ‘1’). Bond to GND to set to 0. * Special Test Modes to help selecting the inductor value for the target output frequency. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 2 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO PAD ASSIGNMENT Pad # Name X (µm) Y (µm) Description 1 GNDOSC 248 109 Ground, Oscillator circuitry. 2 GNDANA 361 109 Ground, Analog circuitry. 3 LP 473 109 Performance/Frequency tuning Inductor. 4 LM 587 109 Performance/Frequency tuning Inductor. 5 DNC 702 109 Do No Connect. 6 DNC 874 109 Do No Connect. 7 GNDDIG 1042 109 Ground, Digital circuitry. 8 GNDBUF 1171 109 Ground, buffer circuitry. 9 OE_SELECT 1400 125 Used to select between PECL or CMOS logic states for OE. Incorporates internal pull up. 10 LVDS 1400 259 LVDS Output. 11 PECL 1400 476 PECL Output. 12 VDDBUF 1400 616 3.3V power supply, Buffer circuitry. 13 VDDBUF 1400 716 3.3V power supply, Buffer circuitry. 14 PECLB 1400 871 Complementary PECL Output. 15 LVDSB 1400 1089 Complementary LVDS Output. 16 CMOS 1400 1227 Single ended CMOS output. 17 GNDBUF 1389 1365 Ground, buffer circuitry. 18 OUTSEL1 1232 1365 Used to select CMOS, PECL or LVDS output type. Incorporates internal pull up. 19 SEL1 1042 1365 20 SEL0 854 1365 Used to select multiplication factor. Incorporates internal pull up. 21 VDDDIG 659 1365 3.3V power supply, Digital circuitry. 22 VDDANA 559 1365 3.3V power supply, Analog circuitry. 23 VDDANA 459 1365 3.3V power supply, Analog circuitry. 24 VDDOSC 358 1365 3.3V power supply, Oscillator circuitry. 25 OUTSEL0B 194 1365 Used to select CMOS, PECL or LVDS output type. Incorporates internal pull down. 26 XIN 109 1223 Crystal input. See crystal specification for details. 27 XOUT 109 1017 Crystal output. See crystal specification for details. 28 SEL2 109 858 Used to select multiplication factor. Incorporates internal pull up. 29 DNC 109 646 Do Not Connect 30 OE_CTRL 109 397 Used to enable/disable the output(s). See Output Selection and Enable table. 31 VCON 109 181 Voltage Control Input. 0V to 3.3V. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 3 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO PERFORMANCE TUNING & INDUCTOR VALUE SELECTION Please refer to PhaseLink’s ‘PhasorV Tuning Assistance’ software to automatically calculate the optimum inductor values for your application. In addition, the chart below could be used as a reference for quick inductor value selection. Please note that the inductor values mentioned in the table below, or when using ‘PhasorV Tuning Assistance’ are derived based on the parasitic values of PhaseLink’s evaluation board. For performance enhancement of your custom board design, please follow the following instruction: Use the special test modes “VCO Max” and “VCO Min” to determine the optimum inductor value. “VCO Max” represents the high end of the VCO range and “VCO Min” represents the low end of the VCO range. The output frequency in the “VCO Max” and “VCO Min” test modes is VCO/16. This means that the output frequencies are around the crystal frequency that will be used. The optimum inductor value is where the target crystal frequency is closest to the middle between the “VCO Max” and “VCO Min” output frequencies. In this case the VCO will lock in the middle of its tuning range with maximum margin on either side. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 4 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model MIN. V DD VI VO TS TA TJ -0.5 -0.5 -65 -40 MAX. UNITS 4.6 V DD +0.5 V DD +0.5 150 85 125 260 2 V V V °C °C °C °C kV Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating Crystal Pullability Recommended ESR SYMBOL CONDITIONS MIN. F XIN Parallel Fundamental Mode at VCON = 0V at VCON = 1.65V at VCON = 3.3V AT cut AT cut 19 C L (xtal) C 0 /C 1 (xtal) RE TYP. MAX. UNITS 40 MHz 17.7 9.5 5.4 pF 250 30 Ω Note: Crystal Loading rating: The listed numbers are for the IC only. Specify the crystal for the value at VCON = 1.65V and add the PCB & package parasitic. A round number (i.e. 12pF) can be achieved by adding external capacitors. Try to add the same value to XIN and XOUT, and please note, that frequency pulling and oscillator gain may decrease. 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * VCXO Tuning Range CLK output pullability VCXO Tuning Characteristic Pull range linearity VCON pin input impedance VCON modulation BW SYMBOL T VCXOSTB CONDITIONS From power valid F XIN = 19 – 40MHz; XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V VCON=1.65V, ±1.65V MIN. TYP. MAX. UNITS 10 ms 500 ppm 150 ppm ppm/V % ±200 10 0V ≤ VCON ≤ 3.3V, -3dB 60 25 kΩ kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 5 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 4. General Electrical Specifications PARAMETERS SYMBOL Supply Current, Dynamic (with Loaded Outputs) I DD Operating Voltage V DD CONDITIONS MAX. 65/45/30 100MHz<Fout<320MHz 80/60/40 320MHz<Fout<640MHz 90/70 2.97 45 45 45 @ 50% V DD (CMOS) @ 1.25V (LVDS) @ V DD – 1.3V (PECL) Output Clock Duty Cycle TYP. 38MHz<Fout<100MHz PECL/LVDS/CMOS PECL/LVDS MIN. Short Circuit Current 3.63 55 55 55 50 50 50 ±50 UNITS mA V % mA Note: CMOS operation is not advised above 200MHz with 15pF load; and 320MHz with 10pF load. 5. Jitter Specifications PARAMETERS Integrated jitter RMS Period jitter RMS Period jitter Peak-toPeak CONDITIONS FREQUENCY Integrated 12 kHz to 20 MHz With capacitive decoupling between VDD and GND. Over 10,000 cycles. With capacitive decoupling between VDD and GND. Over 10,000 cycles. MIN. TYP. MAX. 155.52MHz 311.04MHz 0.4 0.4 0.5 0.5 622.08MHz 77.76MHz 155.52MHz 0.4 2.5 3 0.5 4 5 311.04MHz 3 5 622.08MHz 6 8 77.76MHz 155.52MHz 311.04MHz 622.08MHz 18 20 25 40 30 30 30 50 UNITS ps ps ps 6. Phase Noise Specifications PARAMETERS Phase Noise relative to carrier (typical) FREQ. @10Hz @100Hz @1kHz @10kHz @100kHz @1M @10M 77.76MHz -66 -96 -124 -136 -132 -145 -149 155.52MHz -62 -92 -120 -132 -128 -144 -150 311.04MHz -59 -86 -116 -129 -124 -140 -148 622.08MHz -48 -80 -108 -118 -114 -131 -138 UNITS dBc/Hz Note: Phase Noise measured at VCON = 0V. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 6 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 7. LVDS Electrical Characteristics PARAMETERS SYMBOL Output Differential Voltage V DD Magnitude Change MIN. TYP. MAX. UNITS V OD 247 355 454 mV ∆V OD -50 50 mV 1.6 V Output High Voltage V OH Output Low Voltage V OL Offset Voltage CONDITIONS 1.4 R L = 100 Ω (see figure) 0.9 1.1 V OS 1.125 1.2 1.375 V Offset Magnitude Change ∆V OS 0 3 25 mV Power-off Leakage I OXD ±1 ±10 uA Output Short Circuit Current I OSD -5.7 -8 mA V out = V DD or GND V DD = 0V V 8. LVDS Switching Characteristics PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Differential Clock Rise Time tr 0.2 0.7 1.0 ns Differential Clock Fall Time tf R L = 100 Ω C L = 10 pF (see figure) 0.2 0.7 1.0 ns LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT CL = 10pF 50Ω VOD VDIFF VOS RL = 100Ω 50Ω CL = 10pF OUT OUT LVDS Transistion Time Waveform OUT 0V (Differential) OUT 80% VDIFF 80% 0V 20% 20% tR tF 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 7 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO 9. PECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. Output High Voltage V OH V DD – 1.025 Output Low Voltage V OL R L = 50 Ω to (V DD – 2V) (see figure) MAX. UNITS V V DD – 1.620 V 11. PECL Switching Characteristics PARAMETERS SYMBOL FREQ. Clock Rise & Fall Times CONDITIONS <150MHz >150MHz <320MHz tr & tf Clock Rise & Fall Times Clock Rise & Fall Times @20/80% - PECL @80/20% - PECL >320MHz PECL Levels Test Circuit OUT TYP. MAX. 0.2 0.5 0.7 0.2 0.4 0.55 0.2 0.3 0.45 TYP. MAX. UNITS ns PECL Output Skew OUT VDD 50Ω MIN. 2.0V 50% 50Ω OUT tSKEW OUT PECL Transistion Time Waveform DUTY CYCLE 45 - 55% 55 - 45% OUT 80% 50% 20% OUT tR tF 11. CMOS Electrical Characteristics PARAMETERS Output drive current SYMBOL I OH I OL CONDITIONS V OH = V DD -0.4V, V DD =3.3V V OL = 0.4V, V DD = 3.3V MIN. 30 30 UNITS mA mA Output Clock Rise/Fall Time 0.3V ~ 3.0V with 15 pF load 0.7 ns Output Clock Rise/Fall Time 20%-80% with 50Ω Load 0.3 ns 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 8 (Preliminary) PL580-30 38MHz-640MHz Low Phase Noise VCXO ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL580-30 X C PART NUMBER PACKAGE TYPE D= Die TEMPERATURE C=COMMERCIAL I=INDUSTRAL Order Number Marking Package Option PL580-30DC P580-30DC Die (Waffle Pack) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 11/30/05 Page 9