ie (Preliminary) 19MHz to 800MHz Low Phase-Noise XO FEATURES < 0.5ps RMS phase jitter (12kHz to 20MHz) at 622.08MHz 30ps max peak to peak period jitter 8bit Switch Capacitor for ±50PPM crystal CLoad tuning о Load Capacitance Tuning Range: 8pF to 12pF Ultra Low-Power Consumption о < 90 mA @622MHz PECL output о <10A at Power Down (PDB) Mode Input Frequency: о Fundamental Crystal: 19MHz to 40MHz Output Frequency: о 19MHz to 800MHz output. Output types: LVPECL. Programmable OE input polarity selection. Power Supply: 3.3V, ±10% Operating Temperature Ranges: о Commercial: 0C to 70C о Industrial: -40C to 85C Available in Die or Wafer DESCRIPTION The PL685 is a Dual LC core monolithic IC clock, capable of maintaining sub-1ps RMS phase jitter, while covering a wide frequency output range up to 800MHz, without the use of external components. The high performance and high frequency output is achieved using a low cost fundamental crystal of between 19MHz and 40 MHz. The PL685 is designed to address the demanding requirements of high performance applications such as Fiber Channel, serial ATA, Ethernet, SAN, SONET/SDH, etc. PAD CONFIGURATION 65 mil (1650,2250) 8 SCLK 7 9 Die ID 6 VDD_ANA 5 VDD_DIG 4 VDD_BUF QB OE/PDB/ SDIO 10 DNC 11 GND_ANA 12 3 GND_DIG 13 2 VDD_BUF GND_BUF 14 1 Q (0,0) PL685 DIE SPECIFICATIONS Name Size Reverse side Pad dimensions Thickness Value 65 x 88.6 mil GND 80 micron x 80 micron 8 mils OUTPUT ENABLE CONTROL OE Select (Programmable) 0 1 (Default) OE State 0 (Default) 1 0 1 (Default) Output enabled Tri-state Tri-state Output enabled BLOCK DIAGRAM 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/24/11 Page 1 ie (Preliminary) 19MHz to 800MHz Low Phase-Noise XO PAD ASSIGNMENT Name Pad # X (m) Y (m) Description Q 1 1551 220 Output buffer VDD_BUF 2 1551 448 VDD connection for buffer circuitry QB 3 676 Output buffer VDD_BUF 4 1551 1551 1390 VDD connection for buffer circuitry VDD_DIG 5 1551 1552 VDD connection for digital circuitry VDD_ANA 6 1551 1790 VDD connection for analog circuitry XOUT 7 1503 2156 Output connection to crystal XIN 8 630 2156 Crystal input connection SCLK 9 99 2060 OE/PDB/SDIO 10 99 1256 DNC 11 99 970 Do not connect GND_ANA 12 99 700 GND connection for analog circuitry GND_DIG 13 99 532 GND connection for digital circuitry GND_BUF 14 99 364 GND connection for buffer circuitry The serial interface uses this pin for the serial clock input (SCLK), during programming. This pin may be programmed as output enable (OE), or powerdown (PDB) pin. The serial interface uses this pin for the serial data input (SDIO) during programming. This pin incorporates an Internal pull-up resistor of 60KΩ for OE, PDB operations. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/24/11 Page 2 ie (Preliminary) 19MHz to 800MHz Low Phase-Noise XO FUNCTIONAL DESCRIPTION PL685 family of products is an advanced, programmable LCVCO clock IC that is designed to meet the most stringent performance specifications for phase noise, jitter, and power consumption. There are two main types of VCOs, a) Ring Oscillator, b) LC Tank oscillator. An LCVCO is made up of an LC tank oscillator. Although a Ring Oscillator has very good performance, and has a good tuning range, its phase noise and jitter performance, in particular at higher frequencies, degrades. On the other hand, an LCVCO has an outstanding phase noise and jitter performance, even at higher frequencies. PhaseLink’s PL685 family of products takes advantage of this state of the art technology, and incorporates the LC tank on-chip, for optimal performance. PL685 family of products exhibit very low phase noise/phase jitter and peak to peak jitter, wide tuning range, and very low-power. All members of the PL685 family accept a low-cost fundamental crystal input of 19MHz to 40MHz or a reference clock input of up to 800MHz and its flexible core is capable of producing any output frequency between 19MHz to 800MHz. PLL Programming The PLL in the PL685 family is fully programmable. The PLL is equipped with a Prescaler to divide down the VCO frequency, and a 5-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 4-bit post VCO divider (PCounter), to achieve the desired output frequency. OE (Output Enable) The OE pin in PL685 family, through programming, can be configured to support OE pin activation with a logic ‘1’ or logic ’0’, to provide you with the desired enable polarity. OE Select (Programmable) 0 1 (Default) OE State 0 (Default) 1 0 1 (Default) Output enabled Tri-state Tri-state Output enabled The OE pin incorporates a 60K Ω resistor to either pull-up or pull-down to the default state when the OE pin is left open. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/24/11 Page 3 ie (Preliminary) 19MHz to 800MHz Low Phase-Noise XO ELECTRICAL SPECIFICATIONS 1. ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL Supply Voltage MIN V DD MAX UNITS 4.6 V Input Voltage, dc VI -0.5 V DD +0.5 V Output Voltage, dc VO -0.5 V DD +0.5 V Storage Temperature TS -65 150 C Ambient Operating Temperature (industrial temperature)* T AI -40 85 C Ambient Operating Temperature (commercial temperature) T AC 0 70 C Junction Temperature TJ 125 C ESD Protection, Machine Model 200 V 2 kV ESD Protection, Human Body Model Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only. 2. GENERAL ELECTRICAL SPECIFICATIONS PARAMETERS MAX UNITS LVPECL, 622.08MHz, 3.3V 90 mA Supply Current, Dynamic PDB Enabled PDB = 0, 3.3V 10 uA Output Enable Time t OE OE logic 0 to logic 1, Ta=25º C. Add one clock period to this measurement for a usable clock output. 50 ns Power Up Time T PU PDB logic 0 to logic 1, Ta=25º C 10 ms Operating Voltage V DD 3.63 V Power Up Ramp Rate t PU 100 ms Auto-Calibration Time t AC 10 ms 55 % Supply Current, Dynamic Output Clock Duty Cycle SYMBOL I DDQ CONDITIONS MIN 2.97 Time for V DD to reach 90% V DD . Power ramp must be monotonic. At power up @ V DD – 1.3V 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 TYP 3.3 0.1 45 www.phaselink.com 50 Rev 06/24/11 Page 4 ie (Preliminary) 19MHz to 800MHz Low Phase-Noise XO 4. CRYSTAL SPECIFICATIONS PARAMETERS SYMBOL CONDITIONS MIN Crystal Resonator Frequency F XIN Parallel Fundamental Mode Crystal Cload C L_Crystal V DD = 3.3V, programmable Shunt Capacitance C 0_Crystal Recommended ESR RE TYP MAX UNITS 19 40 MHz 8 12 pF 3.5 pF 50 Ω MAX UNITS AT cut 5. JITTER SPECIFICATIONS PARAMETERS FREQUENCY CONDITIONS RMS Phase Jitter 622.08MHz 10kHz to 20MHz, XIN=38.88MHz 0.5 ps Period Jitter, Pk-to-Pk 622.08MHz 10K cycles, XIN=38.88MHz 30 ps 6. PHASE NOISE SPECIFICATIONS Freq. @ PARAMETERS (MHz) 10Hz Phase Noise, relative to carrier (typical) @ 100Hz @ 1KHz MIN @ @ 10KHz 100KHz TYP @ 1MHz @ 10MHz 155.52 -58 -95 -119 -124 -129 135 148 622.08 -56 -87 -106 -111 -115 -125 -145 UNITS dBc/Hz 7. LVPECL OUTPUTS (Q, QB) PARAMETERS SYMBOL Output High Voltage V OH Output Low Voltage V OL Output Frequency Output Rise, Fall Times Output Voltage Swing F out tr, tf V pp LVPECL Levels Test Circuit OUT CONDITIONS Q, QB Standard LVPECL Termination, V DD = 3.3V 3.3V 20% - 80% of Q pp /QB pp Q, QB TYP MAX UNITS 2.275 2.350 2.420 V 1.490 1.600 1.680 V 200 800 800 300 900 MHz ns mV 19 550 LVPECL Transistion Time Waveform LVPECL Output Skew VDD MIN DUTY CYCLE OUT 45 - 55% 50? 55 - 45% 2.0V 50% OUT 80% 50? 50% OUT OUT tSKEW 20% OUT tR 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 tF www.phaselink.com Rev 06/24/11 Page 5 ie (Preliminary) 19MHz to 800MHz Low Phase-Noise XO ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Road, San Jose, CA, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type, Thickness and Operating temperature range Output Frequency Range Packaging Option PECL PL685-88DC ≤800MHz Waffle Pack (Die) PL685-88WC ≤800MHz Wafer Order Number P/N PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 2880 Zanker Road, San Jose, CA 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 06/24/11 Page 6