(Preliminary) Analog Frequency Multiplier PL565-78 for 491.52 MHz Wireless Base Station VCXO Family PRODUCT DESCRIPTION FEATURES PhaseLink’s Analog Frequency Multiplier (AFM) is the industry’s first ‘Balanced Oscillator’ utilizing analog multiplication of the fundamental frequency (at quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without the use of a phase-locked loop (PLL), in CMOS technology. • • • • • PhaseLink’s world’s best performing AFM products can achieve up to 800 MHz output frequency with little jitter or phase noise deterioration. • • • • • • • PL565-78, however, is custom designed to meet the stringent phase noise requirements of wireless base station applications, operating at 491.52 MHz. Non-PLL frequency multiplication by 4. Input frequency: 122.88 MHz Output frequency: 491.52 MHz Low phase noise and jitter (equivalent to fundamental crystal at the output frequency) Ultra-low jitter o RMS phase jitter < 100 fs (12kHz-20MHz) o RMS random period jitter < 2 ps Low phase noise o -65 dBc/Hz @10Hz offset from the carrier o -96 dBc/Hz @100Hz offset from the carrier High linearity pull range (typ. 5%) VCXO, set pullability ±100ppm ~ ±150ppm Differential output levels: LVPECL Single 3.3V, ±10% power supply Operating temperature range: -40°C to +85°C Available in 3x3mm QFN-16L package. PL565-78 Block Diagram L2X VCON OE X IN O s c illa to r A m p lifie r XOUT F re q u e n c y X2 F re q u e n c y X4 QBAR Q L4X 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 1 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO Name R-BIAS GNDOSC VCON XIN XOUT OE L4X VDDOSC GNDBUF PECL PECLB VDDBUF VDDANA OESEL VDDOSC L2X 15 L2X 16 QFN Pin # Type 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 I P I I O I I P P O O P P I P I GNDBUF PECL 10 9 P565565-78 1 2 3 4 XIN VDDOSC 11 VCON 14 PECLB OESEL 12 GNDOSC 13 R-BIAS VDDANA VDDBUF PIN ASSIGNMENT AND DESCRIPTION 8 VDDOSC 7 L4X 6 OE 5 XOUT Description External bias resistor connection GND connection Control voltage input Crystal Input pad Crystal Output pad Output Enable input External inductor connection VDD connection GND connection LVPECL output LVPECL complementary output VDD connection VDD connection OE style selection pin VDD connection External inductor connection 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 2 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO AFM Phase Noise at 491.52MHz, using 122.88MHz crystal AFM Spectrum at 491.52MHz, using 122.88MHz crystal The analog frequency multiplication preserves the low phase noise of the quartz crystal oscillator while keeping unwanted sub harmonics from the multiplication at very low levels. Sub harmonics appear only at large distance from the carrier, far outside the loop bandwidth of a PLL that uses the AFM signal to multiply up further to a multiple GHz network clock. This means the impact of the sub harmonics on the application is negligible. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 3 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO PHASE NOISE PERFORMANCE Part Number Input Freq. (MHz) Output Freq. (MHz) Phase Noise at Frequency Offset From Carrier (dBc/Hz) 10Hz PL565-78 122.88 491.52 -64 Phase noise was measured using Agilent E5052B. 100Hz 1kHz 10kHz 100kHz 1MHz 10MHz -96 -123 -135 -141 -150 -155 Phase Jitter 12KHz ~ 20MHz (ps) 0.05 SUB-HARMONIC PERFORMANCE Output Input Part Frequency Frequency Number (MHz) (MHz) Spectral Specifications / Sub-harmonic Content (dBc), Freq. (MHz) @ -75%(Fc) @ -50%(Fc) -60 -40 PL565-78 122.88 491.52 Note: Spectral specifications were obtained using Agilent E7401A @ -25%(Fc) -70 @ @ @ +25%(Fc) +50%(Fc) +75%(Fc) -70 -40 -70 AFM MULTIPLYING TECHNIQUE The analog frequency multiplication is achieved through a “squaring” operation. The math is as follows: SIN²(x) = 0.5 - 0.5×COS(2x) A very important property of this processing is that the result is a pure sine wave with double frequency. In theory there are no sub harmonics but in practice the squaring operation is not perfect and a low level of sub harmonics is present anyway. The key is that the resulting sub harmonics are very low and simple filtering with only one inductor per squarer is adequate for excellent performance. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 4 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO APPLICATION CIRCUIT RECOMMENDED PCB LAYOUT • Avoid ground planes underneath the crystal and inductor traces to limit parasitic capacitance. • Add bypass capacitor close to VDDBUF pin. • Avoid bypass capacitors near VDDOSC pins to lower cross-talk of unwanted frequencies. • L1X(a,b) can be used to increase the VCXO pulling range. Using ferrite core inductors limits the oscillation amplitude which can have a positive effect on phase noise. • L2X and L4X tune the frequency multiplier tank circuits. They need to be wire wound inductors with high Q-factor, preferably >20. • The large center pad is the “thermal relief” pad and can be connected to ground. TYPICAL COMPONENT VALUES FOR 491.52MHz OPERATION: L1Xa = L1Xb = 100nH for typical +140/-130ppm Frequency Pulling with Crystal C1=6fF and C0=2pF L2X = 36 nH , Coilcraft 0402CS or 0402HP L4X = 9.5 nH , Coilcraft 0402CS or 0402HP R-BIAS = 300 Ω 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 5 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO INDUCTOR VALUE OPTIMIZATION The required inductor values for the best performance depend on the operating frequency, and the board layout or module specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X / L4X and adjacent VDDOSC pin. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. To assist with the inductor value optimization, PhaseLink has developed AFM “Tuning Assistant” documents. You can download these documents from PhaseLink’s web site (www.phaselink.com). The documents consist of tables with recommended inductor values for certain output frequency ranges. Figure 10: Diagram Representation of the Related System Inductance and Capacitance DIE SIDE - Cinternal at L2X = 7.625 pF , at L4X = 6.25 pF - Cpad = 1.0 pF, Bond pad and its ESD circuitry - C11 = 0.4 pF, The following amplifier stage PCB side - LWB1 = 2 nH, (2 places), Stray inductance - Cstray = 0.5 pF, Stray capacitance - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7 pF), Fine tune the tank, if used. Work out the resonance of this network and you have a good first guess for the required inductor values for optimum performance. Non-linear behavior at large signal amplitudes can shift the tank resonance significantly, especially at the L2X side, to a lower frequency than the calculation suggests. The Tuning Assistant documents are based upon actual lab tests and are corrected for the non-linear behavior. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 6 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS SYMBOL Supply Voltage MIN. V DD MAX. UNITS 4.6 V Input Voltage, DC VI GND-0.5 V DD +0.5 V Output Voltage, DC VO GND-0.5 V DD +0.5 V Storage Temperature TS -65 150 °C Ambient Operating Temperature, Industrial T A_I -40 +85 °C Ambient Operating Temperature, Commercial T A_C 0 +70 °C 125 °C 260 °C 2 kV Junction Temperature TJ Lead Temperature (soldering, 10s) Input Static Discharge Voltage Protection (HBM) Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied . VOLTAGE CONTROL SPECIFICATION PARAMETERS VCXO Stabilization Time SYMBOL T VCXOSTB CONDITIONS MIN. From power valid VCXO Tuning Range* XTAL C 0 /C 1 <300 200 CLK Output Pullability* VCON= 1.65V, ± 1.65V XTAL C 0 /C 1 <300 ±100 Linearity UNITS 10 ms ppm ±120 130 0V < VCON < 3.3V, -3dB MAX. ppm 5 VCON Input Impedance VCON Modulation BW TYP. 10 % kΩ 40 kHz * Note: The VCXO Tuning Range and Pullability can be controlled with the value for inductor L1X. See Tuning Assistant document for a guide to chose the L1X value based upon crystal frequency and motional parameters. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 7 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO LVPECL ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS Supply Current, loaded outputs I DD Fout = 491.52MHz Operating Voltage V DD MIN. TYP. MAX. UNITS 75 80 mA 3.63 V 55 % 2.97 Output Clock Duty Cycle @V DD –1.3V 45 50 Short Circuit Current mA ±50 Output High Voltage V OH Output Low Voltage V OL R L = 50Ω to (V DD – 2V) Clock Rise Time tr @ 20/80% Clock Fall Time tf @ 80/20% LVPECL Levels Test Circuit V DD -1.025 V V DD -1.620 V 0.25 0.45 ns 0.25 0.45 ns LVPECL Transistion Time Waveform DUTY CYCLE OUT VDD 50? 2.0V 45 - 55% 55 - 45% OUT 80% 50% 50? 20% OUT OUT tR tF OE LOGIC SELECTION OESEL 0 (Default) 1 OE Output State 0 (Default) Enabled 1 Tri-state 0 Tri-state 1 (Default) Enabled 0 (Default): Connect to GND or leave floating to set to “0”. Internal pull-down. 1 (Default): Connect to VDD or leave floating to set to “1”. Internal pull-up. 0: Connect to GND to set to “0”. 1: Connect to VDD to set to “1”. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 8 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO PACKAGE INFORMATION QFN-16L Max A 0.70 0.75 0.80 A1 0.00 - 0.05 D1 DED Nom 0.20 A3 b 0.20 0.25 0.30 D 2.95 3.00 3.05 E 2.95 3.00 3.05 D1 1.65 1.70 1.75 E1 1.65 1.70 1.75 L 0.250 0.300 0.350 e L Dimension (mm) Min DDD E1 Symbol e Pin1 Dot b A A3 0.50BSC SEATING PLANE A1 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 9 (Preliminary) Analog Frequency Multiplier PL565-78 AFM VCXO ORDERING INFORMATION For part ordering, please contact our Sales Department: 2880 Zanker Rd., San Jose, CA 95134, USA Tel: (408) 571-1668 Fax: (408) 571-1688 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range PL565-78 X X X PART NUMBER R= TAPE AND REEL PACKAGE TYPE Q= QFN TEMPERATURE C=COMMERCIAL Order Number PL565-78QC Marking P565 78 LLL Package Option* QFN – Tape & Reel *Note: LLL represent the production lot number PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 2880 Zanker Rd., San Jose, California 95134 Tel (408) 571-1668 Fax (408) 571-1688 www.phaselink.com Rev 9/2/11 Page 10