Analog Frequency Multiplier

Analog Frequency Multiplier
PL663-xx XO Families
DESCRIPTION
PhaseLink’s Analog Frequency Multipliers TM
(AFMs) are the industry’s first “Balanced Oscillator”
utilizing analog multiplication of the fundamental
frequency (at double or quadruple frequency),
combined with an attenuation of the fundamental of
the reference crystal, without using a phase-locked
loop (PLL), in CMOS technology.
PhaseLink’s patent pending PL663-xx family of
AFM products can achieve up to 800 MHz
differential LVPECL, LVDS, or single-ended
LVCMOS output with little jitter or phase noise
deterioration.
PL663-xx family of products utilizes a low-power
CMOS technology and is housed in GREEN/ RoHS
compliant 16-pin TSSOP and 3x3 QFN packages.
FEATURES
• Non-PLL frequency multiplication
• Input frequency from 30-200 MHz
• Output frequency from 60-800 MHz
• Low phase noise and jitter (equivalent to fundamental
at the output frequency)
• Ultra-low jitter
o RMS phase jitter < 0.25 ps (12 kHz to 20 MHz)
o RMS period jitter < 2.5 ps typ.
• Low phase noise
o -145 dBc/Hz @ 100 kHz offset from 155.52 MHz
o -150 dBc/Hz @ 10 MHz offset from 155.52 MHz
• Low input frequency eliminates the need for expensive
crystals
• Differential LVPECL/LVDS, or single-ended LVCMOS
output
• Single 2.5V or 3.3V +/- 10% power supply
• Optional industrial temperature range (-40°C to
+85°C)
• Available in 16-pin GREEN/RoHS compliant TSSOP,
and 16-pin 3x3 QFN packages.
Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3rd overtone crystal)
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Rev. 02/18/10 Page 1
Analog Frequency Multiplier
PL663-xx XO Families
L2X
OE
X IN
R
O s c illa t o r
A m p lif ie r
XOUT
QBAR
F re q u e n c y
X2
F re q u e n c y
X4
Q
O n ly r e q u ir e d in x 4 d e s ig n s
L4X
Figure 2: Block Diagram of AFM XO
Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while Figure 4
shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e. low jitter).
Figure 3: Period Jitter Histogram at 212.5MHz
Analog Frequency Multiplier (2x),
with 106.25 MHz crystal
Figure 4: Spectrum Analysis at 212.5MHz
Analog Frequency Multiplier (2x),
with sub-harmonics below –69dBc
OE LOGIC SELECTION
OUTPUT
OESEL
0 (Default)
LVPECL
1
0 (Default)
LVDS or LVCMOS
1
OE
Output State
0 (Default)
1
0
1 (Default)
0
1 (Default)
0 (Default)
1
Enabled
Tri-state
Tri-state
Enabled
Tri-state
Enabled
Enabled
Tri-state
OESEL and OE: Connect to V DD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.]
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Rev. 02/18/10 Page 2
Analog Frequency Multiplier
PL663-xx XO Families
PRODUCT SELECTOR GUIDE
FREQUENCY VERSUS PHASE NOISE PERFORMANCE
Phase Noise at Frequency Offset From Carrier (dBc/Hz)
Input
Frequency
Range
(MHz)
Analog
Multiplication
Factor
Output
Frequency
Range
(MHz)
Output
Type
PL663-07
30 - 80
2
60 to 160
PL663-08
30 - 80
2
PL663-17
75 - 140
PL663-18
Part
Number
Carrier
Freq.
(MHz)
10Hz
100Hz
1KHz
10KHz
100KHz
1MHz
10MHz
LVCMOS
156.25
-75
-105
-130
-140
-145
-150
-150
60 to 160
LVPECL
156.25
-75
-105
-130
-140
-145
-150
-150
2
150 to 280
LVCMOS
212.5
-70
-100
-130
-140
-145
-148
-148
75 - 140
2
150 to 280
LVPECL
212.5
-70
-100
-130
-140
-145
-148
-148
PL663-19
75 - 140
2
150 to 280
LVDS
212.5
-70
-100
-130
-140
-145
-148
-148
PL663-28
140 - 160
2
280 to 320
LVPECL
311.04
-60
-92
-122
-140
-142
-146
-146
PL663-29
100 - 160
2
200 to 320
LVDS
311.04
-60
-92
-122
-140
-142
-146
-148
FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE
Part
Number
Output
Freq.
(MHz)
RMS Period
Jitter
(ps)
Peak to Peak
Period Jitter
(ps)
RMS
Accumulated
(L.T.) Jitter (ps)
Min. Typ. Max. Min. Typ. Max. Min. Typ.
Max.
Phase Jitter
(12 KHz-20MHz)
(ps)
Min.
Typ.
Max.
Spectral Specifications / Sub-harmonic Content
(dBc)
Frequency (MHz)
Carrier
Freq.
MHz
(Fc)
@
-75%
(Fc)
@
-50%
(Fc)
@
-25%
(Fc)
@
+25%
(Fc)
@
+50%
(Fc)
PL663-07
156.25
2
3
18
20
3
0.24
156.25
-70
-75
PL663-08
156.25
2
3
18
20
3
0.24
156.25
-70
-75
PL663-17
212.50
2.5
4
18
20
4
0.19
212.50
-70
-75
PL663-18
212.50
2.5
4
18
20
4
0.19
212.50
-70
-75
PL663-19
212.50
2.5
4
18
20
4
0.19
212.50
-70
-75
PL663-28
311.04
2.5
4
18
20
4
0.16
311.04
-65
-70
PL663-29
311.04
2.5
4
18
20
4
0.16
311.04
-65
-70
@
+75%
(Fc)
Note: Wavecrest data 10,000 hits. No Filtering was used in Jitter Calculations.
Agilent E5500 was used for phase jitter measurements.
Spectral specifications were obtained using Agilent E7401A.
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Rev. 02/18/10 Page 3
Analog Frequency Multiplier
PL663-xx XO Families
BOARD LAYOUT CONSIDERATIONS AND CRYSTAL SPECIFICATIONS
BOARD LAYOUT CONSIDERATIONS
To minimize parasitic effects and improve performance, do the following:
• Place the crystal as close as possible to the IC.
• Make the board traces that are connected to the crystal pins symmetrical. The board trace symmetry is
very important, as it reduces the negative parasitic effects to produce clean frequency multiplication with
low jitter.
CRYSTAL SPECIFICATIONS
CL (xtal)
ESR(RE)
C0
Typical
Max.
Max.
Fundamental or
3rd overtone
5 pF
30Ω
4.5 pF
75 to 140MHz
Fundamental or
3rd overtone
5 pF
60Ω
4.0 pF
140 to 200MHz
Fundamental or
3rd overtone
5 pF
60Ω
4.0 pF
Crystal Resonator
Frequency (FXIN)
Mode
PL663-07
PL663-08
30 to 80MHz
PL663-17
PL663-18
PL663-19
PL663-28
PL663-29
Part Number
Note: Non-specified parameters can be chosen as standard values from crystal suppliers.
CL ratings larger than 5pF require a crystal frequency adjustment.
Request detailed crystal specifications from PhaseLink.
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Rev. 02/18/10 Page 4
Analog Frequency Multiplier
PL663-xx XO Families
EXTERNAL COMPONENT VALUES
INDUCTOR VALUE OPTIMIZATION
The required inductor value(s) for the best performance depends on the operating frequency, and the board
layout specifications. The listed values in this datasheet are based on the calculated parasitic values from
PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine
the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution.
To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software.
You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two
worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second
worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value.
For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to
determine the optimum values for the required inductors. This software is developed based on the parasitic
information from PhaseLink’s board layout and can be used to determine the required inductor and parallel
capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design,
we recommend to use the parasitic information of their board layout to calculate the optimized inductor values.
Please use the following fine tuning procedure:
Figure 5: Diagram Representation of the Related System Inductance and Capacitance
DIE SIDE
- Cinternal = Based on AFM Device
- Cpad = 2.0 pF, Bond pad and its ESD circuitry
- C11 = 0.4 pF, The following amplifier stage
PCB side
- LWB1 = 2 nH, (2 places), Stray inductance
- Cstray = 1.0 pF, Stray capacitance
- L2X = 2x inductor
- C2X = range (0.1 to 2.7), Fine tune inductor if used
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Rev. 02/18/10 Page 5
Analog Frequency Multiplier
PL663-xx XO Families
• There are two default variables that normally will not need to be modified. These are Cpad, and C11 and
are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively.
• LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a
leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of
these and they are assumed to be approximately symmetrical so you only need to enter this inductance
once in cell B23.
• Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a
leaded part is used.
• Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM
Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency.
Internal Capacitor Selection by Device
Device Number
Cinternal (pF)
PL663-0X
PL663-1X
PL663-2X
2X
46.500
14.625
14.625
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Rev. 02/18/10 Page 6
Analog Frequency Multiplier
PL663-xx XO Families
EXTERNAL COMPONENT VALUES – 3 RD OVERTONE RESISTOR SELECTIONS (R3rd)
This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and
the nearest “E12” resistor values versus frequency.
PL663-07/08
PL663-17/18/19
Freq.
(MHz)
R3rd
(C)
E12
Pick
KC
30
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
76
78
80
9,917
9,297
8,750
8,264
7,829
7,438
7,083
6,761
6,467
6,198
5,950
5,721
5,509
5,313
5,129
4,958
4,798
4,648
4,508
4,375
4,250
4,132
4,020
3,914
3,814
3,719
10
10
8.2
8.2
8.2
6.8
6.8
6.8
6.8
6.8
5.6
5.6
5.6
5.6
4.7
4.7
4.7
4.7
4.7
4.7
3.9
3.9
3.9
3.9
3.9
3.9
Freq.
(MHz)
R3rd
(C)
E12
Pick
KC
75
77.5
80
82.5
85
87.5
90
92.5
95
97.5
100
102.5
105
107.5
110
112.5
115
117.5
120
122.5
125
127.5
130
132.5
135
137.5
140
2,125
2,056
1,992
1,932
1,875
1,821
1,771
1,723
1,678
1,635
1,594
1,555
1,518
1,483
1,449
1,417
1,386
1,356
1,328
1,301
1,275
1,250
1,226
1,203
1,181
1,159
1,138
2.2
2.2
2.2
1.8
1.8
1.8
1.8
1.8
1.8
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
1.2
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PL663-28/29
Freq.
(MHz)
R3rd
(C)
E24
Pick
KC
140.0
142.0
144.0
146.0
148.0
150.0
152.0
154.0
156.0
158.0
160.0
162.0
164.0
166.0
168.0
170.0
172.0
174.0
176.0
178.0
180.0
182.0
184.0
186.0
188.0
190.0
192.0
194.0
196.0
198.0
200.0
915
902
890
878
866
854
843
832
821
811
801
790
780
770
759
749
740
730
720
711
701
692
683
674
665
656
647
639
630
622
614
0.91
0.91
0.91
0.91
0.91
0.82
0.82
0.82
0.82
0.82
0.82
0.82
0.75
0.75
0.75
0.75
0.75
0.75
0.75
0.68
0.68
0.68
0.68
0.68
0.68
0.68
0.62
0.62
0.62
0.62
0.62
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Rev. 02/18/10 Page 7
Analog Frequency Multiplier
PL663-xx XO Families
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
PARAMETERS
SYMBOL
Supply Voltage
MIN.
MAX.
UNITS
4.6
V
V DD
Input Voltage, DC
VI
GND-0.5
V DD +0.5
V
Output Voltage, DC
VO
GND-0.5
V DD +0.5
V
Storage Temperature
TS
-55
+150
°C
Industrial Ambient Operating Temperature
T A_I
-40
+85
°C
Commercial Ambient Operating Temperature
T A_C
0
+70
°C
125
°C
260
°C
Junction Temperature
TJ
Lead Temperature (soldering, 10s)
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the
device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other
conditions above the operational limits noted in this specification is not implied.
*Note: For performance reasons, some pins on this device do not meet PhaseLink’s standard ESD protection. Therefore, the ESD protection on this
device is classified as Class I HBM and Class A MM. Handling precaution is recommended.
LVPECL ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
TYP.
MAX.
UNITS
Supply Current (loaded outputs)
IDD
Fout = 212.5 MHz, 15pF Load
58
65
75
mA
Operating Supply Voltage
VDD
3.63
V
55
%
Output Clock Duty Cycle
2.25
@ VDD – 1.3V
45
50
Short Circuit Current
mA
±50
Output High Voltage
VOH
Output Low Voltage
VOL
RL = 50 U to
VDD – 2V
RL = 50 U to VDD – 2V
Clock Rise Time
tr
@20/80%
Clock Fall Time
tf
@80/20%
PECL Levels Test Circuit
OUT
VDD – 1.025
V
VDD – 1.620
V
0.25
0.45
ns
0.25
0.45
ns
PECL Transistion Time Waveform
DUTY CYCLE
VDD
45 - 55%
50Ω
55 - 45%
2.0V
OUT
80%
50Ω
20%
OUT
OUT
tR
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tF
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Rev. 02/18/10 Page 8
Analog Frequency Multiplier
PL663-xx XO Families
LVDS ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
CONDITIONS
MIN.
Supply Current (with loaded outputs)
IDD
Fout = 212.5MHz, 15pF Load
Operating Supply Voltage
VDD
@ 1.25V
VDD Magnitude Change
MAX.
UNITS
55
60
mA
3.63
V
2.25
Output Clock Duty Cycle
Output Differential Voltage
TYP.
45
50
55
%
VOD
247
355
454
mV
∆VOD
-50
50
mV
1.6
V
Output High Voltage
VOH
Output Low Voltage
VOL
Offset Voltage
1.4
RL = 100 U
(see figure)
0.9
1.1
VOS
1.125
1.2
1.375
V
Offset Magnitude Change
∆VOS
0
3
25
mV
Power-off Leakage
IOXD
±1
±10
µA
Output Short Circuit Current
IOSD
-5.7
-8
mA
Differential Clock Rise Time
tr
0.2
0.5
0.7
ns
Differential Clock Fall Time
tf
0.2
0.5
0.7
ns
Vout = VDD or GND
VDD = 0V
RL = 100 U
CL = 10 pF
(see figure)
V
LVDS Transistion Time Waveform
LVDS Levels Test Circuit
LVDS Switching Test Circuit
OUT
OUT
0V (Differential)
OUT
CL = 10pF
50Ω
VOD
OUT
VOS
VDIFF
RL = 100Ω
80%
VDIFF
80%
0V
50Ω
CL = 10pF
OUT
20%
20%
OUT
tR
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tF
Rev. 02/18/10 Page 9
Analog Frequency Multiplier
PL663-xx XO Families
LVCMOS ELECTRICAL CHARACTERISTICS
PARAMETERS
SYMBOL
Supply Current, Dynamic,
Loaded Outputs
IDD
Operating Supply Voltage
VDD
CONDITIONS
MIN.
At 100MHz, load=10pF
TYP.
MAX.
UNITS
32
40
mA
3.63
V
2.25
Output High Voltage (LVTTL)
VOH3.3
IOH = -8.5mA, 3.3V Supplies
Output Low Voltage (LVTTL)
VOL3.3
IOL = 8.5mA, 3.3V Supplies
Output High Voltage (LVCMOS)
VOHC3.3
IOH = -4mA, 3.3V Supplies
VDD – 0.4
V
Output High Voltage
VOH2.5
IOH = 1mA, 2.5V Supplies
VDD – 0.2
V
Output Low Voltage
VOL2.5
IOL = 1mA, 2.5V Supplies
Output Drive Current
IOSD
VOL = 0.4V, VOH = 2.4V
(per output)
8.5
Output Clock Rise/Fall Time
Tr/Tf
10% / 90% VDD with 10 pF
load
1.2
1.6
ns
50
55
%
Output Clock Duty Cycle
Measured @ 50% VDD
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2.4
V
0.4
0.2
45
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V
V
mA
Rev. 02/18/10 Page 10
Analog Frequency Multiplier
PL663-xx XO Families
BOARD DESIGN AND LAYOUT CONSIDERATIONS
L2X: Reduce the PCB trace inductance to a
minimum by placing L2X as physically close to their
respective pins as possible. Also be sure to bypass
each V DD connection especially taking care to place
a 0.01 uF bypass at the V DD side of L2X (see
recommended layout).
used, feed each bypass cap with its own via. Be
sure to connect any ground pin including the bypass
caps with short via connection to the ground plane.
OESEL: J1 is recommended so the same PCB
layout can be used for both OESEL settings.
Crystal Connections: Be sure to keep the ground
plane under the crystal connections continuous so
that the stray capacitace is consistent on both
crystal connections. Also be sure to keep the crystal
connections symmetrical with respect to one another
and the crystal connection pins of the IC. If you
chose to use a series capacitance and/or inductor to
fine tune the crystal frequency, be sure to put
symmetrical pads for this cap on both crystal pins
(see Cadj in recommended layout), even if one of
the capacitors will be a 0.01 uF and the other is
used to tune the frequency. To further maintain a
symmetrical balance on a crystal that may have
more internal Cstray on one pin or the other, place
capacitor pads (Cbal) on each crystal lead to ground
(see recommended layout). R3rd is only required if
a 3 rd overtone crystal is used.
V DD and GND: Bypass VDDANA and VDDBUF with
separate bypass capacitors and if a V DD plane is
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PL663 (2x AFM) TSSOP Layout
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Rev. 02/18/10 Page 11
Analog Frequency Multiplier
PL663-xx XO Families
L2X
GNDOSC
2
15
VDDOSC
DNC
3
14
VDDANA
XIN
4
13
OESEL
VDDANA
14
XOUT
5
12
VDDBUF
VDDOSC
15
OE
6
11
QBAR
L2X
16
DNC
7
10
Q
GNDANA
8
9
11
10
9
1
2
3
4
DNC
XIN
PL663
PL663663-XX
GNDOSC
GNDBUF
12
13
DNC
OESEL
GNDBUF
16
Q
1
PL663-XX
DNC
QBAR
VDDBUF
PACKAGE PIN DESCRIPTION AND ASSIGNMENT
8
GNDANA
7
DNC
6
OE
5
XOUT
2x AFM Package Pin Out
PIN ASSIGNMENTS
Name
Pin #
Type
Description
DNC
1,3,7
I
Do Not Connect.
GNDOSC
2
P
GND connection for oscillator.
XIN
4
I
Input from crystal oscillator circuitry.
XOUT
5
O
Output from crystal oscillator circuitry.
OE
6
I
Output Enable input. See “OE LOGIC SELECTION TABLE”.
GNDANA
8
P
GND connection.
GNDBUF
9
P
GND connection.
Q
10
O
PECL/LVDS/CMOS output.
QBAR
11
O
Complementary PECL/LVDS output or in-phase CMOS.
VDDBUF
12
P
VDD connection for output buffer circuitry. VDDBUF should be separately decoupled
from other VDDs whenever possible.
OESEL
13
I
Selector input to choose the OE control logic (see “OE SELECTION TABLE”). If no
connection is applied, value will be set to default through internal pull-down resistor.
VDDANA
14
P
VDD connection for analog circuitry.VDDANA should be separately decoupled from
other VDDs whenever possible.
VDDOSC
15
P
L2X
16
I
VDD connection for oscillator. VDD should be separately decoupled from other VDDs
whenever possible.
External inductor connection. The inductor is recommended to be a high Q small size
0402 or 0603 SMD component, and must be placed between L2X and adjacent
VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects
and to maintain inductor Q.
2880 Zanker Road, San Jose, California 95134 TEL (408) 571-1668, FAX (408) 571-1688
www.phaselink.com
Rev. 02/18/10 Page 12
Analog Frequency Multiplier
PL663-xx XO Families
PACKAGE INFORMATION
16 PIN TSSOP
16 PIN TSSOP ( mm )
Symbol
A
A1
B
C
D
E
H
L
e
Min.
Max.
1.20
0.05
0.15
0.19
0.30
0.09
0.20
4.90
5.10
4.30
4.50
6.40 BSC
0.45
0.75
0.65 BSC
E
H
D
A
A1
C
L
B
e
16 PIN 3x3 QFN
QFN-16L
Max
A
0.70
0.75
0.80
A1
0.00
-
0.05
D1
DED
Nom
0.203 Ref
A3
b
0.20
0.25
0.30
D
2.95
3.00
3.05
E
2.95
3.00
3.05
D1
1.65
1.70
1.75
E1
1.65
1.70
1.75
L
0.250
0.300
0.350
e
L
Dimension (mm)
Min
DDD
E1
Symbol
e
Pin1 Dot
b
A
A3
0.50BSC
SEATING
PLANE
2880 Zanker Road, San Jose, California 95134 TEL (408) 571-1668, FAX (408) 571-1688
www.phaselink.com
A1
Rev. 02/18/10 Page 13
Analog Frequency Multiplier
PL663-xx XO Families
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
To order parts, please contact our Sales Department:
47745 Fremont Blvd., Fremont, CA 94538, USA
Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following:
Part number, Package type and Operating temperature range
Part/Order Number
PL663-XXOC
PL663-XXOC-R
PL663-XXQC-R
Marking
P663-XX
OC
LLLLL
P663
XX
LLL
PL663-XXDC
Package Option
TSSOP – Tube
TSSOP – Tape and Reel
QFN – Tape and Reel
Die – Waffle Pack
Note: See Product Selector Guide on page 3 for specific –XX part numbers.
LLLLL and LLL designates lot number
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information
furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said
information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product.
LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the
express written approval of the President of PhaseLink Corporation.
2880 Zanker Road, San Jose, California 95134 TEL (408) 571-1668, FAX (408) 571-1688
www.phaselink.com
Rev. 02/18/10 Page 14