Analog Frequency Multiplier PL660 and PL663 XO Families DESCRIPTION FEATURES TM PhaseLink’s Analog Frequency Multipliers (AFMs) are the industry’s first “Balanced Oscillator” utilizing analog multiplication of the fundamental frequency (at double or quadruple frequency), combined with an attenuation of the fundamental of the reference crystal, without using a phase-locked loop (PLL), in CMOS technology. • • • • PhaseLink’s patent pending PL66x family of AFM products can achieve up to 800 MHz differential PECL, LVDS, or single-ended CMOS output with little jitter or phase noise deterioration. • PL66x-xx family of products utilize a low-power CMOS technology and are housed in GREEN/ RoHS compliant 16-pin TSSOP and 3x3 QFN packages. • • • • • • Non-PLL frequency multiplication Input frequency from 30-200 MHz Output frequency from 60-800 MHz Low phase noise and jitter (equivalent to fundamental at the output frequency) Ultra-low jitter o RMS phase jitter < 0.25 ps (12 kHz to 20 MHz) o RMS period jitter < 2.5 ps typ. Low phase noise o -145 dBc/Hz @ 100 kHz offset from 155.52 MHz o -150 dBc/Hz @ 10 MHz offset from 155.52 MHz Low input frequency eliminates the need for expensive crystals Differential PECL/LVDS, or single-ended CMOS output Single 2.5V or 3.3V +/- 10% power supply Optional industrial temperature range (-40°C to +85°C) Available in 16-pin GREEN/RoHS compliant TSSOP, and 16-pin 3x3 QFN packages. rd Figure 1: 2X AFM Phase Noise at 212.5 MHz (106.25 MHz 3 overtone crystal) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 1 Analog Frequency Multiplier PL660 and PL663 XO Families L2X OE X IN R O s c illa t o r A m p lif ie r XOUT QBAR F re q u e n c y X2 F re q u e n c y X4 Q O n ly r e q u ir e d in x 4 d e s ig n s L4X Figure 2: Block Diagram of AFM XO Figure 3 shows the period jitter histogram of the 2x Analog Frequency Multiplier at 212.5 MHz, while Figure 4 shows the very low levels of sub-harmonics that correspond to the exceptional performance (i.e. low jitter). Figure 3: Period Jitter Histogram at 212.5MHz Figure 4: Spectrum Analysis at 212.5MHz Analog Frequency Multiplier (2x), with 106.25 MHz crystal Analog Frequency Multiplier (2x), with sub-harmonics below –69 dBc OE LOGIC SELECTION OUTPUT OESEL 0 (Default) PECL 1 0 (Default) LVDS or CMOS 1 OE Output State 0 (Default) 1 0 1 (Default) 0 1 (Default) 0 (Default) 1 Enabled Tri-state Tri-state Enabled Tri-state Enabled Enabled Tri-state OESEL and OE: Connect to VDD to set to “1”, connect to GND to set to “0”. [The ‘Default’ state is set by internal pull up/down resistor.] 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 2 Analog Frequency Multiplier PL660 and PL663 XO Families PRODUCT SELECTOR GUIDE FREQUENCY VERSUS PHASE NOISE PERFORMANCE Phase Noise at Frequency Offset From Carrier (dBc/Hz) Input Frequency Range (MHz) Analog Frequency Multiplication Factor Output Frequency Range (MHz) Output Type PL660-08 30 - 80 4 120 - 320 PL660-09 30 - 80 4 PL663-07 30 - 80 PL663-08 Part Number Carrier Freq. (MHz) 10 Hz 100 Hz 1 KHz 10 KHz 100 KHz 1 MHz 10 MHz PECL 155.52 -72 -100 -125 -132 -142 -147 -149 120 - 320 LVDS 155.52 -72 -100 -125 -132 -142 -147 -149 2 60 - 160 CMOS 156.25 -75 -105 -130 -140 -145 -150 -150 30 - 80 2 60 - 160 PECL 156.25 -75 -105 -130 -140 -145 -150 -150 PL663-09 30 - 80 2 60 - 160 LVDS 156.25 -75 -105 -130 -140 -145 -150 -150 PL663-17 75 - 140 2 150 - 280 CMOS 212.5 -70 -100 -130 -140 -145 -148 -148 PL663-18 75 - 140 2 150 - 280 PECL 212.5 -70 -100 -130 -140 -145 -148 -148 PL663-19 75 - 140 2 150 - 280 LVDS 212.5 -70 -100 -130 -140 -145 -148 -148 PL663-28 140 - 160 2 280 - 320 PECL 311.04 -60 -92 -122 -140 -142 -146 -146 PL663-29 140 - 160 2 280 - 320 LVDS 311.04 -60 -92 -122 -140 -142 -146 -148 FREQUENCY VERSUS JITTER, AND SUB-HARMONIC PERFORMANCE Part Number Output Freq. (MHz) RMS Period Jitter (ps) Peak to Peak Period Jitter (ps) RMS Accumulated (L.T.) Jitter (ps) Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Phase Jitter (12 KHz-20MHz) (ps) Min. Typ. Max. Spectral Specifications / Sub-harmonic Content (dBc) Frequency (MHz) Carrier Freq. MHz (Fc) @ -75% (Fc) @ -50% (Fc) @ -25% (Fc) @ +25% (Fc) @ +50% (Fc) @ +75% (Fc) PL660-08 155.52 3 5 21 30 5 0.25 155.52 -66 -61 -67 -70 PL660-09 155.52 3 5 21 30 5 0.25 155.52 -66 -61 -67 -70 PL663-07 156.25 2 3 18 20 3 0.24 156.25 -70 -75 PL663-08 156.25 2 3 18 20 3 0.24 156.25 -70 -75 PL663-09 156.25 2 3 18 20 3 0.24 156.25 -70 -75 PL663-17 212.50 2.5 4 18 20 4 0.19 212.50 -70 -75 PL663-18 212.50 2.5 4 18 20 4 0.19 212.50 -70 -75 PL663-19 212.50 2.5 4 18 20 4 0.19 212.50 -70 -75 PL663-28 311.04 2.5 4 18 20 4 0.16 311.04 -65 -70 PL663-29 311.04 2.5 4 18 20 4 0.16 311.04 -65 -70 Note: Wavecrest data 10,000 hits. No Filtering was used in Jitter Calculations. Agilent E5500 was used for phase jitter measurements. Spectral specifications were obtained using Agilent E7401A. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 3 Analog Frequency Multiplier PL660 and PL663 XO Families BOARD LAYOUT CONSIDERATIONS AND CRYSTAL SPECIFICATIONS BOARD LAYOUT CONSIDERATIONS To minimize parasitic effects and improve performance, do the following: • Place the crystal as close as possible to the IC. • Make the board traces that are connected to the crystal pins symmetrical. The board trace symmetry is very important, as it reduces the negative parasitic effects to produce clean frequency multiplication with low jitter. CRYSTAL SPECIFICATIONS Crystal Resonator Frequency (FXIN) Mode PL660-08 PL660-09 25~75MHz PL663-07 PL663-08 PL663-09 CL (xtal) ESR(RE) C0 C0/C1 Typical Max. Max. Max. Fundamental or 3rd overtone 5 pF 30 Ω 4.5 pF N.A. 30~80MHz Fundamental or 3rd overtone 5 pF 30 Ω 4.5 pF N.A. PL663-17 PL663-18 PL663-19 75~140MHz Fundamental or 3rd overtone 5 pF 60 Ω 4.0 pF N.A. PL663-28 PL663-29 140~200MHz Fundamental or 3rd overtone 5 pF 60 Ω 4.0 pF N.A. Part Number Note: Non-specified parameters can be chosen as standard values from crystal suppliers. CL ratings larger than 5pF require a crystal frequency adjustment. Request detailed crystal specifications from PhaseLink. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 4 Analog Frequency Multiplier PL660 and PL663 XO Families EXTERNAL COMPONENT VALUES INDUCTOR VALUE OPTIMIZATION The required inductor value(s) for the best performance depends on the operating frequency, and the board layout specifications. The listed values in this datasheet are based on the calculated parasitic values from PhaseLink’s evaluation board design. These inductor values provide the user with a starting point to determine the optimum inductor values. Additional fine-tuning may be required to determine the optimal solution. To assist with the inductor value optimization, PhaseLink has developed the “AFM Tuning Assistant” software. You can download this software from PhaseLink’s web site (www.phaselink.com). The software consists of two worksheets. The first worksheet (named L2) is used to fine-tune the ‘L2’ inductor value, and the second worksheet (named L4) is used for fine tuning of the ‘L4’ (used in 4x AFMs only) inductor value. For those designs using PhaseLink’s recommended board layout, you can use the “AFM Tuning Assistant” to determine the optimum values for the required inductors. This software is developed based on the parasitic information from PhaseLink’s board layout and can be used to determine the required inductor and parallel capacitor (see LWB1 and Cstray parameters) values. For those employing a different board layout in their design, we recommend to use the parasitic information of their board layout to calculate the optimized inductor values. Please use the following fine tuning procedure: Figure 5: Diagram Representation of the Related System Inductance and Capacitance DIE SIDE - Cinternal = Based on AFM Device - Cpad = 2.0 pF, Bond pad and its ESD circuitry - C11 = 0.4 pF, The following amplifier stage PCB side - LWB1 = 2 nH, (2 places), Stray inductance - Cstray = 1.0 pF, Stray capacitance - L2X (L4X) = 2x or 4x inductor - C2X (C4X) = range (0.1 to 2.7), Fine tune inductor if used 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 5 Analog Frequency Multiplier PL660 and PL663 XO Families • There are two default variables that normally will not need to be modified. These are Cpad, and C11 and are found in cells B22 and B27 of ‘AFM Tuning Assistant’, respectively. • LWB1 is the combined stray inductance in the layout. The DIE wire bond is ~ 0.6 nH and in the case of a leaded part an additional 1.0 nH is added. Your layout inductance must be added to these. There are 2 of these and they are assumed to be approximately symmetrical so you only need to enter this inductance once in cell B23. • Enter the stray parasitic capacitance into cell B26. An additional 0.5 pF must be added to this value if a leaded part is used. • Enter the appropriate value for Cinternal into B21 based on the device used (see column D). Use the ‘AFM Tuning Assistant’ software to calculate L2X (and C2X if used) for your resonance frequency. • For 4X AFMs, repeat the same procedure in the L4X worksheet. • See the examples below. DETERMINING STRAY L’s AND C’s IN A LAYOUT Figure 6: Diagram Representation of PL660-08 Board Layout Let’s take the PL660-08 (4x XO) for example, as shown in Figure 6. This takes a crystal input range of 30 to 80 MHz and multiplies this to an output of 120 to 320 MHz. To determine the stray L’s and C’s of the layout we will assemble two test units. One AFM will be tuned to the lower range of the device (120 MHz), and the other to the upper range of the device (320 MHz). 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 6 Analog Frequency Multiplier PL660 and PL663 XO Families 120 MHz AFM Tuning: Using the “AFM Tuning Assistant” find the PL660-0x in the L2X worksheet. Enter the Cinternal value found next to it into cell B21. In cell B24 enter the closest standard inductor value (see CoilCraft 0603CS series for example) to achieve the closest peak frequency to 60 MHz. Repeat the same procedure for L4X at 120 MHz. Results: L2X = 180 nH, L4X = 82 nH. 320 MHz AFM tuning: Repeat the previous procedure for L2X at 120 MHz and L4X at 320 MHz. Results: L2X = 24 nH, L4X = 10 nH. Proceed and assemble the test units. Measuring 120 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 30 MHz. Since this is the 2x port, the scope will show 60 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 30 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 29.8x2 or 59.6 MHz. Measuring 320 MHz L2X: Connect the RF generator and scope probe as shown in Figure 6. While power is applied to the PCB, set the generator output to +12 dBm and the frequency to 80 MHz. Since this is the 2x port the scope will show 160 MHz with ~ 3V pk-pk amplitude. Vary the generator above and below 80 MHz until the amplitude on the scope is maximum and record the generator frequency. For example peak recorded at 78.0 x 2 = 156 MHz In the AFM Tuning Assistant, add the scope’s probe capacitance to the Cstray cell. For our example 0.5 pF + 1.0 pF = 1.5 pF. With L2X at 24 nH adjust LWB1 (cell B23) until the peak frequency reads 156 MHz. Next replace the L2X value with 180 nH and see if it peaks at 59.6 MHz. If it does not, adjust the Cstray until 59.4 MHz is achieved. Again enter 24 nH for L2X and fine tune LWB1 for 156 MHz. Results: LWB1 = 1.6 nH, Cstray = 2.9 pF-0.5 pF = 2.4 pF (subtract scope probe stray) Repeat the same steps for the L4X: Set the generator to 80 MHz. The 82 nH peaks at 118 MHz and the 10 nH peaks at 304 MHz. Results: LWB1 = 1.8 nH, Cstray = 2.5 pF-0.5 pF = 2.0 pF (subtract scope probe stray) Internal Capacitor Selection by Device Device Number PL660-0X PL663-0X PL663-1X PL663-2X Cinternal (pF) 2X 34.125 46.500 14.625 14.625 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 4X 16.500 www.phaselink.com Rev. 3/20/07 Page 7 Analog Frequency Multiplier PL660 and PL663 XO Families EXTERNAL COMPONENT VALUES – 3 RD OVERTONE RESISTOR SELECTIONS (R3rd) This resistor is only required when a third overtone crystal is used. The chart below indicates the calculated and the nearest “E12” resistor values versus frequency. PL660-08/09 Freq. (MHz) R3rd (Ω) 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 66 68 70 72 74 76 12,396 11,442 10,625 9,917 9,297 8,750 8,264 7,829 7,438 7,083 6,761 6,467 6,198 5,950 5,721 5,509 5,313 5,129 4,958 4,798 4,648 4,508 4,375 4,250 4,132 4,020 3,914 E12 Pick KΩ 12 12 10 10 10 8.2 8.2 8.2 6.8 6.8 6.8 6.8 6.8 5.6 5.6 5.6 5.6 4.7 4.7 4.7 4.7 4.7 4.7 3.9 3.9 3.9 3.9 PL663-07/08/09 E12 Freq. R3rd Pick (MHz) (Ω) KΩ 30 9,917 10 32 9,297 10 34 8,750 8.2 36 8,264 8.2 38 7,829 8.2 40 7,438 6.8 42 7,083 6.8 44 6,761 6.8 46 6,467 6.8 48 6,198 6.8 50 5,950 5.6 52 5,721 5.6 54 5,509 5.6 56 5,313 5.6 58 5,129 4.7 60 4,958 4.7 62 4,798 4.7 64 4,648 4.7 66 4,508 4.7 68 4,375 4.7 70 4,250 3.9 72 4,132 3.9 74 4,020 3.9 76 3,914 3.9 78 3,814 3.9 80 3,719 3.9 PL663-017/18/19 E12 Freq. R3rd Pick (MHz) (Ω) KΩ 75 2,125 2.2 77.5 2,056 2.2 80 1,992 2.2 82.5 1,932 1.8 85 1,875 1.8 87.5 1,821 1.8 90 1,771 1.8 92.5 1,723 1.8 95 1,678 1.8 97.5 1,635 1.5 100 1,594 1.5 102.5 1,555 1.5 105 1,518 1.5 107.5 1,483 1.5 110 1,449 1.5 112.5 1,417 1.5 115 1,386 1.5 117.5 1,356 1.5 120 1,328 1.2 122.5 1,301 1.2 125 1,275 1.2 127.5 1,250 1.2 130 1,226 1.2 132.5 1,203 1.2 135 1,181 1.2 137.5 1,159 1.2 140 1,138 1.2 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 PL663-28/29 Freq. (MHz) R3rd (Ω) 140.0 142.0 144.0 146.0 148.0 150.0 152.0 154.0 156.0 158.0 160.0 162.0 164.0 166.0 168.0 170.0 172.0 174.0 176.0 178.0 180.0 182.0 184.0 186.0 188.0 190.0 192.0 194.0 196.0 198.0 200.0 915 902 890 878 866 854 843 832 821 811 801 790 780 770 759 749 740 730 720 711 701 692 683 674 665 656 647 639 630 622 614 www.phaselink.com E24 Pick KΩ 0.91 0.91 0.91 0.91 0.91 0.82 0.82 0.82 0.82 0.82 0.82 0.82 0.75 0.75 0.75 0.75 0.75 0.75 0.75 0.68 0.68 0.68 0.68 0.68 0.68 0.68 0.62 0.62 0.62 0.62 0.62 Rev. 3/20/07 Page 8 Analog Frequency Multiplier PL660 and PL663 XO Families ELECTRICAL SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS PARAMETERS MIN. SYMBOL Supply Voltage V DD MAX. UNITS 4.6 V Input Voltage, DC VI GND-0.5 V DD +0.5 V Output Voltage, DC VO GND-0.5 V DD +0.5 V Storage Temperature TS -55 +150 °C Industrial Ambient Operating Temperature T A_I -40 +85 °C Commercial Ambient Operating Temperature T A_C 0 +70 °C 125 °C 260 °C Junction Temperature TJ Lead Temperature (soldering, 10s) Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. PECL ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL CONDITIONS MIN. TYP. MAX. UNITS Supply Current (with loaded outputs) IDD Fout = 212.5 MHz 58 65 75 mA Operating Supply Voltage VDD 3.63 V 55 % Output Clock Duty Cycle 2.25 @ VDD – 1.3V 45 Short Circuit Current 50 mA ±50 Output High Voltage VOH RL = 50 Ω to VDD – 2V Output Low Voltage VOL RL = 50 Ω to VDD – 2V Clock Rise Time tr @20/80% Clock Fall Time tf @80/20% VDD – 1.025 PECL Levels Test Circuit OUT V VDD – 1.620 V 0.25 0.45 ns 0.25 0.45 ns PECL Transistion Time Waveform DUTY CYCLE VDD 45 - 55% 50Ω 55 - 45% 2.0V OUT 80% 50Ω 20% OUT OUT tR 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 tF www.phaselink.com Rev. 3/20/07 Page 9 Analog Frequency Multiplier PL660 and PL663 XO Families LVDS ELECTRICAL CHARACTERISTICS PARAMETERS Supply Current (with loaded outputs) SYMBOL IDD Operating Supply Voltage CONDITIONS Fout = 212.5 MHz MIN. VDD 2.25 Output Clock Duty Cycle @ 1.25V Output Differential Voltage VDD Magnitude Change TYP. 55 MAX. 60 UNITS mA 3.63 V 45 50 55 % VOD 247 355 454 mV ∆VOD -50 50 mV 1.6 V Output High Voltage VOH Output Low Voltage VOL Offset Voltage 1.4 RL = 100 Ω (see figure) 0.9 1.1 VOS 1.125 1.2 1.375 V Offset Magnitude Change ∆VOS 0 3 25 mV Power-off Leakage IOXD ±1 ±10 µA Output Short Circuit Current IOSD -5.7 -8 mA 0.2 0.5 0.7 ns 0.2 0.5 0.7 ns Differential Clock Rise Time tr Differential Clock Fall Time tf Vout = VDD or GND VDD = 0V RL = 100 Ω CL = 10 pF (see figure) V LVDS Transistion Time Waveform LVDS Levels Test Circuit LVDS Switching Test Circuit OUT OUT 0V (Differential) OUT CL = 10pF 50Ω VOD OUT VOS VDIFF RL = 100Ω 80% VDIFF 80% 0V 50Ω CL = 10pF OUT 20% 20% OUT tR 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com tF Rev. 3/20/07 Page 10 Analog Frequency Multiplier PL660 and PL663 XO Families CMOS ELECTRICAL CHARACTERISTICS PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs I DD Operating Supply Voltage V DD CONDITIONS MIN. At 100MHz, load=15pF TYP. MAX. UNITS 32 40 mA 3.63 V 2.25 Output High Voltage (LVTTL) V OH3.3 I OH = -8.5mA, 3.3V Supplies 2.4 V Output Low Voltage (LVTTL) V OL3.3 I OL = 8.5mA, 3.3V Supplies Output High Voltage (LVCMOS) V OHC3.3 I OH = -4mA, 3.3V Supplies V DD – 0.4 V Output High Voltage V OH2.5 I OH = 1mA, 2.5V Supplies V DD – 0.2 V Output Low Voltage V OL2.5 I OL = 1mA, 2.5V Supplies 0.4 V 0.2 V Output drive current I OSD V OL = 0.4V, V OH = 2.4V (per output) 8.5 Output Clock Rise/Fall Time Tr/Tf 10% ~ 90% VDD with 10 pF load 1.2 1.6 ns 50 55 % Output Clock Duty Cycle Short Circuit Current Measured @ 50% VDD 45 IS 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 mA ±50 www.phaselink.com Rev. 3/20/07 Page 11 mA Analog Frequency Multiplier PL660 and PL663 XO Families BOARD DESIGN AND LAYOUT CONSIDERATIONS L2X and L4X: Reduce the PCB trace inductance to a minimum by placing L2X and L4X as physically close to their respective pins as possible. Also be sure to bypass each VDD connection especially taking care to place a 0.01 uF bypass at the VDD side of L2X and L4X (see recommended layout). Crystal Connections: Be sure to keep the ground plane under the crystal connections continuous so that the stray capacitace is consistent on both crystal connections. Also be sure to keep the crystal connections symmetrical with respect to one another and the crystal connection pins of the IC. If you chose to use a series capacitance and/or inductor to fine tune the crystal frequency, be sure to put symmetrical pads for this cap on both crystal pins (see Cadj in recommended layout), even if one of the capacitors will be a 0.01 uF and the other is used to tune the frequency. To further maintain a symmetrical balance on a crystal that may have more internal Cstray on one pin or the other, place capacitor pads (Cbal) on each crystal lead to ground (see recommended layout). R3rd is only required if a 3rd overtone crystal is used. PL660 (4x AFM) TSSOP Layout VDD and GND: Bypass VDDANA and VDDBUF with separate bypass capacitors and if a VDD plane is used, feed each bypass cap with its own via. Be sure to connect any ground pin including the bypass caps with short via connection to the ground plane. OESEL: J1 is recommended so the same PCB layout can be used for both OESEL settings. PL663 (2x AFM) TSSOP Layout 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 12 Analog Frequency Multiplier PL660 and PL663 XO Families 13 OESEL XOUT 5 OE 6 DNC GNDANA 12 VDDBUF 11 QBAR 7 10 Q 8 9 VDDANA VDDOSC L2X GNDBUF VDDOSC DNC 3 14 OESEL DNC 6 OE XIN 4 13 VDDANA VDDOSC XOUT 5 12 VDDBUF L2X OE 6 11 QBAR L4X 7 10 VDDOSC 8 9 XOUT 2x AFM Package Pin Out VDDANA OESEL Q GNDBUF GNDBUF Q QBAR VDDBUF L2X 15 GNDANA 7 5 16 2 1 1 1 9 12 1 0 3 1 4 1 PL660-XX 5 1 61 2 3 4 8 VDDOSC 7 L4X 6 OE 5 XOUT XIN 4 8 1 GNDOSC DNC XIN OESEL OSCOFFSEL OSCOFF SEL GNDOSC VDDANA Q 14 GNDBUF 3 XIN DNC 1 1 1 9 12 1 0 3 1 4 1 PL663-XX 5 1 61 2 3 4 DNC VDDOSC DNC L2X 15 GNDOSC 16 2 PL660-XX 1 PL663-XX DNC GNDOSC QBAR VDDBUF PACKAGE PIN DESCRIPTION AND ASSIGNMENT 4x AFM Package Pin Out PIN ASSIGNMENTS Name Pin # Type 1 I GNDOSC 2 P 2X & 4X GND connection for oscillator. DNC 3 I 2X & 4X Do Not Connect. XIN 4 I XOUT 5 O 2X & 4X OE 6 I 2X & 4X DNC OSCOFFSEL DNC Product Description 2X Do Not Connect. Set to “0” (GND) to turn off the oscillator when outputs are disabled (OE). Default (no connect) is OSC always on. 4X 2X & 4X 2X L4X 7 I 8 P GNDANA 4X 2X Input from crystal oscillator circuitry. Output from crystal oscillator circuitry. Output Enable input. See “OE LOGIC SELECTION TABLE”. Do Not Connect. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L4X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. This inductor is used with 4x AFMs. GND connection. GNDBUF 9 P 2X & 4X VDD connection for oscillator circuitry. VDDOSC should be separately decoupled from other VDDs whenever possible. GND connection. Q 10 O 2X & 4X PECL/LVDS/CMOS output. QBAR 11 O 2X & 4X Complementary PECL/LVDS output or in-phase CMOS. VDDBUF 12 P 2X & 4X VDD connection for output buffer circuitry. VDDBUF should be separately decoupled from other VDDs whenever possible. VDDOSC OESEL VDDANA 4X 13 14 14 13 I P 2X 4X 2X 4X VDDOSC 15 P 2X & 4X L2X 16 I 2X & 4X Selector input to choose the OE control logic (see “OE SELECTION TABLE”). If no connection is applied, value will be set to default through internal pull-down resistor. VDD connection for analog circuitry.VDDANA should be separately decoupled from other VDDs whenever possible. VDD connection for oscillator. VDD should be separately decoupled from other VDDs whenever possible. External inductor connection. The inductor is recommended to be a high Q small size 0402 or 0603 SMD component, and must be placed between L2X and adjacent VDDOSC. Place inductor as close to the IC as possible to minimize parasitic effects and to maintain inductor Q. Note: 663-xx devices are 2x multipliers, and 660-xx devices are 4x multipliers. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 13 Analog Frequency Multiplier PL660 and PL663 XO Families PACKAGE INFORMATION 16 PIN TSSOP 16 PIN TSSOP ( mm ) Symbol A A1 B C D E H L e Min. Max. 1.20 0.05 0.15 0.19 0.30 0.09 0.20 4.90 5.10 4.30 4.50 6.40 BSC 0.45 0.75 0.65 BSC E H D A A1 C e B L 16 PIN 3x3 QFN 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 14 Analog Frequency Multiplier PL660 and PL663 XO Families ORDERING INFORMATION To order parts, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PL66X-XX X X X X NONE= TUBE R= TAPE AND REEL PART NUMBER NONE= NORMAL PACKAGE L= GREEN PACKAGE PACKAGE TYPE O=TSSOP Q= QFN 3x3 Order Number PL66X-XXOC PL66X-XXOC-R PL66X-XXOCL PL66X-XXOCL-R PL66X-XXQC PL66X-XXQC-R PL66X-XXQCL PL66X-XXQCL-R TEMPERATURE C=COMMERCIAL I=INDUSTRIAL Marking P66X-XX P66X-XX P66X-XX P66X-XX P66X-XX P66X-XX P66X-XX P66X-XX OC OC OC OC QC QC QC QC Package Option TSSOP – Tube TSSOP – Tape and Reel TSSOP (GREEN)– Tube TSSOP (GREEN)– Tape and Reel QFN – Tube QFN – Tape and Reel QFN (GREEN)– Tube QFN (GREEN)– Tape and Reel PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990, FAX (510) 492-0991 www.phaselink.com Rev. 3/20/07 Page 15