PLL500-17B Low Phase Noise VCXO (17MHz to 36MHz) FEATURES • • • • • • • • • VCXO output for the 17MHz to 36MHz range Low phase noise (-130 dBc @ 10kHz offset at 35.328MHz). CMOS output with OE tri-state control. Selectable output drive (Standard or High drive). - Standard: 12mA drive capability at TTL level. - High: 36mA drive capability at TTL level. 17 to 36MHz fundamental crystal input. Integrated high linearity variable capacitors. 12mA drive capability at TTL output. +/- 150 ppm pull range, max 5% linearity. Low jitter (RMS): 2.5ps period jitter. 2.5-3.3V operation. Available in 8-Pin SOIC or DIE. XIN 1 OE^ 2 VIN 3 GND 4 8 XOUT 7 DS^ 6 VDD* 5 CLK ^: Denotes internal Pull-up DIE PAD LAYOUT 8 1 2 DESCRIPTION The PLL500-17 is a low cost, high performance and low phase noise VCXO for the 17 to 36MHz range, providing less than -130dBc at 10kHz offset at 35.328MHz. The very low jitter (2.5 ps RMS period jitter) makes this chip ideal for applications requiring voltage controlled frequency sources. Input crystal can range from 17 to 36MHz (fundamental resonant mode). P500-17B • • PIN CONFIGURATION Die ID: 7 C500AA0505-05P 6 3 5 4 FREQUENCY RANGE MULTIPLIER FREQUENCY OUTPUT BUFFER No PLL 17 – 36 MHz CMOS BLOCK DIAGRAM XIN XOUT XTAL OSC VARICAP OE VCON 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/14/04 Page 1 PLL500-17B Low Phase Noise VCXO (17MHz to 36MHz) PIN AND PAD DESCRIPTION Name Pin# XIN Die Pad Position Type Description X (µm) Y (µm) 1 94.183 768.599 I Crystal input pin. OE 2 94.157 605.029 P Output Enable input pin. Disables the output when low. Internal pull-up enables output by default if pin is not connected to low. VCON 3 94.183 331.756 I Frequency control voltage input pin. GND 4 94.193 140.379 P Ground pin. CLK 5 715.472 203.866 O Output clock pin. VDD 6 715.307 455.726 P DS 7 715.472 626.716 I XOUT 8 476.906 888.881 I VDD power supply pin. Output drive select pin. High drive if set to ‘0’. Low drive if set to ‘1’. Internal pull-up. Crystal output pin. Ref Clock input. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V CC - 0.5 4.6 V Input Voltage Range VI - 0.5 V CC + 0.5 V Output Voltage Range VO - 0.5 V CC + 0.5 V 240 °C -65 150 °C -40 +85 °C Supply Voltage Range Soldering Temperature Storage Temperature TS Ambient Operating Temperature Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/14/04 Page 2 PLL500-17B Low Phase Noise VCXO (17MHz to 36MHz) 2. AC Electrical Specifications PARAMETERS SYMBOL CONDITIONS Input Crystal Frequency MIN. TYP. 17 Output Clock Rise/Fall Time Output Clock Duty Cycle 0.8V ~ 2.0V with 10 pF load 1.15 0.3V ~ 3.0V with 15 pF load 3.7 Measured @ 1.4V 45 50 MAX. UNITS 36 MHz ns 55 ±50 Short Circuit Current % mA 3. Voltage Control Crystal Oscillator PARAMETERS VCXO Stabilization Time * SYMBOL T VCXOSTB CONDITIONS From power valid F XIN = 17 – 36MHz; VCXO Tuning Range XTAL C 0 /C 1 < 250 0V ≤ VCON ≤ 3.3V CLK output pullability MIN. TYP. 10 ppm ±150 ppm Pull range linearity Frequency change with VDD varied +/- 10% VCON pin input impedance VCON modulation BW ms 100 PWSRR 0V ≤ VCON ≤ 3.3V, -3dB UNITS 300 VCXO Tuning Characteristic Power Supply Rejection MAX. -1 ppm/V 5 % +1 ppm 1000 kΩ 45 kHz Note: Parameters denoted with an asterisk (*) represent nominal characterization data and are not production tested to any specific limits. 4. Jitter and Phase Noise specification PARAMETERS RMS Period Jitter CONDITIONS MIN. TYP. MAX. UNITS (1 sigma – 1000 samples) With capacitive decoupling between VDD and GND. 2.5 ps Phase Noise relative to carrier 36MHz @100Hz offset -80 dBc/Hz Phase Noise relative to carrier 36MHz @1kHz offset -110 dBc/Hz Phase Noise relative to carrier 36MHz @10kHz offset -130 dBc/Hz Phase Noise relative to carrier 36MHz @100kHz offset -138 dBc/Hz Phase Noise relative to carrier 36MHz @1MHz offset -145 dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/14/04 Page 3 PLL500-17B Low Phase Noise VCXO (17MHz to 36MHz) 5. DC Specification PARAMETERS SYMBOL Supply Current, Dynamic, with Loaded Outputs I DD Operating Voltage V DD Output High Voltage V OH I OH = -12mA Output Low Voltage V OL I LO = 12mA Output High Voltage at CMOS level V OHC I OH = -4mA Output drive current CONDITIONS MIN. F XIN = 36MHz Output load of 15pF MAX. UNITS 5 6 mA 3.63 V 2.25 2.4 V 0.4 V DD – 0.4 12 17 High drive at TTL level 36 51 mA ±50 VCON ESD Protection 0 Human Body Model V V Standard drive at TTL level Short Circuit Current VCXO Control Voltage TYP. mA 3.3 2000 V V 6. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Rating (VCON = 1.65V) SYMBOL MIN. F XIN 17 C L (xtal) TYP. UNITS 36 MHz 8.5 Maximum Sustainable Drive Level pF 200 Operating Drive Level C0/C1 RS µW µW 50 C0 ESR MAX. 5 pF 250 - 30 Ω Note: The crystal must be such that it oscillates (parallel resonant) at nominal frequency when presented a C Load as specified above. If the crystal requires more load to be at nominal frequency, the additional load must be added externally. This however may reduce the pull range. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/14/04 Page 4 PLL500-17B Low Phase Noise VCXO (17MHz to 36MHz) PACKAGE INFORMATION 8 PIN ( dimensions in mm ) Narrow SOIC Symbol Min. Max. A 1.47 1.73 A1 0.10 0.25 B 0.33 0.51 C 0.19 0.25 D 4.80 4.95 E 3.80 4.00 H 5.80 6.20 L 0.38 1.27 e 1.27 BSC E H D A A 1 C L e B ORDERING INFORMATION PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range Order Number PLL500-17BSC PLL500-17BSC-R PLL500-17BDC Marking P500-17B SC P500-17B SC P500-17B DC Package Option 8-Pin SOIC (Tube) 8-Pin SOIC (Tape and Reel) Die (Waffle Pack) PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 09/14/04 Page 5