Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier FEATURES • • • • • • • • Full swing CMOS outputs with 25 mA drive capability at TTL levels. Reference 20-30MHz crystal or clock. Integrated crystal load capacitor: no external load capacitor required. Output clocks up to 150MHz at 3.3V. Low phase noise (-126dBc/Hz @ 1kHz). Output Enable function. Low jitter (RMS): 6.4ps (period), 9.4ps (accum.) Advanced low power sub-micron CMOS process. 3.3V operation. Available in 8-Pin SOIC or TSSOP. DESCRIPTIONS XIN 1 GND 2 GND 3 GND 4 PLL601-15 • • PIN CONFIGURATION 8 XOUT 7 VDD 6 VDD 5 CLK CRYSTAL RANGE Multiplier Xtal range 5x 20-30MHz The PLL601-15 is a low cost, high performance and low phase noise clock synthesizer. It implements PhaseLink’s proprietary analog and digital Phase Locked Loop techniques for a fixed 5x multiplier. The chip accepts crystal or clock inputs ranging from 20 to 30MHz, and produces outputs clocks up to 150MHz at 3.3V. BLOCK DIAGRAM Phase Locked Loop XIN XOUT CLK XTAL OSC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/08/02 Page 1 Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier PIN DESCRIPTIONS Name Number Type Description CLK 5 O Clock output from VCO. Equals the input frequency times multiplier. VDD 7,6 P 3.3V Power Supply. XIN 1 I Crystal input to be connected to 20-30MHz fundamental parallel mode crystal (C L =15pF). On chip load capacitors: No external capacitor required. XOUT 8 O Crystal Connection. GND 2, 3,4 P Ground. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/08/02 Page 2 Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V CC - 0.5 7 V Input Voltage Range VI - 0.5 V CC + 0.5 V Output Voltage Range VO - 0.5 V CC + 0.5 V 260 °C -65 150 °C 0 70 °C Supply Voltage Range Soldering Temperature Storage Temperature TS Ambient Operating Temperature Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC Specification PARAMETERS CONDITIONS Input Frequency MIN. TYP. 20 MAX. UNITS 30 MHz Output Frequency At 3.3V 150 MHz Output Rise Time 0.8V to 2.0V with no load 1.5 ns Output Fall Time 2.0V to 0.8V with no load 1.5 ns Duty Cycle At VDD/2 55 % Period jitter RMS With capacitive decoupling between VDD and GND 6.4 ps Accumulated jitter RMS With capacitive decoupling between VDD and GND 9.4 ps Phase Noise, relative to carrier, 150Mhz(x5) 100Hz offset, 3.3V -103 dBc/Hz Phase Noise, relative to carrier, 150Mhz(x5) 1kHz offset, 3.3V -126 dBc/Hz Phase Noise, relative to carrier, 150Mhz(x5) 10kHz offset, 3.3V -133 dBc/Hz Phase Noise, relative to carrier, 150Mhz(x5) 100kHz offset, 3.3V -128 dBc/Hz 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 45 50 Rev 01/08/02 Page 3 Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier 3. DC Specification PARAMETERS SYMBOL CONDITIONS MIN. TYP. Operating Voltage VDD 3.135 Input High Voltage V IH 2 Input Low Voltage V IL Input High Voltage V IH For XIN pin Input Low Voltage V IL For XIN pin Output High Voltage V OH I OH = -25mA Output Low Voltage V OL I OL = 25mA Output High Voltage At CMOS Level V OH I OH = -8mA Operating Supply Current I DD No Load Short-circuit Current IS MAX. UNITS 3.465 V V 0.8 (VDD/2) + 1 VDD/2 VDD/2 V V (VDD/2) − 1 2.4 V V 0.4 VDD-0.4 V V 35 mA ±120 mA 4. Crystal Specifications PARAMETERS SYMBOL CONDITIONS MIN. Crystal Resonator Frequency F XIN Parallel Fundamental Mode 20 Crystal Loading Capacitance Rating C L (xtal) 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 TYP. 15 MAX. UNITS 30 MHz pF Rev 01/08/02 Page 4 Preliminary PLL601-15 Low Phase Noise PLL Clock Multiplier PACKAGE INFORMATION 8 PIN ( dimensions in mm ) TSSOP Narrow SOIC Symbol Min. Max. Min. Max. A 1.47 1.73 - 1.20 A1 0.10 0.25 0.05 0.15 B 0.33 0.51 0.19 0.30 C 0.19 0.25 0.09 0.20 D 4.80 4.95 2.90 3.10 E 3.80 4.00 4.30 4.50 H 5.80 6.20 6.20 6.60 L 0.38 1.27 0.45 e H D A 0.75 0.65 BSC 1.27 BSC E A1 C L B e ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL601-15 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 01/08/02 Page 5