Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) FEATURES • • • • Low phase noise XO output for the 48MHz to 96MHz range (-137 dBc at 10kHz offset). CMOS output. 12 to 24MHz crystal input. Integrated crystal load capacitor: no external load capacitor required. Low jitter (RMS): 3-6ps period, 7-10ps accum. 3.3V operation. Available in 8-Pin TSSOP or SOIC. CLK 1 VDD 2 OE 3 XIN 4 PLL602-41 • • • PIN CONFIGURATION 8 GND 7 GND 6 N/C 5 XOUT OUTPUT RANGE DESCRIPTIONS The PLL602-41 is a low cost, high performance and low phase noise XO, providing less than -137dBc at 10kHz offset in the 48MHz to 96MHz operating range. The very low jitter (3 to 6 ps RMS period jitter and 7 to 10 ps RMS accumulated jitter) makes this chip ideal for applications requiring reference frequency sources. Input crystal can range from 12 to 24MHz (fundamental resonant mode). MULTIPLIER FREQUENCY RANGE OUTPUT BUFFER X4 48 - 96MHz CMOS BLOCK DIAGRAM VCO Divider Reference Divider XIN XOUT Phase Comparator Charge Pump Loop Filter VCO CLK OE XTAL OSC 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 1 Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) PIN DESCRIPTIONS Name Number Type Description CLK 1 O Output clock pin. VDD 2 P +3.3V VDD power supply pin. OE 3 I Output enable input pin. Disables (tri-state) output when low. Internal pullup enables output by default if pin is not connected to low. XIN 4 I Crystal input pin. XOUT 5 I Crystal output pin. N/C 6 - Not connected. GND 7, 8 P Ground pin. ELECTRICAL SPECIFICATIONS 1. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS V CC - 0.5 7 V Input Voltage Range VI - 0.5 V CC + 0.5 V Output Voltage Range VO - 0.5 V CC + 0.5 V 260 °C -65 150 °C 0 70 °C Supply Voltage Range Soldering Temperature Storage Temperature TS Ambient Operating Temperature Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. 2. AC Specification PARAMETERS CONDITIONS MIN. TYP. MAX. UNITS Input Frequency 12 24 MHz Output Frequency 48 96 MHz Output Rise Time 0.8V to 2.0V with no load 1.5 ns Output Fall Time 2.0V to 0.8V with no load 1.5 ns Duty Cycle At VDD/2 55 % 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 45 50 Rev 07/13/01 Page 2 Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) 3. Jitter and Phase Noise specification PARAMETERS CONDITIONS MIN. TYP. With capacitive decoupling between VDD and GND. VIN = 3.3V Period jitter RMS MAX. UNITS TBM ps TBM ps -101 dBc/Hz Phase Noise relative to carrier With capacitive decoupling between VDD and GND. Over 10,000 cycles. VIN = 3.3V 100Hz offset, VIN = 3.3V Phase Noise relative to carrier 1kHz offset, VIN = 3.3V -127 dBc/Hz Phase Noise relative to carrier 10kHz offset, VIN = 3.3V -137 dBc/Hz Phase Noise relative to carrier 100kHz offset, VIN = 3.3V -137 dBc/Hz Accumulated jitter RMS 4. DC Specification PARAMETERS SYMBOL CONDITIONS MIN. Operating Voltage VDD 3.135 Input High Voltage V IH 2 Input Low Voltage V IL Input High Voltage V IH For XIN pin Input Low Voltage V IL For XIN pin Output High Voltage V OH I OH = -25mA Output Low Voltage V OL I OL = 25mA Output High Voltage At CMOS Level V OH I OH = -8mA Operating Supply Current I DD No Load Short-circuit Current IS Input Capacitance C IN TYP. MAX. UNITS 3.465 V V 0.8 (VDD/2) + 1 VDD/2 V V VDD/2 (VDD/2) − 1 2.4 V V 0.4 VDD-0.4 OE, Select Pins V V 35 mA ±120 mA 5 pF 5. Crystal Specifications PARAMETERS Crystal Resonator Frequency Crystal Loading Capacitance Rating SYMBOL MIN. F XIN 12 C L (xtal) Driving power ESR TYP. MAX. UNITS 24 MHz TBD pF 1 mW RS 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 25 Ω Rev 07/13/01 Page 3 Preliminary for proposal PLL602-41 Low Phase Noise CMOS XO (48MHz to 96MHz) PACKAGE INFORMATION 8 PIN ( dimensions in mm ) TSSOP Narrow SOIC Symbol Min. Max. Min. Max. A 1.47 1.73 - 1.20 A1 0.10 0.25 0.05 0.15 B 0.33 0.51 0.19 0.30 C 0.19 0.25 0.09 0.20 D 4.80 4.95 2.90 3.10 E 3.80 4.00 4.30 4.50 H 5.80 6.20 6.20 6.60 L 0.38 1.27 0.45 e H D A 0.75 0.65 BSC 1.27 BSC E A1 C L B e ORDERING INFORMATION For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Device number, Package type and Operating temperature range PLL602-41 X C PART NUMBER TEMPERATURATURE C=COMMERCIAL M=MILITARY I=INDUSTRAL PACKAGE TYPE S=SOIC, O=TSSOP, D=DIE PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink’s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation. 47745 Fremont Blvd., Fremont, California 94538 TEL (510) 492-0990 FAX (510) 492-0991 Rev 07/13/01 Page 4