ASAHI KASEI [AK6010A/12A] AK6010A / 12A 2 I C bus 32K / 64Kbit Serial CMOS EEPROM Features ADVANCED CMOS EEPROM TECHNOLOGY READ/WRITE NON-VOLATILE MEMORY WIDE VCC OPERATION : VCC = 1.8V to 5.5V AK6010A ・・ 32768 bits, 4096 x 8 organization AK6012A ・・ 65536 bits, 8192 x 8 organization I2CTM SERIAL INTERFACE LOW POWER CONSUMPTION - 0.8µA Max. Standby HIGH RELIABILITY - Endurance : 100K cycles - Data Retention : 10 years 32 byte Page Write Mode Automatic write cycle time-out with auto-ERASE IDEAL FOR LOW DENSITY DATA STORAGE - Low cost, space saving, 8-pin package (SOP) VCC GND WC SDA SCL S2 S1 S0 H.V.GENERATION TIMING & CONTROL START STOP LOGIC SLAVE ADDRESS REGISTER +COMPARATOR CONTROL LOGIC XDEC EEPROM AK6010A = 32768bit AK6012A = 65536bit WORD ADDRESS COUNTER YDEC DATA REGISTER DOUT ACK Block Diagram I2CTM is a registered trademark of Philips Corporation. DAI02E-03 2002/11 - 1 - ASAHI KASEI [AK6010A/12A] General Description The AK6010A/12A is a 32768/65536-bit serial CMOS EEPROM divided into 4096/8192 registers of 8 bits each. The AK6010A/12A can operate full function under wide operating voltage range from 1.8V to 5.5V. The charge up circuit is integrated for high voltage generation that is used for write operation. The AK6010A/12A conforms to all specifications in the 2 wire protocol and is controlled by serial clock (SCL) and serial data (SDA) line. Some devices can be connected to the same bus. Each device connected to the bus is software addressable by a unique address, and can operate as either a transmitter or receiver. In addition to transmitters and receivers, devices can also be considered as masters or slaves when performing data transfers (see Table1). The master is the device which initiates a data transfers on the bus and generates the clock signals to permit that transfer. At that time, the device addressed is considered as the slave. TERM DESCRIPTION Transmitter The device which sends the data to the bus Receiver The device which receives the data from the bus Master The device which initiates a transfer, generates clock signals and terminates a transfer Slave The device addressed by a master Table 1. Definitions Pin arrangement AK6010A/12A S0 1 8 VCC S1 2 7 WC S2 3 6 SCL GND 4 5 SDA Pin Name Function S0, S1, S2 Device Address Inputs SCL Clock Input SDA Data Input / Output WC Write Control VCC Power Supply GND Ground Type of Products Model AK6010AF AK6012AF Memory size 32K bits 64K bits Temp. Range -40°C to +70°C -40°C to +70°C DAI02E-03 VCC 1.8V to 5.5V 1.8V to 5.5V Package 8pin Plastic SOP 8pin Plastic SOP 2002/11 - 2 - ASAHI KASEI [AK6010A/12A] DATA TRANSFER All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK6010A/12A recognizes the START condition, the devices interfaced to the bus wait for the slave address to be transmitted over the SDA line. If the transmitted slave address matches an address of one of the devices, the designated slave pulls the SDA line to LOW (ACKNOWLEDGE). The data transfer is always terminated by a STOP condition generated by the master. [Data validity] The data on the SDA line must be stable during the HIGH period of the clock. The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW. SCL SDA DATA STABLE DATA CHANGE Figure 1. Data transfer [START and STOP condition] A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition. All commands are preceded by the START condition. A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition. All communications are terminated by the STOP condition. After a read sequence, the STOP condition will place the EEPROM in a standby power mode. SCL SDA START CONDITION STOP CONDITION Figure 2. Start and Stop Definition DAI02E-03 2002/11 - 3 - ASAHI KASEI [AK6010A/12A] [ACKNOWLEDGE] ACKNOWLEDGE is a software convention used to indicate successful data transfers. The transmitting device will release the bus after transmitting eight bits. During the next clock (ninth clock), the receiver will pull the SDA line to LOW to acknowledge that it received the eight bits of data. The AK6010A/12A will respond with an acknowledge after recognition of a start condition and its slave address. If both the device and a write operation have been selected, the AK6010A/12A will respond with an acknowledge after the receipt of each subsequent eight bit word. In the read mode the AK6010A/12A slave will transmit eight bits of data, release the SDA line and monitor the line for an acknowledge. If an acknowledge is detected and no STOP condition is generated by the master, the slave will continue to transmit data. If an acknowledge is not detected, the slave will terminate further data transmissions and await the STOP condition to return to the standby power mode. SCL FROM MASTER 1 8 9 DATA OUTPUT FROM TRANSMITTER DATA OUTPUT FROM RECEIVER ACKNOWLEDGE Figure 3. Acknowledge Response from Receiver [SLAVE ADDRESS] After the START condition, a SLAVE ADDRESS is sent. If the transmitted slave address matches an address of one of the device, the designated slave pulls the SDA line to LOW. The most significant four bits of the slave address are fixed as "1010". The next three bits are S0, S1 and S2 device address bits. These three bits identify the specific device on the bus. They is set by the hard wired input pins (S0 pin, S1 pin and S2 pin). Therefore a total of eight devices can be connected to the same bus. The last bit of the slave address (R/W bit) defines whether a write or read condition is requested by the master. A "1" indicates that the read operation is to be executed. A "0" indicates that the write operation is to be executed. DEVICE ADDRESS 1 0 1 0 S2 S1 S0 R/W They is set by the hard-wired input pins (S0 pin, S1 pin and S2 pin). Figure 4. Slave Address DAI02E-03 2002/11 - 4 - ASAHI KASEI [AK6010A/12A] Pin Descriptions SCL (Serial Clock) The SCL input is used to clock all data into and out of the device. SDA (Serial Data) The SDA is a bidirectional pin used to transfer data into and out of the device. It is an open drain output and may be wire-ORed with any number of open drain or open collector outputs. S0, S1, S2 (Device Address) The S0, S1 and S2 are device address inputs that are used to set three bits of the slave address. A total of eight devices can be connected to the same bus. WC (Write Control) If the WC is High level, WRITE operations onto the upper quarter of the memory (AK6010A: C00 to FFF(Hex), AK6012A: 1800 to 1FFF(Hex)) will not be executed. If the WC is Low level, the AK6010A/12A will be enabled to perform WRITE operation. As the WC is internally pulled down to GND, the AK6010A/12A will be enabled to perform WRITE operation if the WC is left floating. WC must not change from the start condition input to the stop condition input. VCC (Power Supply) GND (Ground) DAI02E-03 2002/11 - 5 - ASAHI KASEI [AK6010A/12A] Functional Description WRITE Operations BYTE WRITE A write operation requires a word address following the slave address word (R/W=0) and acknowledge. The word address is comprised of eight bits and provides access to any one of the 4096/8192 words. Upon receipt of the word address the AK6010A/12A responds with an acknowledge, and awaits the next eight bits of data, again, responding with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the AK6010A/12A begins the internal write cycle to the nonvolatile memory. While the internal write cycle is in progress the AK6010A/12A inputs are disable, and the device will not respond to any requests from the master. Bus Activity: Master S T A R T SLAVE ADDRESS WORD ADDRESS SDA LINE S Bus Activity: AK6010A/12A WORD ADDRESS S T O P DATA P * * * S2 – S0 A C K A12 – A8 A C K A7 - A0 A C K A C K (note) Address bit A12 becomes a "don't care" for AK6010A. *: don't care BYTE WRITE PAGE WRITE The AK6010A/12A is capable of a thirty-two byte page write operation. It is initiated in the same manner as the byte write operation. But instead of terminating the write cycle after the first data word is transferred, the master can transmit up to thirty-one more words. After the receipt of each word, the AK6010A/12A will respond with an acknowledge. The master then terminates the transfer by generating a stop condition, at which time the AK6010A/12A begins the internal write cycle to the nonvolatile memory. After the receipt of each word, the five lower order address pointer bits are internally incremented by one. The higher order seven/eight bits of the word address remains constant. AK6010A: When the highest address is reached (XXXX XXX1 1111), the address counter rolls over to address "XXXX XXX0 0000" allowing the read cycle to be continued indefinitely. AK6012A: When the highest address is reached (X XXXX XXX1 1111), the address counter rolls over to address "X XXXX XXX0 0000" allowing the read cycle to be continued indefinitely. If the master should transmit more than thirty-two words prior to generating the stop condition, the address counter will "roll over" and the previously written data will be overwritten. When the master transmit thirty-four words prior to the stop condition, thirty-third word will be overwritten to first word, and thirty-fourth word will be overwritten to second word. Bus Activity: Master S T A R T SLAVE ADDRESS WORD ADDRESS(n) SDA LINE S Bus Activity: AK6010A/12A WORD ADDRESS(n) DATA(n) S T O P P DATA(n+31) * * * S2 – S0 A C K A12 – A8 A C K A7 - A0 (note) Address bit A12 becomes a "don't care" for AK6010A. A C K A C K A C K *: don't care PAGE WRITE DAI02E-03 2002/11 - 6 - ASAHI KASEI [AK6010A/12A] ACKNOWLEDGE POLLING Since the device will not acknowledge during the internal write cycle, this can be used to determine when the cycle is complete. This feature (ACK polling) can be used to maximize bus throughput. Once the stop condition is issued to indicate the end of the host's write operation the AK6010A/12A initiates the internal write cycle. ACK polling can be initiated immediately. This involves issuing the start condition followed by the slave address for a write operation. If the AK6010A/12A is still busy with the write operation no ACK will be returned. If the AK6010A/12A has completed the write operation an ACK will be returned and the host can then proceed with the next read or write operation. When the write operation is executed after the ACK polling, the host can issue the byte address consecutively after the ACK is returned. When the read operation is executed after the ACK polling, the host should issue the stop condition once. Bus Activity: Master S T A R T SLAVE ADDRESS SDA LINE S Bus Activity: AK6010A/12A A C K S T O P S T A R T P S SLAVE ADDRESS A C K AK6010A/12A initiates the internal write cycle. WRITE command If the AK6010A/12A is still busy with the write operation, no ACK will be returned. If the AK6010A/12A has completed the write operation, an ACK will be returned. ACKNOWLEDGE POLLING ACKNOWLEDGE POLLING DAI02E-03 2002/11 - 7 - ASAHI KASEI [AK6010A/12A] READ Operations There are three basic read operations: current address read, random read, and sequential read. Read operations are initiated in the same manner as write operations, with the exception that the R/W bit of the slave address is set to a one. It is noted that the ninth clock cycle of the read operation is not a "don't care". To terminate a read operation, the master must hold SDA HIGH during the ninth clock cycle and then issue a stop condition. CURRENT ADDRESS READ Internally the AK6010A/12A contains an address counter that maintains the address of the last word accessed, incremented by one. Therefore, if the last access (either a read or write) was to address n, the next read operation would access data from address n+1. Upon receipt of the slave address with R/W bit set to one, the AK6010A/12A issues an acknowledge and transmits the eight bit word. The master will not acknowledge the transfer but generate a stop condition, and therefore the AK6010A/12A discontinues transmission. Bus Activity: Master S T A R T SLAVE ADDRESS S T O P P DATA SDA LINE S Bus Activity: AK6010A/12A S2 – S0 A C K CURRENT ADDRESS READ RANDOM READ Random read operations allow the master to access any memory location in a random manner. Prior to issuing the slave address with the R/W bit set to one, the master must first perform a "dummy" write operation. The master issues the start condition, slave address and then the word address it is to read. After the word address acknowledge, the master immediately reissues the start condition and the slave address with the R/W bit set to one. This will be followed by an acknowledge from the AK6010A/12A and then by the eight bit word. The master will not acknowledge the transfer but generate the stop condition, and therefore the AK6010A/12A discontinues transmission. Bus Activity: Master S T A R T SLAVE ADDRESS SDA LINE S Bus Activity: AK6010A/12A WORD ADDRESS(n) S T A R T WORD ADDRESS(n) DATA(n) S * * * S2 – S0 A C K SLAVE ADDRESS A12 – A8 A C K A7 - A0 (note) Address bit A12 becomes a "don't care" for AK6010A. A C K S T O P P S2 – S0 A C K *: don't care RANDOM READ DAI02E-03 2002/11 - 8 - ASAHI KASEI [AK6010A/12A] SEQUENTIAL READ Sequential read can be initiated as either a current read or random read. The first word is transmitted in the same manner as the other read modes. However the master responds with an acknowledge, indicating it requires additional data. The AK6010A/12A continues to output data for each acknowledge received. The data output is sequential, with the data from address n followed by the data from n+1. The master will not acknowledge the transfer but generate the stop condition, and therefore the AK6010A/12A discontinues transmission. AK6010A: When the highest address is reached ($FFF), the address counter rolls over to address $000 allowing the read cycle to be continued indefinitely. AK6012A: When the highest address is reached ($1FFF), the address counter rolls over to address $0000 allowing the read cycle to be continued indefinitely. Bus Activity: Master SLAVE ADDRESS A C K A C K S T O P P A C K SDA LINE Bus Activity: AK6010A/12A A C K DATA(n) DATA(n+1) DATA(n+2) DATA(n+x) SEQUENTIAL READ DAI02E-03 2002/11 - 9 - ASAHI KASEI [AK6010A/12A] Absolute Maximum Ratings Parameter Power Supply All Input Voltages with Respect to Ground Ambient Storage Temperature Symbol VCC VIO Min -0.6 -0.6 Max +7.0 VCC+0.6 Unit V V Tst -65 +150 °C Stress above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. Exposure to absolute maximum conditions for extended periods may affect device reliability. Recommended Operating Condition Parameter Power Supply Ambient Operating Temperature Symbol VCC Ta DAI02E-03 Min 1.8 -40 Max 5.5 +70 Unit V °C 2002/11 - 10 - ASAHI KASEI [AK6010A/12A] Electrical Characteristics (1) D.C. ELECTRICAL CHARACTERISTICS (1.8V≤VCC≤5.5V, -40°C≤Ta≤70°C, unless otherwise specified) Parameter Current Dissipation (WRITE) Symbol ICC1 ICC2 ICC3 Current Dissipation (READ) ICC4 ICC5 ICC6 Current Dissipation (Standby) Input High Voltage Input Low Voltage Output Low Voltage ICCS VIH1 VIH2 VIL1 VIL2 VOL1 VOL2 Hysteresis of Schmitt trigger inputs (SCL, SDA) *2 Input Leakage Current *3 Output Leakage Current Condition AK6010A VCC=5.5V, fSCL=400KHz AK6012A AK6010A VCC=2.5V, fSCL=100KHz AK6012A AK6010A VCC=1.8V, fSCL=100KHz AK6012A AK6010A VCC=5.5V, fSCL=400KHz AK6012A AK6010A VCC=2.5V, fSCL=100KHz AK6012A AK6010A VCC=1.8V, fSCL=100KHz AK6012A VCC=5.5V *1 2.5V≤VCC≤5.5V 1.8V≤VCC<2.5V 2.5V≤VCC≤5.5V 1.8V≤VCC<2.5V 2.5V≤VCC≤5.5V IOL=4.5mA 1.8V≤VCC<2.5V IOL=3.0mA VHYS Min. Max. 4.0 5.0 3.5 4.5 2.5 3.5 500 700 200 250 150 200 0.8 Unit mA mA mA mA mA mA µA µA µA µA µA µA µA 0.7xVCC 0.8xVCC -0.3 -0.3 VCC+0.5 VCC+0.5 0.3xVCC 0.2xVCC 0.4 V V V V V 0.4 V 0.05xVCC V ILI VCC=5.5V, VIN=VCC/GND ±1.0 µA ILO VCC=5.5V, VOUT=VCC/GND ±1.0 µA *1: VIN=VCC/GND, WC=GND *2: The parameter is periodically sampled and not 100% tested. *3: SCL, SDA, S0, S1, S2 (2) CAPACITANCE (Ta=25°C, f=1MHz, VCC=5.0V) Parameter Input / Output Capacitance (SDA) Input Capacitance (SCL) Symbol CI/O Condition VI/O=0V CIN VIN=0V Min. Max. 8.0 Unit pF 6.0 pF (Note) The parameter is periodically sampled and not 100% tested. DAI02E-03 2002/11 - 11 - ASAHI KASEI [AK6010A/12A] (3) A.C. ELECTRICAL CHARACTERISTICS 1: Standard mode (1.8V≤VCC≤5.5V, -40°C≤Ta≤70°C, unless otherwise specified) Parameter SCK Clock Frequency Noise Suppression Time Constant at SCL, SDA *5 SCL Low to SDA Data Out Valid: SDA Time the Bus Must be Free before a New Transmission can start Start Condition Hold Time Symbol fSCL tI tAA1 tAA2 tAA3 tBUF Condition 4.5V≤VCC≤5.5V 2.5V≤VCC<4.5V 1.8V≤VCC<2.5V Min. Max. 100 100 Unit KHz ns 0.2 0.3 0.3 4.7 3.5 3.5 4.5 µs µs µs µs tHD:STA 4.0 µs Clock Low Period tLOW 4.7 µs Clock High Period tHIGH 4.0 µs Start Condition Setup Time tSU:STA 4.7 µs Data in Hold Time tHD:DAT 0 µs Data in Setup Time tSU:DAT 250 ns SDA and SCL Rise Time tR 1.0 µs SDA and SCL Fall Time tF 0.3 µs *5 Stop Condition Setup Time tSU:STO 4.0 µs Data Out Hold Time tDH 100 ns Write Cycle Time tWR *5 10 ms *4 *4: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal program cycle. Since the device will not acknowledge during the internal program cycle, this can be used to determine when the cycle is complete. This feature (ACK polling) can be used to maximize bus throughput. *5: The parameter is periodically sampled and not 100% tested. DAI02E-03 2002/11 - 12 - ASAHI KASEI [AK6010A/12A] (4) A.C. ELECTRICAL CHARACTERISTICS 2: Fast mode (4.5V≤VCC≤5.5V, -40°C≤Ta≤70°C, unless otherwise specified) Parameter SCK Clock Frequency Noise Suppression Time Constant at SCL, SDA *7 SCL Low to SDA Data Out Valid: SDA Time the Bus Must be Free before a New Transmission can start Start Condition Hold Time Symbol fSCL tI Condition Min. Max. 400 50 Unit KHz ns tAA 0.2 0.9 µs tBUF 1.3 µs tHD:STA 0.6 µs Clock Low Period tLOW 1.3 µs Clock High Period tHIGH 0.6 µs Start Condition Setup Time tSU:STA 0.6 µs Data in Hold Time tHD:DAT 0 µs Data in Setup Time tSU:DAT 100 ns SDA and SCL Rise Time tR 0.3 µs SDA and SCL Fall Time tF 0.3 µs *7 Stop Condition Setup Time tSU:STO Data Out Hold Time tDH *7 Write Cycle Time 0.6 µs 50 ns tWR 10 ms *6 *6: The write cycle time (tWR) is the time from a valid stop condition of a write sequence to the end of the internal program cycle. Since the device will not acknowledge during the internal program cycle, this can be used to determine when the cycle is complete. This feature (ACK polling) can be used to maximize bus throughput. *7: The parameter is periodically sampled and not 100% tested. AC Conditions of Test Input Pulse Levels Input Rise and Fall Times Output Timing Level 0.1xVCC to 0.9xVCC R= 466Ω (VCC=1.8V), 1133Ω (VCC=5.5V) 10ns 0.5xVCC C=100pF Equivalent AC Load Circuit DAI02E-03 2002/11 - 13 - ASAHI KASEI [AK6010A/12A] Synchronous Data Timing tF tHIGH tLOW tR SCL tSU:STA tHD:STA tHD:DAT tSU:DAT tSU:STO SDA IN tAA tDH tBUF SDA OUT BUS TIMING SCL SDA 8th BIT WORD n ACK tWR STOP CONDITION START CONDITION WRITE CYCLE TIMING DAI02E-03 2002/11 - 14 - IMPORTANT NOTICE • These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. 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