Data Sheet NE5550979A R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Silicon Power LDMOS FET FEATURES • • • • • High Output Power : Pout = 39.5 dBm TYP. (VDS = 7.5 V, IDset = 200 mA, f = 460 MHz, Pin = 25 dBm) High power added efficiency : ηadd = 66% TYP. (VDS = 7.5 V, IDset = 200 mA, f = 460 MHz, Pin = 25 dBm) High Linear gain : GL = 22 dB TYP. (VDS = 7.5 V, IDset = 200 mA, f = 460 MHz, Pin = 10 dBm) High ESD tolerance : ESD tolerance > 8 kV (IEC61000-4-2, Contact discharge) Suitable for VHF to UHF-BAND Class-AB power amplifier. APPLICATIONS • 150 MHz Band Radio System • 460 MHz Band Radio System • 900 MHz Band Radio System ORDERING INFORMATION Part Number NE5550979A Order Number NE5550979A-A NE5550979A-T1 NE5550979A-T1-A Package 79A (Pb Free) Marking W6 Supplying Form • 12 mm wide embossed taping • Gate pin faces the perforation side of the tape • • • • • • 12 mm wide embossed taping Gate pin faces the perforation side of the tape Qty 1 kpcs/reel NE5550979A-T1A NE5550979A-T1A-A 12 mm wide embossed taping Gate pin faces the perforation side of the tape Qty 5 kpcs/reel Remark To order evaluation samples, please contact your nearby sales office. Part number for sample order: NE5550979A ABSOLUTE MAXIMUM RATINGS (TA = 25°C, unless otherwise specified) Operation in excess of any one of these parameters may result in permanent damage. Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Total Power Dissipation Note Channel Temperature Storage Temperature Note: Symbol VDS VGS IDS Ptot Ratings 30 6.0 3.0 25 Unit V V A W Tch Tstg 150 −55 to +150 °C °C Value at TC = 25°C CAUTION Observe precautions when handling because these devices are sensitive to electrostatic discharge. The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 1 of 11 NE5550979A RECOMMENDED OPERATING RANGE (TA = 25°C) Parameter Drain to Source Voltage Gate to Source Voltage Drain Current Input Power Symbol VDS VGS IDS Pin Test Conditions f = 460 MHz, VDS = 7.5 V MIN. − 1.65 − − TYP. 7.5 2.20 1.7 25 MAX. 9.0 2.85 − 30 Unit V V A dBm ELECTRICAL CHARACTERISTICS (TA = 25°C, unless otherwise specified) Parameter DC Characteristics Gate to Source Leakage Current Drain to Source Leakage Current (Zero Gate Voltage Drain Current) Gate Threshold Voltage Drain to Source Breakdown Voltage Transconductance Thermal Resistance RF Characteristics Output Power Drain Current Power Drain Efficiency Power Added Efficiency Linear Gain Output Power Drain Current Power Drain Efficiency Power Added Efficiency Linear Gain Output Power Drain Current Power Drain Efficiency Power Added Efficiency Linear Gain Symbol IGSS IDSS Vth BVDSS Gm Rth Pout IDS ηd ηadd GL Note 1 Pout IDS ηd ηadd GL Note 2 Pout IDS ηd ηadd GL Note 1 Test Conditions MIN. TYP. MAX. Unit − − − − 100 10 nA μA VDS = 7.5 V, IDS = 1.0 mA IDS = 10 μA VDS = 7.5 V, IDS = 700±100 mA Channel to Case 1.15 25 1.8 − 1.65 37 2.2 5.0 2.25 − 2.9 − V V S °C/W f = 460 MHz, VDS = 7.5 V, Pin = 25 dBm, IDset = 200 mA (RF OFF) 38.5 − − − − − − − − − − − − − − 39.5 1.70 68 66 22.0 39.6 1.60 75 73 25.0 38.6 1.76 55 52 16.0 − − − − − − − − − − − − − − − dBm A % % dB dBm A % % dB dBm A % % dB VGS = 6.0 V VDS = 25 V f = 157 MHz, VDS = 7.5 V, Pin = 23 dBm, IDset = 200 mA (RF OFF) f = 900 MHz, VDS = 7.5 V, Pin = 27 dBm, IDset = 200 mA (RF OFF) Note 1 : Pin = 10 dBm Note 2 : Pin = 5 dBm Remark DC performance is 100% testing. RF performance is testing several samples per wafer. Wafer rejection criteria for standard devices is 1 reject for several samples. R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 2 of 11 NE5550979A TEST CIRCUIT SCHEMATIC FOR 460 MHz VGS VDS R1 C1 L1 C1 IN 50 Ω OUT C10 C22 C11 C12 C20 FET NE5550979A (WS) 50 Ω C21 COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS <R> Symbol C1 C10 C11 Value 1μF 100 pF 24 pF Type GRM31CR72A105KA01B GRM1882C1H101JA01 ATC100A240JW Maker Murata Murata C12 2.4 pF ATC100A2R4BW American Technical Ceramics C20 27 pF ATC100A270JW American Technical Ceramics C21 1.8 pF ATC100A1R8BW American Technical Ceramics C22 100 pF ATC100A101JW R1 4.7 kΩ L1 PCB SMA Connecter 123 nH − − 1/10 W Chip Resistor SSM_RG1608PB472 φ 0.5 mm, φ D = 3 mm, 10 Turns R1766, t = 0.4 mm, εr = 4.5, size = 30 × 48 mm WAKA 01K0790-20 American Technical Ceramics SSM American Technical Ceramics Ohesangyou Panasonic WAKA COMPONENT LAYOUT OF TEST CIRCUIT FOR 460 MHz V GS GND V DS C1 C1 L1 C12 C20 C21 R1 C11 C22 C10 R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 3 of 11 NE5550979A TYPICAL CHARACTERISTICS 1 (TA = 25°C) R: f = 460MHz, VDS = 3.6/4.5/6/7.5/8.4/9 V, IDset = 200 mA, Pin = 0 to 32 dBm IM: f1 = 460MHz, f2 = 461 MHz, VDS = 3.6/4.5/6/7.5/8.4/9 V, IDset = 200mA, Pout (2 tone) = 12 to 38 dBm POWER GAIN, POWER ADDED EFFICIENCY vs. INPUT POWER 40 Output Power Pout (dBm) 35 4.5 30 3.5 3.0 25 2.5 20 2.0 15 1.5 10 1.0 5 0.5 0 5 35 4.0 30 0 –5 40 10 15 20 25 30 Power Gain GP (dB) 45 5.0 Pout - 3.6 V Pout - 4.5 V Pout - 6.0 V Pout - 7.5 V Pout - 9 V IDS - 3.6 V IDS - 4.5 V IDS - 6.0 V IDS - 7.5 V IDS - 9 V Drain Current IDS (A) 50 0.0 35 25 15 30 10 20 5 10 0 5 2f0 - 3.6 V 2f0 - 4.5 V 2f0 - 6.0 V 2f0 - 7.5 V 3f0 - 3.6 V 3f0 - 4.5 V 3f0 - 6.0 V 3f0 - 7.5 V 2f0 - 9 V 3f0 - 9 V –40 –50 –60 15 20 25 30 35 10 15 20 25 30 0 35 IM3/IM5 vs. 2 TONES OUTPUT POWER 0 –30 –70 10 50 Input Power Pin (dBm) 3rd/5th Order Intermodulation Distortion IM3/IM5 (dBc) 2nd Harmonics 2f0 (dBc) 3rd Harmonics 3f0 (dBc) –20 60 40 0 –5 2f0, 3f0 vs. OUTPUT POWER –10 70 20 Input Power Pin (dBm) 0 80 Gp - 3.6 V Gp - 4.5 V Gp - 6 V Gp - 7.5 V Gp - 9 V η add - 3.6 V η add - 4.5 V η add - 6.0 V η add - 7.5 V η add - 9 V Power Added Efficiency η add (%) OUTPUT POWER, DRAIN CURRENT vs. INPUT POWER 40 45 Output Power Pout (dBm) –10 –20 IM3 - 3.6 V IM3 - 4.5 V IM3 - 6 V IM3 - 7.5 V IM5 - 3.6 V IM5 - 4.5 V IM5 - 6.0 V IM5 - 7.5 V IM3 - 9 V IM5 - 9 V –30 –40 –50 –60 –70 10 15 20 25 30 35 40 2 Tones Output Power Pout (2 tone) (dBm) Remark The graphs indicate nominal characteristics. R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 4 of 11 NE5550979A <R> TEST CIRCUIT SCHEMATIC FOR 157 MHz VGS VDS R1 C1 L1 C1 IN 50 Ω OUT C10 L11 C11 <R> C12 C24 L20 FET NE5550979A C20 C21 C22 50 Ω C23 COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS Symbol C1 C10 C11 Value 1μF 100 pF 4.7 pF Type GRM31CR72A105KA01B GRM1882C1H101JA01 ATC100A4R7CT C12 39 pF ATC100A390JT American Technical Ceramics C20 2.0 pF ATC100A2R0CT American Technical Ceramics C21 22 pF ATC100A220JT American Technical Ceramics C22 68 pF ATC100A680JT American Technical Ceramics C23 12 pF ATC100A120JT American Technical Ceramics C24 100 pF ATC100A101JT R1 4.7 kΩ L1 L11 L20 PCB SMA Connecter 123 nH 27 nH 35 nH − − 1/10 W Chip Resistor SSM_RG1608PB472 φ 0.5 mm, φ D = 3 mm, 10 Turns LLQ2012-F27N φ 0.5 mm, φ D = 2.4 mm, 5 Turns R1766, t = 0.4 mm, εr = 4.5, size = 30 × 48 mm WAKA 01K0790-20 American Technical Ceramics SSM R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Maker Murata Murata American Technical Ceramics Ohesangyou TOKO Ohesangyou Panasonic WAKA Page 5 of 11 NE5550979A COMPONENT LAYOUT OF TEST CIRCUIT FOR 157 MHz GND VGS VDS C1 C1 L1 L11 C12 C11 C10 C20 C21 C22 R1 L20 C23 C24 TYPICAL CHARACTERISTICS 2 (TA = 25°C) f = 157 MHz, VDS = 3.6/4.5/6/7.5/9 V, IDset = 200 mA, Pin = 0 to 27 dBm POWER GAIN, POWER ADDED EFFICIENCY vs. INPUT POWER OUTPUT POWER, DRAIN CURRENT vs. INPUT POWER 4.5 40 4.0 35 35 3.5 30 3.0 25 20 15 2.5 2.0 IDS - 3.6 V IDS - 4.5 V IDS - 6 V IDS - 7.5 V IDS - 9 V 1.0 5 0.5 0 5 80 Gp - 3.6 V Gp - 4.5 V Gp - 6 V Gp - 7.5 V Gp - 9 V η add - 3.6 V η add - 4.5 V η add - 6 V η add - 7.5 V η add - 9 V 70 60 25 50 20 40 15 30 10 20 5 10 1.5 10 0 –5 30 Power Gain GP (dB) Output Power Pout (dBm) 40 Pout - 3.6 V Pout - 4.5 V Pout - 6.0 V Pout - 7.5 V Pout - 9 V Drain Current IDS (A) 45 10 15 20 Input Power Pin (dBm) R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 25 0.0 30 0 –5 0 5 10 15 20 25 Power Added Efficiency η add (%) R: 0 30 Input Power Pin (dBm) Page 6 of 11 NE5550979A TEST CIRCUIT SCHEMATIC FOR 900 MHz VGS VDS R1 C1 L1 C1 IN 50 Ω OUT C10 C23 C11 <R> FET NE5550979A C20 C21 50 Ω C22 COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS Symbol C1 C10 C11 Value 1μF 100 pF 15 pF Type GRM31CR72A105KA01B GRM1882C1H101JA01 ATC100A150JW C20 3.3 pF ATC100A3R3BW American Technical Ceramics C21 3.3 pF ATC100A3R3BW American Technical Ceramics C22 12 pF ATC100A120JT American Technical Ceramics C23 100 pF ATC100A101JT R1 4.7 kΩ L1 PCB SMA Connecter 123 nH − − 1/10 W Chip Resistor SSM_RG1608PB472 φ 0.5 mm, φ D = 3 mm, 10 Turns R1766, t = 0.4 mm, εr = 4.5, size = 30 × 48 mm WAKA 01K0790-20 American Technical Ceramics SSM R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Maker Murata Murata American Technical Ceramics Ohesangyou Panasonic WAKA Page 7 of 11 NE5550979A COMPONENT LAYOUT OF TEST CIRCUIT FOR 900 MHz VGS VDS C1 C1 L1 R1 C22 C11 C10 C23 C20 C21 TYPICAL CHARACTERISTICS 3 (TA = 25°C) RF: f = 900 MHz VDS = 3.6/4.5/6/7.5/9 V, IDset = 200 mA, Pin = 0 to 32 dBm POWER GAIN, POWER ADDED EFFICIENCY vs. INPUT POWER Output Power Pout (dBm) 40 35 4.5 4.0 30 3.5 30 3.0 25 2.5 20 2.0 15 1.5 10 1.0 5 0.5 0 –5 0 5 35 10 15 20 25 30 0.0 35 Input Power Pin (dBm) Power Gain GP (dB) 45 40 5.0 Pout - 3.6 V Pout - 4.5 V Pout - 6.0 V Pout - 7.5 V Pout - 9 V IDS - 3.6 V IDS - 4.5 V IDS - 6.0 V IDS - 7.5 V IDS - 9 V Drain Current IDS (A) 50 25 80 Gp - 3.6 V Gp - 4.5 V Gp - 6 V Gp - 7.5 V Gp - 9 V η add - 3.6 V η add - 4.5 V η add - 6.0 V η add - 7.5 V η add - 9 V 70 60 50 20 40 15 30 10 20 5 10 0 –5 0 5 10 15 20 25 30 Power Added Efficiency η add (%) OUTPUT POWER, DRAIN CURRENT vs. INPUT POWER 0 35 Input Power Pin (dBm) Remark The graphs indicate nominal characteristics. R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 8 of 11 NE5550979A S-PARAMETERS S-parameters and noise parameters are provided on our web site in a form (S2P) that enables direct import of the parameters to microwave circuit simulators without the need for keyboard inputs. Click here to download S-parameters. [Products] → [RF Devices] → [Device Parameters] URL http://www.renesas.com/products/microwave/ R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 9 of 11 NE5550979A PACKAGE DIMENSIONS 79A (UNIT: mm) Source 1.0 MAX. 0.8±0.15 W Drain Gate Drain 0.4±0.15 1.2 MAX. Source 4.4 MAX. 1.5±0.2 21001 4.2 MAX. 6 Gate 0.6±0.15 5.7 MAX. (Bottom View) 0.8 MAX. 5.7 MAX. 0.9±0.2 0.2±0.1 3.6±0.2 79A PACKAGE RECOMMENDED P.C.B. LAYOUT (UNIT: mm) 4.0 1.7 Source Stop up the hole with a rosin or something to avoid solder flow. Drain 1.2 0.5 1.0 5.9 Gate Through Hole: φ 0.2 × 33 0.5 0.5 6.1 R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 10 of 11 NE5550979A RECOMMENDED SOLDERING CONDITIONS This product should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact your nearby sales office. Soldering Method Infrared Reflow Soldering Conditions Peak temperature (package surface temperature) Time at peak temperature Time at temperature of 220°C or higher Preheating time at 120 to 180°C Maximum number of reflow processes Maximum chlorine content of rosin flux (% mass) : 260°C or below : 10 seconds or less : 60 seconds or less : 120±30 seconds : 3 times : 0.2% (Wt.) or below Condition Symbol IR260 Wave Soldering Peak temperature (molten solder temperature) : 260°C or below Time at peak temperature : 10 seconds or less Preheating temperature (package surface temperature) : 120°C or below Maximum number of flow processes : 1 time Maximum chlorine content of rosin flux (% mass) : 0.2% (Wt.) or below WS260 Partial Heating Peak temperature (terminal temperature) : 350°C or below Soldering time (per side of device) : 3 seconds or less Maximum chlorine content of rosin flux (% mass) : 0.2% (Wt.) or below HS350 CAUTION Do not use different soldering methods together (except for partial heating). R09DS0031EJ0300 Rev.3.00 Mar 12, 2013 Page 11 of 11 Revision History Rev. Date NE5550979A Data Sheet Description Summary Page 1.00 Nov 25, 2011 − 2.00 Jul 04, 2012 p.1 Modification of ORDERING INFORMATION p.5 Addition of TEST CIRCUIT SCHEMATIC FOR 157 MHz p.6 Addition of COMPONENT LAYOUT OF TEST CIRCUIT FOR 157 MHz p.7 Addition of TEST CIRCUIT SCHEMATIC FOR 900 MHz p.8 Addition of COMPONENT LAYOUT OF TEST CIRCUIT FOR 900 MHz 3.00 Mar 12, 2013 First edition issued p.9 Modification of S-PARAMETERS P3 Modification of COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS P5 Modification of TEST CIRCUIT SCHEMATIC FOR 157 MHz P7 Modification of COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS Modification of COMPONENTS OF TEST CIRCUIT FOR MEASURING ELECTRICAL CHARACTERISTICS All trademarks and registered trademarks are the property of their respective owners. C-1 Notice 1. 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