Data Sheets - Skyworks Solutions, Inc.

DATA SHEET
SKY73103-11: 1460-1665 MHz High Performance
VCO/Synthesizer With Integrated Switch
Applications
Description
x 2G, 2.5G, and 3G base station transceivers:
GSM, EDGE, CDMA, WCDMA
Skyworks SKY73103-11 Voltage-Controlled Oscillator
(VCO)/Synthesizer is a fully integrated, high performance signal
source for high dynamic range transceivers. The device provides
ultra-fine frequency resolution, fast switching speed, and low
phase noise performance for 2G, 2.5G, and 3G base station
transceivers.
x General purpose RF systems
Features
The SKY73103-11 VCO/Synthesizer is a key building block for
high-performance radio system designs that require low power
and a fine step size. Reference clock generators with an output
frequency up to 52 MHz can be used with the SKY73103-11. The
input clock frequency is divided down by programmable dividers
(1 to 8) for the synthesizer. The phase detector can operate at a
maximum speed of 26 MHz, which allows better phase noise due
to the lower division value.
x Wideband frequency operation: 1460 to 1665 MHz
x Process-tolerant compensation for VCO
x 24-bit 6' fractional-N synthesizer
x Ultra-fine frequency resolution of 0.001 ppm
x Flexible reference frequency selection
x Three-wire serial interface up to 20 MHz clock frequency
The SKY73103-11 VCO/Synthesizer is provided in a compact, 38pin Multi-Chip Module (MCM). The device package and pinout are
shown in Figure 1. A functional block diagram is shown in
Figure 2. Signal pin assignments and functional pin descriptions
are provided in Table 1.
x Integrated PLL supply regulation for spur isolation
x MCM (38-pin, 9 x 12 mm) SMT package (MSL3, 260 qC per
JEDEC J-STD-020)
N/C
GND
GND
GND
36
GND
37
GND
GND
38
VDD
GND
Skyworks offers lead (Pb)-free, RoHS (Restriction of
Hazardous Substances) compliant packaging.
35
34
33
32
31
30
GND
1
29
GND
2
28
GND
GND
3
27
N/C
SW_EN
4
26
GND
GND
5
25
GND
GND
6
24
GND
GND
7
23
FREF
GND
8
22
LD
GND
9
21
N/C
20
GND
16
GND
GND
17
18
19
LE
15
CLK
14
DATA
13
N/C
GND
12
GND
10
11
GND
RF_OUT
GND
S958
Figure 1. SKY73103-11 Pinout– 38-Pin MCM Package
(Top View)
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Vtune
Varactor
DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Z = 1:4
VCO Out +
Lr
Cal
2
Lr
2
2
Buffer
RF Output
VCO Out –
SW_EN
SR Out +
7
SR Out –
2
Vtune
cap [6:0]
PLL
Low Pass Filter
Flag
FREF
SP1
SC1
R1
Divider
RF
PFD
RF Charge
Pump
CLK
LE
DAT
3-Wire
Serial
Interface
CPO RF
R1
N
PS
RFIN
P/P+1
Prescaler
N
Divider
7
RFINB
Mux
(LD/Test)
LD
FN
ΔΣ
Modulator
Divide-by-2
ME
Digital
Coarse
Calibration
cap [6:0]
7
Calibration
Complete
S1040
Figure 2. SKY73103-11 Functional Block Diagram
Table 1. SKY73103-11 Signal Descriptions
Pin #
Name
Description
Pin #
Name
Description
1
GND
Ground
20
GND
Ground
2
GND
Ground
21
N/C
No connection
3
GND
Ground
22
LD
Lock detect output
4
SW_EN
Synthesizer RF output switch enable
23
FREF
Frequency reference input
5
GND
Ground
24
GND
Ground
6
GND
Ground
25
GND
Ground
7
GND
Ground
26
GND
Ground
8
GND
Ground
27
N/C
No connection
9
GND
Ground
28
GND
Ground
10
RF_OUT
Synthesizer output
29
GND
Ground
11
GND
Ground
30
GND
Ground
12
GND
Ground
31
GND
Ground
13
GND
Ground
32
GND
Ground
14
N/C
No connection
33
N/C
No connection
15
GND
Ground
34
GND
Ground
16
GND
Ground
35
GND
Ground
17
CLK
Serial port clock
36
GND
Ground
18
DATA
Serial port data
37
VDD
+5 V power supply
19
LE
Serial port latch enable
38
GND
Ground
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Technical Description
The SKY73103-11 is a fractional-N frequency synthesizer using a
6'modulation technique. The fractional-N implementation
provides low in-band noise by having a low division and fast
frequency settling time. The device also provides programmable,
arbitrary fine frequency resolution. This compensates the
frequency synthesizer for crystal frequency drift.
Serial I/O Control Interface
The SKY73103-11 is programmed through a three-wire serial bus
control interface. The three-wire interface consists of three
signals: CLK (pin 17), LE (pin 19), and the bit serial data line DATA
(pin 18). A serial data input timing diagram is shown in Figure 3.
Timing parameter values are provided in Table 2.
Although the SKY73103-11 uses a 5 V DC supply, the internal
voltage regulator has a 3.3 V output for the Phase Locked Loop
(PLL). Therefore, the input DC voltage for the CLK, DATA, and LE
signals should be set ≤3.3 V.
Figure 4 depicts the serial bus, which consists of one 26-bit load
register and four separate 24-bit hold registers. Data is initially
clocked into the load register starting with the Most Significant Bit
(MSB) and ending with the Least Significant Bit (LSB).
The LE signal is used to gate the clock to the load register,
requiring the LE signal to be brought low before the data load.
Data is shifted on the rising edge of CLK. The falling edge of LE
latches the data into the appropriate hold register from the load
register. This programming sequence must be repeated to fill all
four hold registers.
The specific hold register addresses are determined by the wd_0
and wd_1 parameters in the load register. These are the two
LSBs (bits [1:0]) as shown in Figure 4. Table 3 lists the four hold
registers and their respective addresses as determined in the load
register.
The contents of each word in the load register are used to
program the four hold registers described in Tables 4 through 7.
The dpll_ctrl parameter (bits [19:2] of Word 1) programs the
Digital Phase Locked Loop (DPLL) block. Each of the 18 bits that
comprise the dpll_ctrl parameter map directly to the signal ports
on the DPLL block as shown in Table 8 (except for the
dpll_flag_override and dpll_flag_value parameters).
Loading new data into a hold register not associated with the
synthesizer frequency programming does not reset or change the
synthesizer. The synthesizer should not lose lock before, during,
or after a new serial word load that does not change the
programmed frequency.
VCO Auto-Tuning Loop
An auto-tuning loop provides the proper 7-bit coarse tuning
setting for the switch capacitors in the VCO tank circuits. This sets
the oscillation frequency as close to target as possible before
starting fine analog tuning.
The auto-tuning loop is designed to compensate for process
variation so that the VCO fine tuning range can be reduced to
cover minor variations only. The auto-tuning loop reduces VCO
gain (KV), which reduces the VCO phase noise.
The loop includes an analog part and a digital part (referred to as
the DPLL). The analog part includes the VCO, a high-speed
divider, and a VCO tuning voltage control block. The high-speed
divider consists of the prescaler (divide by 16/17 or divide by 8/9)
followed by an additional divide-by-2 block to generate the low
frequency internal signal, vco_clk.
There are two conditions that enable the VCO auto-tuning
function: a Power-On-Reset (POR) and a change in frequency. The
difference in the program flow under each of these conditions is
illustrated in Figure 5. Under either condition, dpll_en (bit [20] of
Word 1) should first be cleared so that a rising edge pulse can be
generated. Following this pulse, set dpll_en to enable VCO autotuning.
A POR timing diagram is shown in Figure 6. Auto-tuning details in
the frequency and time domains for the VCO are shown in
Figure 7.
DATA
tDHD
tDSU
tCKH
tCKL
CLK
tCLE
tLEC
tLEW
LE
S1053
Figure 3. SKY73103-11 Serial Data Input Timing Diagram (MSB First)
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Table 2. CLK, DATA, LE Timing Parameters
Parameter
Value
Input high voltage (VIH)
1.6 V
Input low voltage (VIL)
0.3 V
Input current (lDIG)
1 PA (maximum)
Clock frequency
15 MHz (maximum)
Clock high (tCKH)
15 ns (minimum)
Clock low (tCKL)
15 ns (minimum)
Data set up (tDSU)
20 ns (minimum)
Data hold (tDHD)
10 ns (minimum)
Clock to latch enable (tCLE)
20 ns (minimum)
Latch enable width (tLEW)
15 ns (minimum)
Latch enable to clock (tLEC)
15 ns (minimum)
Word length
26 bits
Number of words
4
Current drain
2 PA
Power-On
Preset
CLK
DATA
Load
Register
Bits [25:2]
(Words 0-3, bits [25:0])
Operation
Mode
Register
Latch
Word 0
Bits [25:2]
Word 1
Bits [25:2] Frequency
Auto
Calibration
Control
Register
Control 1
Register
Latch
Latch
Word 2
Bits [25:2]
Frequency
Control 2
Register
Word 3
Bits [25:2]
Latch
Words 0-3
Bits [1:0]
LE
2 LSB Decode
(Register Address,
Bits [1:0])
S918
Figure 4. Serial Bus Block Diagram
Table 3. SKY73103-11 Hold Registers and Addresses
Hold Register Name
Operation Mode
Hold Register Address (Binary) in Load Register Words
Bit [1]
Bit [0]
0
0
Auto Calibration Control
0
1
Frequency Control 1
1
0
Frequency Control 2
1
1
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Table 4. Load Register Word 0 (Programs the Operation Mode Register) (1 of 2)
Parameter
Function
wd_0, wd_1
Address bits [1:0]. Must be set to 00b (see
Table 3)
cp_output
Charge pump setting [4:2]
State Description
Recommended
Operational Value
(Binary)
00
Application
dependent
(see Table 11)
Bits [4:2]:
0 0 0 = 200 PA
0 0 1 = 400 PA
0 1 0 = 600 PA
0 1 1 = 800 PA
1 0 0 = 1000 PA
1 0 1 = 1200 PA
1 1 0 = 1400 PA
1 1 1 = 1600 PA
cp_delay
Charge pump delay [6:5]
00
Bits [6:5]:
0 0 = 2 nsec
0 1 = 4 nsec
1 0 = 7 nsec
1 1 = 9 nsec
pd_polar
Polarity of phase detector [7]
Bit [7]:
0
0 = negative
1 = positive
cp_tristate
Tri-state selection for the transmit PLL
charge pump output [8]
Bit [8]:
0
0 = charge pump in normal functional mode
1 = charge pump disabled/tri-stated
rsvd
Reserved [9]
Reserved
sd_sel
Internal operating voltage control bit for 6'
synthesizer [10]
Bit [12] Bit [11] Bit [10]: N-Cntr/R-Divider
Voltage
Note: this bit needs to be programmed
together with bits [11] and [12].
nr_sel
Internal operating voltage control bit for Ncounter and R-divider [11]
pll_en
Internal operating voltage control bit for PLL
[12]
0
1
1
1
1
0
X
0
0
1
1
X
0
1
0
1
=
=
=
=
=
0V
1.8 V
1.8 V
2.4 V
2.4 V
Mod Dig
Voltage
100
0V
1.8 V
2.4 V
1.8 V
2.4 V
This bit needs to be programmed together with bits [10] and [12].
–
This bit needs to be programmed together with bits [10] and [11].
–
See sd_sel parameter (bit [10])
See sd_sel parameter (bit [10])
ref_bw_sel
Reference buffer bandwidth [14:13]
Bits [14:13]:
0 0 = 20 MHz
0 1 = 30 MHz
1 0 = 40 MHz
1 1 = 50 MHz
test_mux
Lock detect and diagnostic output select
[17:15]
Bits [17:15]:
Application
dependent
(see Table 11)
000
0 0 0 = lock detect output
0 0 1 = R-divider output
0 1 0 = N-divider output
0 1 1 = not used
1 0 0 = not used
1 0 1 = not used
1 1 0 = not used
1 1 1 = DPLL test
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Table 4. Load Register Word 0 (Programs the Operation Mode Register) (2 of 2)
Parameter
Function
State Description
Recommended
Operational Value
(Binary)
rsvd
Reserved [20:18]
Reserved
000
pre_curr_sel
Prescaler current bias [22:21]
Bits [22:21]:
00
0 0 = 20 PA
0 1 = 22 PA
1 0 = 24 PA
1 1 = 26 PA
prescale_sel
Prescaler mode select [23]
Bit [23]:
Application
dependent
(see Table 11)
0 = Prescaler in 8/9 divide mode
1 = Prescaler in 16/17 divide mode
rsvd
Reserved [25:24]
Reserved
00
Table 5. Load Register Word 1 (Programs the Auto Calibration Control Register)
Parameter
wd_0, wd_1
Function
State Description
Recommended
Operational Value
(Binary)
Address bits [1:0]. Must be set to 01b (see
Table 3)
01
dpll_ctrl
DPLL control [19:2]
Refer to Table 8
dpll_en
VCO auto tuning enable flag [20]
0 = disable VCO auto tuning
1 = enable VCO auto tuning
–
rsvd
Reserved [25:21]
Reserved
Refer to Figure 5
00000
Table 6. Load Register Word 2 (Programs the Frequency Control 1 Register) (1 of 2)
Parameter
Function
wd_0, wd_1
Address bits [1:0]. Must be set to 10b (see
Table 3)
rdiv
Reference divider ratio [3:2]
State Description
Recommended
Operational Value
(Binary)
10
Application
dependent
(see Table 11)
Bits [3:2]:
00=8
01=4
10=2
11=1
rsvd
Reserved [5:4]
Reserved
ndiv
N-divider/prescaler mode for control of M
and A counters [15:6]
Bits [15:6]:
–
Bits [15:10]
Bits [9:6]
M bits [5:0]
M bits [5:0]
A bits [3:0] = use 16/17 prescaler
A bits [2:0] = use 8/9 prescaler
Application
dependent
Note: The six MSBs of ndiv denote the M counter value and the four
LSBs denote the A counter value. For the 8/9 prescaler mode, the A
counter value requires only three bits. Therefore, bit [9] of ndiv is a
“don’t care” bit.
rsvd
Reserved [16]
Reserved
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Table 6. Load Register Word 2 (Programs the Frequency Control 1 Register) (2 of 2)
Parameter
mod_reset_f
Function
Modulator reset/fractional mode select [17]
State Description
Recommended
Operational Value
(Binary)
Bit [17]:
1
0 = modulator is reset or disabled
1 = modulator is in fractional mode
fract_int_sel
Fractional/integer mode select [18]
Bit [18]:
1
0 = modulator is in integer mode
1 = modulator is in functional mode
rsvd
Reserved [19]
Reserved. This bit should always remain set (logic high).
me
Modulus extender [23:20]
These four bits need to be programmed together with bits [12:2] of
Word 3. Bits [23:20] represent the four LSBs ([3:0]) of the 15-bit
modulus extender value (ME [14:0]). Refer to the Synthesizer
Programming section of this Data Sheet for further information.
rsvd
Reserved [25:24]
Reserved
1
Application
dependent
00
Table 7. Load Register Word 3 (Programs the Frequency Control 2 Register)
Parameter
Function
State Description
Recommended
Operational Value
(Binary)
wd_0, wd_1
Address bits [1:0]. Must be set to 11b (see
Table 3)
11
me
Modulus extender [12:2]
These 11 bits need to be programmed together with bits [23:20] of
Word 2. Bits [12:2] represent the 11 MSBs ([14:4]) of the 15-bit
modulus extender value (ME [14:0]). Refer to the Synthesizer
Programming section of this Data Sheet for further information.
Application
dependent
fn
Fractional divisor code [20:13]
Bits [20:13] represent the 8-bit fractional divisor code (FN [7:0]).
Refer to the Synthesizer Programming section of this Data Sheet for
information.
Application
dependent
rsvd
Reserved [23:21]
These three bits should always remain cleared (logic low).
0
rsvd
Reserved [25:24]
Reserved
00
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Table 8. DPLL Signal Mapping
Serial Port Name
Load Register Word 1 Bit
Recommended Operation Value
dpll_clk_dly(0)
2
0
dpll_clk_dly(1)
3
0
dpll_temp_comp(0)
4
0
dpll_temp_comp(1)
5
0
dpll_temp_comp(2)
6
0
dpll_temp_comp(3)
7
0
dpll_temp_comp(4)
8
0
dpll_temp_comp_en
9
0
dpll_ext_test(0)
10
0
dpll_ext_test(1)
11
0
dpll_ext_test(2)
12
0
dpll_ext_test(3)
13
0
dpll_ext_test(4)
14
0
dpll_ext_test(5)
15
0
dpll_ext_test(6)
16
0
dpll_ext_test(7)
17
0
dpll_flag_override
18
0
dpll_flag_value
19
0
VCO Prescalers
The VCO prescalers divide the VCO output signal by either 16/17
or 8/9. The 6' modulator determines whether to divide by 16 or
17 in the 16/17 mode, or whether to divide by 8 or 9 in the 8/9
mode. The prescaler mode is determined by bit [23] of Word 0
(Operation Mode Register).
N-Counter
The N-counter consists of two asynchronous ripple counters, a 6bit M-counter and a 4-bit A-counter. The M-counter determines
the counts using the lower division ratio in the prescaler (8 or 16);
the A-counter determines the counts using the upper division ratio
(9 or 17).
By changing the counter setting at each reference clock cycle, the
Modulated Fractional Divider (MFD) achieves the desired noise
shaping.
VCO MFD Block
The MFD block divides down the prescaler output to the internal
PLL comparison frequency. A third order cascaded 6' modulation
technique minimizes spurs through randomization of the division
ratio.
The MFD block controls the division ratio by dynamically
programming the M and A counters.
Phase Detector and Charge Pump
The phase detector and charge pump detect and integrate the
phase and frequency errors of the divided-down VCO output
versus the reference clock. This results in a feedback adjustment
of the control voltage for the VCO.
Lock Detect
Lock detection circuitry provides a CMOS logic level indication
when the PLL is frequency locked (high when locked).
Reference Input Divider
The R-counter (reference input clock divider) consists of three
divide-by-two blocks and one multiplexer controlled by the rdiv
parameter in Word 2 (Frequency Control 1 Register). The Rcounter is used to select a divide-by-one or a divide-by-eight
function.
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
DC Power On
Frequency Change
Hardware Auto Reset
Clear dpll_en
(Word 1, Bit [20])
Clear dpll_en
(Word 1, Bit [20])
Send Only Changed
Words
Send Word 0, 1, 2, and 3
Set dpll_en
(Word 1, Bit [20])
Set dpll_en
(Word 1, Bit [20])
Send Word 1
Send Word 1
Lock on New Frequency
Lock on New Frequency
S998
Figure 5. VCO Auto-Tuning Enable Process Flow Due to POR or Frequency Change
Word 0
Word 1 (Bit [20] low)
Word 2
Word 3
Word 1 (Bit [20] high)
CLK
DATA
D25
D24
D1
D0
D25
D24
D1
D0
D25
D24
D1
D0
D25
D24
D1
D0
D25
D24
D1
D0
LE
Phase Settling Time
LD
S1296
Figure 6. POR Timing Diagram
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
1616
1614
1612
1610
1608
1606
Frequency (MHz)
1604
1602
1600
1598
1596
1594
1592
1590
1588
1586
Analog Tune
1584
1582
Digital Tune
(VCO Auto-Tuning)
1580
0
50
100
150
200
250
300
350
400
450
Time (μs)
500
S1387a
Figure 7. VCO Auto-Tuning @ 1600 MHz Frequency Settling
Synthesizer Output Switch
An on-chip switch is integrated into the SKY73103-11 RF output
after the balun and is controlled by the SW_EN signal (pin 4) as
indicated below:
The calculated value for DTotal can then be used to determine the
correct synthesizer frequency, RF:
RF
FREF
u DTotal
R1
(2)
Where: FREF = the reference frequency
SW_EN Input
Synthesizer Output
High
On
Low
Off
R1 = the reference divider radio
The 6-bit M-counter and the 4-bit A-counter portions of the Ncounter are calculated according to the following relationships:
Nactual is the actual N-counter value and is the integer portion of
(DTotal – 3.5):
The switch provides >50 dB isolation at the synthesizer RF
output. This allows the SKY73103-11 to be used for GSM
applications.
Nactual = Mactual × P + Aactual
If:
Synthesizer Programming
Where: Nactual = the actual value of the N-counter
FNactual = the actual fractional divisor
MEactual = the actual fractional modulus extender
Because of the way the '6 modulator is implemented in the
SKY73103-11, the number 3.5 must be added to the division
number to obtain the final division ratio.
M = Mactual (binary number, fit to six bits)
A = Aactual (binary number, fit to four bits)
To program the synthesizer to the correct frequency, values for
the N-counter (both M and A portions), fractional divisor (FN), and
fractional modulus extender (ME) are needed. These values are
used to determine the total divider ratio, DTotal, according to
Equation 1:
DTotal = Nactual + FNactual + MEactual + 3.5
(1)
Then: N = M × 24 + A
Where: N is the number to be programmed into the N-counter.
The synthesizer has a selectable prescaler of 8/9 or 16/17. If the
16/17 prescaler is used:
P = 24 = 16
In this case, N is the same as Nactual, M is equal to the six MSBs of
Nactual, and A is equal to the four LSBs of Nactual.
If the 8/9 prescaler is used:
P=8
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Here, N is not equal to Nactual. The A-counter portion only uses the
three LSBs (the 4th bit of the A-counter is a “don’t care” bit).
0.6575 u 256 = 168.32
The fractional divisor code (FN) sets the fractional-N modulo up to
256 modulo according to the following equation:
Divide FN by 256 to determine the actual fractional part, FNactual:
§ 1
§1·
D7 ¨¨ ¸¸ D6 ¨¨ 2
©2¹
©2
FN actual
·
§ 1
¸¸ D5 ¨¨
3
¹
©2
·
¸¸ ¹
x x
§ 1
x D0 ¨
¨ 8
©2
FNactual = 168/256 = 0.65625
·
¸¸
¹
(4)
The value of FN is equal to the binary representation of 256 (or 28)
u FNactual, or:
FN = D7 u 2 + D6 u 2 + D5 u 2 + . . . D0
7
6
5
10
11
Subtract this result from the fractional portion of (DTotal – 3.5) to
determine the actual fractional modulus extender, MEactual:
MEactual = (DTotal – 3.5 – Nactual) – FNactual
= 0.6575 – 0.65625
The fractional modulo can be extended up to 223 using the modulo
extender (ME) if required:
9
FN = 168 = 10101000b
23
MEactual = D14(1/2 ) + D13(1/2 ) + D12(1/2 ) + . . . + D0(1/2 )
The value of ME is equal to the binary representation of the
integer part of 223 u MEactual, or:
ME = D14 u 214 + D13 u 213 + D12 u 212 + . . .D0
= 0.00125
Multiply this result by 8388608 (the 23-bit '6 modulator value,
223) and remove the fractional portion to determine the value of
ME:
0.00125 u 8388608 = 10485.76
ME = 10485 = 010100011110101b
Example:
Package and Handling Information
A desired synthesizer frequency of 1537.25 MHz is required using
a crystal frequency of 16 MHz and a 16/17 prescaler. Since the
maximum internal reference frequency is 25 MHz, the crystal
frequency does not need to be divided. However, a reference
divider ratio of 2 is used for this example.
Since the device package is sensitive to moisture absorption, it is
baked and vacuum packed before shipping. Instructions on the
shipping container label regarding exposure to moisture after the
container seal is broken must be followed. Otherwise, problems
related to moisture absorption may occur when the part is
subjected to high temperature during solder assembly.
Restating Equation 2 as a function of DTotal:
DTotal = (1537.26 u 2)/16 = 192.1575
Where: RF = 1537.26
R1 = 2
FREF = 16
Determine Nactual by subtracting 3.5 from DTotal and removing the
fractional portion:
DTotal – 3.5 = 188.6575
Using Equation 3:
The SKY73103-11 is rated to Moisture Sensitivity Level 3 (MSL3)
at 260 qC. It can be used for lead or lead-free soldering. For
additional information, refer to Skyworks Application Note, PCB
Design and SMT Assembly/Rework Guidelines for MCM-L
Packages, document number 101752.
Care must be taken when attaching this product, whether it is
done manually or in a production solder reflow environment.
Production quantities of this product are shipped in a standard
tape and reel format. For packaging details, refer to the Skyworks
Application Note, Tape and Reel, document number 101568.
Nactual = 188 = Mactual u P + Aactual
Where: Mactual = 11
P = 16
Aactual = 12
M = Mactual = 11 = 001011b (the six MSBs)
A = Aactual = 12 = 1100b (the four LSBs)
N = M u 24 + A = 0010111100b (this is the same as Nactual)
Multiply the fractional portion that was removed in the previous
step by 256 and remove the fractional portion of the result to
determine FN:
Circuit Design Considerations
The following design considerations are general in nature and
must be followed regardless of final use or configuration
1. Paths to ground should be made as short and as low
impedance as possible.
2. The ground pad of the SKY73103-11 provides critical
electrical grounding requirements. Design the connection to
the ground pad to provide the best electrical connection to the
circuit board. Multiple vias to the grounding layer are
recommended to connect the top layer ground area to the
main ground layer.
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11
DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
3. Skyworks recommends including external bypass capacitors
on the VDD voltage input (pin 37) of the device. These
capacitors should be placed as close as possible to the VDD
input pin.
Measurement plots for single sideband phase noise and settling
time are shown in Figures 8 and 9, respectively.
4. A 50 : impedance trace is needed for the RF_OUT (pin 10)
line.
A typical application schematic for the SKY73103-11 is provided
in Figure 28. The PCB layout footprint of the SKY73103-11 is
provided in Figure 29. Figure 30 shows the package dimensions
for the 38-pin MCM, and Figure 31 provides the tape and reel
dimensions.
Typical performance characteristics of the SKY73103-11 are
illustrated in Figures 10 through 27.
Electrical and Mechanical Specifications
The absolute maximum ratings of the SKY73103-11 are provided
in Table 9. The recommended operating conditions are specified
in Table 10 and electrical specifications are provided in Table 11.
Spur suppression measurements are provided in Table 12.
Table 9. SKY73103-11 Absolute Maximum Ratings (Note 1)
Parameter
Supply voltage
Symbol
VCC
CLK, DATA, LE input DC voltage
Min
Typical
Max
Units
0
5.5
V
0
4.6
V
Operating temperature
TOP
–40
+85
°C
Storage temperature
TST
–40
+150
°C
Note 1: Exposure to maximum rating conditions for extended periods may reduce device reliability. There is no damage to device with only one parameter set at the limit and all other
parameters set at or below their nominal values. Exceeding any of the limits listed here may result in permanent damage to the device.
CAUTION: Although this device is designed to be as robust as possible, Electrostatic Discharge (ESD) can damage this device. This device
must be protected at all times from ESD. Static charges may easily produce potentials of several kilovolts on the human body
or equipment, which can discharge without detection. Industry-standard ESD precautions should be used at all times. The
SKY73103-11 threshold level is 2500 VDC using Human Body Model (HBM) testing. This level applies to RF signal lines
>100 MHz, analog and RF lines <100 MHz, digital lines, power supply lines, and ground pins.
Table 10. SKY73103-11 Recommended Operating Conditions
Parameter
Min
Typical
Max
Units
4.75
5.00
5.25
V
Input voltage (CLK, DATA, LE) (Note 1):
Low level
High level
1.4
3.3
0.6
3.6
V
V
Output voltage (LD) with 18 k: load from
VCC PLL:
Low level, unlocked
High level, unlocked
0.4
2.4
V
V
1.5
Vp-p
Supply voltage
Symbol
VCC
Reference frequency input voltage (FREF,
pin 23)
FREFIN
0.5
50 :, maximum VSWR (load input) 2.0:1, all phases
Load connected to RF output
RF output switch enable:
High
Low
1.0
SWENH
SWENL
2.2
0.8
Note 1: The CLK, DATA, and LE signals (pins 17, 18, and 19, respectively) are internally 3.3 VDC. DO NOT apply 5 VDC to these pins.
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V
V
DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Table 11. SKY73103-11 Electrical Characteristics (Note 1) (Note 2)
(VCC = 5 V, TC = 25 °C, cp_output = 1000 PA, FREF = 52 MHz, ref_bw_sel = 50 MHz, rdiv = 8, prescale_sel = 8/9, Unless Otherwise Noted)
Parameter
Symbol
Test Conditions
Oscillation frequency
Reference frequency
Min
Typical
1460
FREF
13
Phase detector frequency
Max
1665
MHz
52
MHz
6.5
PLL loop bandwidth
MHz
25
Output level
–12.0
Output impedance
–10.8
kHz
–8.0
2:1
Reference frequency (FREF) input impedance
Integrated RMS phase noise
–38
–61
100 Hz to 100 kHz
Single sideband phase noise offset:
@ 10 kHz
@ 200 kHz
@ 400 kHz
@ 600 kHz
@ 800 kHz
@ 1000 kHz
@ 1.8 MHz
@6 MHz
–
:
470
Harmonic suppression:
2nd harmonic
3rd harmonic
dBm
:
50
Output VSWR
Units
–86
–126
–137
–141
–143
–148
–150
–156
PLL-reference spurious suppression
–33
–52
dBc
dBc
1
degrees RMS
–82
–120
–129
–134
–138
–142
–145
–153
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
–100
dBc
Frequency settling time
Within r2 kHz
215
375
Ps
Phase settling time
Within r5 deg
230
450
Ps
2
5
degrees
Peak phase error
Switch isolation
48
Current consumption
52
114
dB
135
mA
Note 1: Performance is guaranteed only under the conditions listed in this Table.
Note 2: Characterized performance may change if the SKY73103-11 is configured differently than the test conditions specified here. This characterization used a 6.5 MHz fixed comparison
frequency for the PLL phase loop filter. The PLL synthesizer is programmable up to a maximum comparison frequency of 26 MHz but with degraded performance.
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13
DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
–60
1461 MHz
1600 MHz
1662 MHz
–70
–80
–90
Phase Noise (dBc/Hz)
–100
–110
–120
–130
–140
–150
–160
–170
–180
0.1
1
10
100
1000
10000
Offset Frequency (kHz)
S1000
Figure 8. SKY73103-11 Single Sideband Phase Noise Measurements
Table 12. SKY73103-11 Spur Suppression Measurements
(VCC = 5 V, TC = 25 °C, cp_output = 1000 PA, FREF = 52 MHz, rdiv = 8)
Frequency (MHz)
Offset From Center Frequency
(kHz)
1461
1499
1537
1600
1631
1662
100-400
No spur
No spur
No spur
No spur
No spur
No spur
400-600
No spur
No spur
No spur
No spur
498.51 kHz,
–97 dBc
No spur
600-1000
No spur
No spur
No spur
No spur
No spur
No spur
1000-3000
2232.74 kHz,
–100 dBc
2355.55 kHz,
–103 dBc
No spur
2272.95 kHz,
–103 dBc
No spur
No spur
3551.30 kHz,
–105 dBc
4478.81 kHz,
–107 dBc
3306.59 kHz,
–106 dBc
5074.89 kHz,
–102 dBc
2866.58 kHz,
–101 dBc
t 3000
No spur
No spur
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
20
1461 MHz
1600 MHz
1662 MHz
15
Relative Phase (deg)
10
5
0
–5
–10
–15
–20
0
0.05
0.10
0.15
0.20
0.25
0.30
0.35
0.40
0.45
0.50
Time (msec)
S1001
Figure 9. SKY73103-11 Settling Time Measurements
–5
–5
–6
–7
–6
–7
–8
POUT (dBm)
POUT (dBm)
–8
–9
–10
–11
–40 °C
+25 °C
+85 °C
–12
–13
–14
–15
1461
1491
1521
1551
1581
1611
–9
–10
–11
4.75 V
5.00 V
5.25 V
–12
–13
–14
–15
1461
1641
1491
1521
Figure 10. Output Power vs Frequency and Temperature
1611
1641
2.0
–40 °C
+25 °C
+85 °C
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Figure 12. Integrated Phase Noise vs Frequency and Temperature
Phase Noise (deg RMS)
Phase Noise (deg RMS)
1581
Figure 11. Output Power vs Frequency and Supply Voltage
2.0
0
1461
1551
Frequency (MHz)
Frequency (MHz)
4.75 V
5.00 V
5.25 V
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
1461
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Figure 13. Integrated Phase Noise vs Frequency and Supply
Voltage
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
500
–40 °C
+25 °C
+85 °C
450
400
350
300
250
200
150
100
50
0
1461
1491
1521
1551
1581
1611
Phase Settling Time (μs)
Phase Settling Time (μs)
500
1641
4.75 V
5.00 V
5.25 V
450
400
350
300
250
200
150
100
50
0
1461
1491
1521
Frequency (MHz)
Figure 14. Phase Settling Time vs Frequency and Temperature
–83
–84
–85
–86
–87
–88
–82
–83
–84
–85
–86
–87
–88
–89
–90
1491
1521
1551
1581
1611
1641
1461
1491
1521
Frequency (MHz)
1611
1641
–120
4.75 V
5.00 V
5.25 V
–121
–122
–123
–124
–125
–126
–40 °C
+25 °C
+85 °C
–127
–128
1491
1521
1551
1581
1611
Phase Noise (dBc/Hz)
–121
Phase Noise (dBc/Hz)
1581
Figure 17. Phase Noise @ 10 kHz Offset vs Frequency and Supply
Voltage
–120
–122
–123
–124
–125
–126
–127
–128
–129
–130
1461
1641
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Frequency (MHz)
Figure 18. Phase Noise @ 200 kHz Offset vs Frequency and
Temperature
Figure 19. Phase Noise @ 200 kHz Offset vs Frequency and
Supply Voltage
–130
–130
–132
–133
–134
–135
–136
–137
–138
4.75 V
5.00 V
5.25 V
–131
Phase Noise (dBc/Hz)
–40 °C
+25 °C
+85 °C
–131
Phase Noise (dBc/Hz)
1551
Frequency (MHz)
Figure 16. Phase Noise @ 10 kHz Offset vs Frequency and
Temperature
–132
–133
–134
–135
–136
–137
–138
–139
–139
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Figure 20. Phase Noise @ 400 kHz Offset vs Frequency and
Temperature
–140
1461
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Figure 21. Phase Noise @ 400 kHz Offset vs Frequency and
Supply Voltage
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1641
4.75 V
5.00 V
5.25 V
–81
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
–82
–140
1461
1611
–80
–40 °C
+25 °C
+85 °C
–81
–129
–130
1461
1581
Figure 15. Phase Settling Time vs Frequency and Supply Voltage
–80
–89
–90
1461
1551
Frequency (MHz)
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–140
–140
–141
–141
–142
–143
–142
–144
–145
–146
–147
–40 °C
+25 °C
+85 °C
–148
–149
–150
1461
1491
1521
1551
1581
1611
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
1641
–143
–144
–145
–146
–147
4.75 V
5.00 V
5.25 V
–148
–149
–150
1461
1491
1521
Frequency (MHz)
–145
–145
–146
–146
–147
–147
–148
–149
–150
–151
–152
–40 °C
+25 °C
+85 °C
–153
–154
1491
1521
1551
1581
1611
1641
4.75 V
5.00 V
5.25 V
–149
–150
–151
–152
–153
–154
–155
1461
1641
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Figure 24. Phase Noise @ 1.8 MHz Offset vs Frequency
Temperature
Figure 25. Phase Noise @ 1.8 MHz Offset vs Frequency and
Supply Voltage
–150
–150
–152
–153
–154
–155
–156
–157
–158
–159
4.75 V
5.00 V
5.25 V
–151
Phase Noise (dBc/Hz)
–40 °C
+25 °C
+85 °C
–151
Phase Noise (dBc/Hz)
1611
–148
Frequency (MHz)
–160
1461
1581
Figure 23. Phase Noise @ 800 kHz Offset vs Frequency and
Supply Voltage
Phase Noise (dBc/Hz)
Phase Noise (dBc/Hz)
Figure 22. Phase Noise @ 800 kHz Offset vs Frequency and
Temperature
–155
1461
1551
Frequency (MHz)
–152
–153
–154
–155
–156
–157
–158
–159
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Figure 26. Phase Noise @ 6 MHz Offset vs Frequency and
Temperature
–160
1461
1491
1521
1551
1581
1611
1641
Frequency (MHz)
Figure 27. Phase Noise @ 6 MHz Offset vs Frequency and Supply
Voltage
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
C2
10 nF
×
6
7
8
9
(50 Ω Controlled
Impedance Line)
10
GND
GND
GND
N/C
GND
GND
29
GND
GND
GND
GND
GND
N/C
28
27
×
26
SW_EN
GND
GND
GND
25
SKY73103
GND
24
GND
23
GND
Frequency
Reference
Lock Detect
FREF
22
GND
LD
GND
N/C
21
×
20
RF_OUT
GND
RF Output
30
11
12
GND
13
14
15
16
17
18
LE
5
31
DATA
4
32
CLK
RF Output
Switch Control
33
GND
3
34
GND
2
35
N/C
1
36
GND
37
GND
38
GND
+
VDD
C1
10 μF
GND
+5 V
From Regulator
19
×
Latch Enable
Data
Clock
S962
Figure 28. SKY73103-11 Typical Application Schematic
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
1.1
0.95
9.4
0.075
2X 0.2
Stencil aperture size for center
ground pads should be 80% to
100% (by area) of the solder
mask opening of the package.
Pin 1
0.075
0.8 0.95
Stencil and
Metallization
Component Outline
Soldermask Opening
SMT Pad Detail
Scale: 2X
1 X This Rotation
1X Rotated 180o
0.5 Typ
12X 0.1375
12.4
0.65
36X 1.4
0.5
1.0 Pitch
Typ
0.075
0.2
24X 0.28
0.075
0.8
0.95
Stencil and
Metallization
24X 0.27
Component Outline
12X 0.1375
SMT Pad Detail
Scale: 2X
7 X This Rotation
7X Rotated 180o
10X Rotated 90o CW
10X Rotated 90o CCW
Stencil Aperture
Top View
9.55
6.88
1.1
0.95
0.075
Component Outline
Soldermask Opening
36X 0.9
Component Outline
0.075
Pin 1
2X 0.2
0.95 0.8
Stencil and
Metallization
Soldermask Opening
SMT Pad Detail
Scale: 2X
1 X This Rotation
1X Rotated 180o
0.5 Typ
12.55
9.4
9.88
1.0 Pitch
Typ
2X 4.3
(2.8)
Pin 1
0.25
Typ
2X 5.8
Component Outline
Solder Mask Opening
Top View
(3.4)
0.5 Typ
12.4
(4.3)
1.0 Pitch
Typ
Thermal Via Array.
∅0.3 mm on 0.6 mm pitch.
Additional vias in common ground
pad will improve thermal and
electrical performance.
NOTE: thermal vias should be tented
and filled with solder mask,
30-35 μm Cu plating recommended.
Component Outline
Metallization
Top View
All measurements are in millimeters
Note: The cross-hatched area represents the merger of the center
ground pad +24 individual I/O ground pads. All I/O ground
pads should have at least one via connected to internal ground
planes for optimum electrical performance.
S1285
Figure 29. PCB Layout Footprint for the SKY73103-11 9 x 12 mm MCM
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Pin 1 Indicator
9
12X 2.937
12X 1.762
12X 0.587
4X 1
4X 2
4X 3
24X 4.4
DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
38X SMT Pad
0.1 A B C
B
0
C
18X 5.9
Pin 38
C
Pin 1 Indicator
See Detail D
Pin 1
4X 4.5
4X 3.5
A
4X 2.5
4X 1.5
4X 0.5
12
0
12X 0.837
12X 2.512
See Detail E
36X Solder Mask Openings
0.2 A B C
12X 4.187
B
A
1.70 ± 0.1
0.15 A B C
0.1
Side View
Top View
Bottom View
0.2 x 0.2
0.5 ± 0.1
(0.1)
Metal Pad Edge
0.65 ± 0.1
2X (0.1)
0.5 ± 0.05
1.5
0.5 ± 0.1
Metal Pad Edge
Solder Mask Edges
1.5
0.5 ± 0.1
2X (0.1)
Solder Mask Edges
0.65 ± 0.1
Metal Pad Edge
Detail A
Detail B
Detail C
SMT Pad
Scale: 2X
10X This Rotation
10X Rotated 180o
7X Rotated 90o CW
7X Rotated 90o CCW
SMT Pad
Scale: 2X
1X This Rotation
1X Rotated 180o
SMT Pad
Scale: 2X
1X This Rotation
1X Rotated 180o
1.0
Solder Mask Edges
1.0
Detail D
Detail E
Scale: 2X
Scale: 2X
35X This Rotation
All measurements are in millimeters.
Dimensioning and tolerancing according to ASME Y14.5M-1994.
S1286
Figure 30. SKY73103-11 38-Pin MCM Package Dimensions
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DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
12.00 (P1)
4.00 (Po)
2.00 ± 0.05
∅1.55 ± 0.05
0.30 ± 0.05 (T)
Pin #1
indicator
1.75 ± 0.10
A
11.50 ± 0.05
B
24.00 ± 0.30
12.30 (Bo)
A
B
9.30 (Ao)
2.00 (Ko)
∅1.50 Min.
B
Notes:
1. Carrier tape material: black conductive polystyrene
2. Cover tape material: transparent conductive PSA
3. Cover tape size: 21.3 mm width
4. Po/P1 10 pitches cumulative tolerance on tape: ±0.20 mm
5. Ao and Bo measurement point to be 0.30 mm from bottom pocket
6. All measurements are in millimeters
A
S1832
Figure 31. SKY73103-11 Tape and Reel Dimensions
Skyworks Solutions, Inc. • Phone [781] 376-3000 • Fax [781] 376-3100 • [email protected] • www.skyworksinc.com
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21
DATA SHEET • SKY73103-11 VCO/SYNTHESIZER
Ordering Information
Model Name
SKY73103-11 1460-1665 MHz VCO/Synthesizer
Manufacturing Part Number
SKY73103-11 (Pb-free package)
Evaluation Kit Part Number
TW17-D770
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November 30, 2009 • Skyworks Proprietary Information • Products and Product Information are Subject to Change Without Notice • 200649D