SC195B - Semtech

SC195B
3.5MHz, 500mA Synchronous
Step Down DC-DC Regulator
POWER MANAGEMENT
Features
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Description
Input Voltage — 2.9V to 5.5V
Output Voltage — 0.8V to 3.6V
Output current capability — 500mA
Efficiency up to 94%
15 Programmable output voltages
High light-load efficiency via automatic PSAVE mode
Fast transient response
Temperature range — -40 to +85°C
Oscillator frequency — 3.5MHz
100% duty cycle capability
Quiescent current — 38µA typ
Shutdown Current — 0.1µA typ
Internal soft-start
Over-voltage protection
Current limit and short circuit protection
Over-temperature protection
Under-voltage lockout
Floating control pin protection
WLCSP8-0.80 X 0.80 X 0.375 (mm) package
Pb free, halogen free, and RoHS/WEEE compliant
Applications
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Smart phones and cellular phones
MP3/Personal media players
Personal navigation devices
Digital cameras
Single Li-ion cell or 3 NiMH/NiCd cell devices
Devices with 3.3V or 5V internal power rails
The SC195B is a high efficiency, 500mA step down regulator designed to operate with an input voltage range of
2.9V to 5.5V. The input voltage range makes it ideal for
battery operated applications with space limitations. The
SC195B also includes fifteen programmable output
voltage settings that can be selected using the four
control pins, eliminating the need for external feedback
resistors. The output voltage can be fixed to a single
setting or dynamically switched between different levels.
Pulling all four control pins low disables the output and
puts the device into a low current shutdown state.
The SC195B operates at a fixed 3.5MHz switching frequency in normal PWM (Pulse-Width Modulation) mode.
A variable frequency PSAVE (power-save) mode is used to
optimize efficiency at light loads for each output setting.
Built-in hysteresis prevents chattering between the two
modes.
The SC195B provides several protection features to safeguard the device under stressed conditions. These
include short circuit protection, over-temperature protection, over-voltage protection, under-voltage lockout, and
soft-start to control in-rush current. These features
coupled with the small 8-bump 0.80 X 0.80 X 0.375 (mm)
package make it a versatile device ideal for step-down
regulation in products needing high efficiency and a
small PCB footprint.
Typical Application Circuit
VIN
2.9V to 5.5V
CIN
4.7µF
Control Logic
(May also be
hard wired to
VIN/ GND)
Rev 2.1
SC195B
V IN
CTL3
CTL2
CTL1
CTL0
LX
OUT
L1
1µH
VOUT
0.8V to 3.6V
COUT
10µF
GND
Semtech Corporation
SC195B
Bump Configuration
Ordering Information
Device
Package
SC195BCSTRT(1)(2)
WLCSP8-0.80X0.80X0.375
SC195BEVB
Evaluation Board
Top View
A
B
1
2
3
CTL2
CTL0
CTL1
CTL3
IN
LX
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Lead-free packaging only. Device is WEEE and RoHS compliant
and halogen-free.
GND
OUT
C
WLCSP8 0.80 X 0.80 (mm)
θJA = 107 °C/W
Table 1 – Output Voltage (CTL) Settings
Marking Information
MM
A1 Corner Bump and Part Number Marking Code
CTL3
CTL2
CTL1
CTL0
Vout
0
0
0
0
Shutdown
0
0
0
1
0.80
0
0
1
0
1.00
0
0
1
1
1.10
0
1
0
0
1.20
0
1
0
1
1.35
0
1
1
0
1.50
0
1
1
1
1.60
1
0
0
0
1.80
1
0
0
1
2.00
1
0
1
0
2.50
1
0
1
1
2.80
1
1
0
0
3.00
1
1
0
1
3.30
1
1
1
0
3.40
1
1
1
1
3.60
SC195B
Absolute Maximum Ratings
Recommended Operating Conditions
IN (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0
Input Voltage Range (V). . . . . . . . . . . . . . . . . . . . . +2.9 to +5.5
LX Voltage (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -1.0 to (VIN +0.5)
Operating Temperature Range (°C) . . . . . . . . . . -40 to +85
Other Pins (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to (VIN + 0.3)
Thermal Information
Output Short Circuit to GND. . . . . . . . . . . . . . . . . Continuous
ESD Protection Level(1) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.5
Thermal Resistance, Junction to Ambient(2) (°C/W) . . . . . . . 107
Junction Temperature Range (°C) . . . . . . . . . . . . - 40 to +150
Storage Temperature Range (°C). . . . . . . . . . . . . -65 to +150
Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters
specified in the Electrical Characteristics section is not recommended.
NOTES:
(1) Tested according to JEDEC standard JESD22-A114.
(2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB per JESD51 standards.
Electrical Characteristics
Unless otherwise specified: VIN= 3.6V, CIN= 4.7µF, COUT=10µF, LX=1µH, VOUT=1.8V, TJ(MAX)=125°C, TA= -40 to +85 °C. Typical values are TA=+25 °C
Parameter
Output Voltage Range(1)
Symbol
Condition
VOUT
Iout = 200mA, PWM Mode
Output Voltage Tolerance (2)
VOUT_TOL
Min
Typ
Max
Units
0.8
3.6
V
-2.0
2.0
%
PSAVE mode
1.5
Line Regulation
ΔVLINEREG
2.9 ≤ VIN ≤ 5.5V, PWM mode
0.3
%/V
Load Regulation
ΔVLOADREG
200mA ≤ Iout ≤ 500mA, PWM mode
-1
%/A
CTL Setting Regulation
ΔVCTLREG
Relative to VOUT at CTL =1000;
Iout = 200mA, PWM mode
+/- 0.3
%
Output Current Capability
IOUT
500
Current Limit Threshold
ILIMIT
800
Foldback Current Limit
IFB_LIM
Under-Voltage Lockout
VUVLO
ILOAD > ILIMIT; VOUT forced to 1V
mA
1500
215
Rising VIN
mA
2.9
Hysteresis
200
mA
V
mV
Quiescent Current(3)
IQ
No switching, IOUT = 0mA,
CTLx = VIN or GND
38
60
µA
Shutdown Current
ISD
VCTL 0-3= 0V
0.1
1.0
µA
LX Leakage Current
ILX
Into LX pin
0.1
1.0
µA
SC195B
Electrical Characteristics (continued)
Parameter
Symbol
Condition
Min
Typ
Max
Units
High Side Switch Resistance(4)
RDSON_P
IOUT= 100mA, TA=+25 °C
100
250
850
Low Side Switch Resistance(5)
RDSON_N
IOUT= 100mA, TA=+25 °C
200
350
900
2.8
3.5
4.2
MHz
500
µs
mΩ
Switching Frequency
fSW
Soft-Start
tSS
VOUT = 90% of final value
100
Thermal Shutdown
TOT
Rising temperature
160
°C
20
°C
Thermal Shutdown Hysteresis
THYST
Logic Inputs - CTL0, CTL1, CTL2, and CTL3(2)
Input High Voltage
VIH
2.9V < VIN < 5.5V
Input Low Voltage
VIL
2.9V < VIN < 5.5V
Input High Current(3)
IIH
VCTL 0-3= VIN
Input Low Current(3)
IIL
VCTL 0-3= GND
1.6
V
0.4
V
-1.0
1.0
µA
-1.0
1.0
µA
Notes
(1) Maximum output voltage is limited to VIN.
(2) VIN = 3.6V for VOUT < 3.0V. VIN = 4.0V for VOUT > 3.0V.
(3) Recommend connection for all CTLx inputs is VIN or GND. Refer to “CTL Input Resistance” in the Applications Information.
(4) Measured from IN to LX.
(5) Measured from LX to GND.
SC195B
Typical Characteristics
VIN = 4.0V for VOUT = 3.3V, VIN = 3.6V for all others. CIN = 4.7µF, COUT = 10µF, LX = 1µH, TA = 25°C unless otherwise noted.
Load Regulation, Vout=1.8V
Efficiency vs. IOUT (TA = -40°C)
1 .88
100
90
3 .3 V
2 .8 V
1 .8 V
80
1 .84
1V
60
50
V o u t (V )
Efficiency (%)
70
1 .86
40
1 .82
1 .8
30
20
1 .78
10
0
85 °C
25 °C
-40 °C
0.1
1
10
Load Current (mA)
100
1 .76
1000
0
0.2
0.3
Load (A )
0 .4
0 .5
0 .6
Line Regulation, Vout=1.8V/400mA
Efficiency vs. IOUT (TA = 25°C)
1 .8 8
100
90
1 .8 6
3 .3 V
2 .8 V
80
1 .8 V
70
60
1 .8 4
1V
V ou t (V )
Efficiency (%)
0.1
50
40
1 .8 2
8 5 °C
2 5 °C
-4 0 °C
1 .8 0
30
20
1 .7 8
10
0
0 .1
1
10
Load Current (mA)
100
1000
1 .7 6
2 .5
3.0
4.5
5 .0
5 .5
Efficiency vs. Vin, 1.8V/400mA
90
100
70
3 .3V
2 .8V
1 .8V
60
1V
80
89
88
E fficien cy (% )
90
Efficiency (%)
4 .0
V in (V )
Efficiency vs. IOUT (TA = 85°C)
50
40
30
87
-4 0 °C
86
2 5 °C
85
84
20
8 5 °C
83
10
0
3 .5
0 .1
1
10
Load Current (mA)
100
1000
82
2 .5
3 .0
3.5
4 .0
V in (V )
4 .5
5 .0
5 .5
SC195B
Typical Characteristics (continued)
Light Load Switching — VOUT = 1.8V
Light Load Switching — VOUT = 1.0V
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div)
ILX (200mA/div)
Time (400ns/div)
Time (400ns/div)
Light Load Switching — VOUT = 3.3V
Light Load Switching — VOUT = 2.8V
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div)
ILX (200mA/div)
Time (400ns/div)
Time (400ns/div)
Heavy Load Switching — VOUT = 1.8V
Heavy Load Switching — VOUT = 1.0V
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2.0V/div)
VLX (2V/div)
ILX (200mA/div)
ILX (200mA/div)
Time (200ns/div)
Time (200ns/div)
SC195B
Typical Characteristics (continued)
Heavy Load Switching — VOUT = 2.8V
Heavy Load Switching — VOUT = 3.3V
VOUT (50mV/div)
VOUT (50mV/div)
VLX (2V/div)
VLX (2V/div)
ILX (200mA/div)
ILX (200mA/div)
Time (200ns/div)
Time (200ns/div)
Light Load Soft-start
Heavy Load Soft-start
ILOAD = 500mA
ILOAD = 10mA
IIN (200mA/div)
IIN (200mA/div)
VOUT (1.0V/div)
Vout (1.0V/div)
ILX (500mA/div)
ILX (500mA/div)
Time (40μs/div)
Load Transient Response — 10 to 80mA
VOUT (50mV/div)
Time (40μs/div)
Load Transient Response — 10 to 500mA
VOUT (100mV/div)
ILX (200mA/div)
ILX (500mA/div)
ILOAD (50mA/div)
ILOAD (500mA/div)
Time (20μs/div)
Time (20μs/div)
SC195B
Typical Characteristics (continued)
Load Transient Response — 200 to 500mA
VID Transient Response — PWM
1.2V to 1.8V transition
VOUT (100mV/div)
VOUT (500mV/div)
ILX (500mA/div)
ILX (200mA/div)
ILOAD (500mA/div)
VCTL2 (2.0V/div)
Time (20μs/div)
Time (20μs/div)
Shutdown Transient Response
VID Transient Response — PSAVE
1.2V to 1.8V transition
VOUT (2V/div)
VOUT (500mV/div)
ILX (200mA/div)
ILX (200mA/div)
VCTL3-0 (2V/div)
VCTL2 (2.0V/div)
Time (20μs/div)
Time (20μs/div)
Line Transient Response — PSAVE
Line Transient Response — PWM
3.5V to 4.0V transition on VIN
VOUT (100mV/div)
3.5V to 4.0V transition on VIN
VOUT (100mV/div)
ILX (200mA/div)
ILX (200mA/div)
VIN 500mV/div)
VIN (500mV/div)
Time (20μs/div)
Time (40μs/div)
SC195B
Bump Descriptions
Bump
Bump Name
Bump (Pin) Function
A1
ctl2
Control bit 2 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL2 is pulled above the logic high threshold.
A2
ctl0
Control bit 0 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL0 is pulled above the logic high threshold.
A3
ctl1
Control bit 1 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL1 is pulled above the logic high threshold.
B1
in
B3
ctl3
C1
lx
C2
GND
Ground reference and power ground.
C3
out
Output voltage sense pin — output voltage regulation point (connection node of inductor and output
capacitor).
Input power supply pin — connect a bypass capacitor from this pin to GND.
4.7µF minimum is recommended.
Control bit 3 — see Table 1, page 2, for decoding. This pin has a weak pull-down resistor (> 1MΩ) in place at
reset that is removed when CTL3 is pulled above the logic high threshold.
Switching output — connect an inductor between this pin and the output capacitors and load to filter the LX
switching pulses.
Bump Array Configuration
Top View
A
B
1
2
3
CTL2
CTL0
CTL1
CTL3
IN
LX
GND
OUT
C
SC195B
Block Diagram
P lim it A m p
B1
IN
C u rre n t A m p
PMOS
O S C & S lo p e
G e n e ra to r
C o n tro l
L o g ic
PW M
Com p
5 0 0m V
Ref
NMOS
E rro r A m p
CTL3
B3
CTL2 A 1
CTL1 A 3
CTL0
C 1 LX
PSAVE
Com p
Z e ro C u rre n t
D e te ct
C 2 GND
V o lta g e
S e le ct
A2
OUT C 3
10
SC195B
Applications Information
General Description
The SC195B is a synchronous step-down Pulse Width
Modulated (PWM) DC-DC regulator utilizing a 3.5MHz
fixed-frequency voltage mode architecture. The device is
designed to operate in fixed-frequency PWM mode and
enter power save (PSAVE) mode utilizing pulse frequency
modulation under light load conditions to maximize efficiency. The device requires only two capacitors and a
single inductor to be implemented in most systems. The
switching frequency has been chosen to minimize the size
of the inductor and capacitors while maintaining high
efficiency. The output voltage is programmable, eliminating the need for external programming resistors. Loop
compensation is also internal, eliminating the need for
external components to control stability.
Programmable Output Voltage
The SC195B has 15 fixed output voltage levels which can
be individually selected by programming the CTL control
pins (CTL3-0 — see Table 1 on page 2 for settings). The
device is disabled whenever all four CTL pins are pulled
low and enabled whenever at least one of the CTL pins is
pulled high. This configuration eliminates the need for a
dedicated enable pin.
CTL Input Resistance
Each CTL pin is internally pulled down via 1MΩ at power
up if VIN is below 1.5V or if the voltage on the control pin is
below the input high voltage. This ensures that the output
is disabled when power is applied if there are no inputs to
the CTL pins. Each 1MΩ pull-down is disabled whenever
its pin is pulled high and remains disabled until all CTL
pins are pulled low.
Output Voltage Setting
The output voltage can be set using different approaches.
If a static output voltage is required, the CTL pins can be
tied to either IN or GND to set the desired voltage whenever power is applied at IN. If enable control is required,
each CTL pin can be tied to either GND or to a microprocessor I/O line to create the desired control code whenever
the control signal is forced high. This approach is equivalent to using the CTL pins collectively as a single enable
pin. A third option is to connect each of the four CTL pins
to individual microprocessor I/O lines. Any of the 15
output voltages can be programmed using this approach.
If only two output voltages are needed, the CTL pins can
be combined in a way that will reduce the number of I/O
lines to 1, 2, or 3, depending on the control code for each
desired voltage. Other CTL pins could be hard wired to
GND or IN. This option allows dynamic voltage adjustment for systems that reduce the supply voltage when
entering sleep states. Note that applying all zeros to the
CTL pins when changing the output voltages will temporarily disable the device, so it is important to avoid this
combination when dynamically changing levels.
Dynamic Output Voltage Adjustment
Dynamically changing the CTL pins allows dynamic
voltage adjustment for systems that reduce the supply
voltage when entering sleep states. This should be done
using specific procedures. Attention is required since
applying all zeros in a very short period to the CTL pins
when changing the output voltage will temporarily
disable the device. Therefore it is important to avoid the
combination of all zeros when dynamically changing the
CTL levels. For example, when the CTLs change from
0001 to 0010 (0.8V to 1.0V), a transitional state of 0000
(shut down) state might occur for a very short period of
time, which could result the device being disabled unintentionally. In order to achieve such operation, the correct
logic transition stages can be arranged in this way: 0001-0011--0010 (0.8V--1.1V--1V). The very short transition
state 0011 would keep the part in operation but not
affect the voltage transition waveform.
When the CTL pins are changed to raise the output
voltage, the regulator increases the inductor current to
force the output voltage to slew up. A large change in
the voltage setting could result in over-current due to
charging the output capacitor. For large voltage steps it
is recommended to use minimal output capacitors and to
raise the voltage in smaller steps to reduce the transient
inductor current.
When the CTL pins are changed to decrease the output
voltage, the output response will vary depending on the
operating mode. If the device is operating in PWM mode,
the regulator will continue active switching and will bring
the output capacitors down to match the new CTL
setting. If the device is operating in PSAVE mode, the
11
SC195B
Applications Information (continued)
regulator will stop switching; in this case the regulator
relies on the load current to discharge the output capacitors and bring the output voltage down to the desired
setting.
Note that if the commanded decrease in output voltage
exceeds the Over-voltage threshold, the device will detect
an Over-voltage condition regardless of whether the
device is operation in PWM or PSAVE mode. All switching
will stop and the output capacitors will discharge into the
load. When the output voltage falls to the new CTL setting,
previous switching operation will resume.
Voltage Selection
If an output voltage other than one of the 15 programmable settings is needed, external resistors can be added to
adjust the output voltage setting. The resistor values can
be determined using the following equation.
VOUT
ª R RFB2 º
VSET u « FB1
» ILEAK u RFB1
¬ RFB2
¼
VOUT is the desired output voltage, VSET is the voltage setting
from the CTL pins, RFB1 is the resistor between the output
capacitor and the OUT pin, RFB2 is the resistor between the
OUT pin and ground, and ILEAK is the leakage current into
the OUT pin during normal operation. The ILEAK input
current is typically 1µA, so the last term of the equation
can be neglected if the current through RFB2 is much larger
than 1µA. Selecting a resistor value of 10kΩ or lower will
simplify the design. If ILEAK is neglected and RFB2 is fixed,
RFB1 can be determined using the equation
RFB1
RFB2 u
VOUT VSET
VSET
Inserting resistance in the feedback loop will adversely
affect the system’s transient performance if feed-forward
capacitance is not included in the circuit.
Figure 1 illustrates how the resistor divider and feedforward capacitor can be added to the SC195B circuit.
V IN
IN
SC195B
LX
LX
C IN
OUT
E n a b le
CTL1
C OUT
R FB1
CTL3
CTL2
V OUT
C FF
R FB2
GND
CTL0
Figure 1 — Application Circuit with External Resistors
The value of feed-forward capacitance needed can be
determined using the equation
CFF
4 u 10 6 u
VSET VOUT 0.5 RFB1 VOUT VSET VSET 0.5 2
VOUT is the selected voltage using the CTL pins and VSET is
the final desired voltage. To simplify the design, it is recommended to program the output setting to 1.0V, use
resistor values smaller than 10kΩ, and include a feedforward capacitance calculated with the equation above.
If VOUT is set to 1.0V, the previous equation reduces to
CFF
8 u 10 6 u
VOUT 0.52
RFB1 VOUT 1
Example:
An output voltage of 1.3V is desired, but this is not a programmable option. What external component values for
Figure 1 are needed?
Solution: To keep the circuit simple, set RFB2 to 10kΩ so
current into the OUT pin can be neglected and set the
CTL3-0 pins to 0010 (1.0V setting). The necessary component values for this situation are
VOUT VSET
VSET
RFB1
RFB 2 u
CFF
8 u 10 6 u
3k:
VOUT 0.52
RFB1 VOUT 1
5.69nF
12
SC195B
Applications Information (continued)
PWM Operation
Normal PWM operation occurs when the output load
current exceeds the PSAVE threshold. In this mode, the
PMOS high side switch is activated with the duty cycle
required to produce the output voltage programmed by
the CTL pins. An internal synchronous NMOS rectifier
eliminates the need for an external Schottky diode on the
LX pin. The duty cycle (percentage of time PMOS is active)
increases as VIN decreases to maintain output voltage regulation. As V IN approaches the programmed output
voltage, the duty cycle approaches 100% (PMOS always
on) and the device enters a pass-through mode until the
input voltage increases or the load decreases enough to
allow PWM switching to resume.
Power Save Mode Operation
When the load current decreases below the PSAVE threshold, PWM switching stops and the device automatically
enters PSAVE mode. This threshold varies depending on
the input voltage and output voltage setting, optimizing
efficiency for all possible load currents in PWM or PSAVE
mode. While in PSAVE mode, output voltage regulation is
controlled by a series of switching bursts. During a burst,
the inductor current is limited to a peak value which controls the on-time of the PMOS switch. After reaching this
peak, the PMOS switch is disabled and the NMOS switch is
enabled, and the inductor current then decreases to near
0mA. Switching bursts continue until the output voltage
climbs to the VOUT +2.5% threshold. Switching is then
stopped to eliminate switching losses and enhance overall
efficiency. Switching resumes when the output voltage
reaches the lower threshold of VOUT and continues until
the upper +2.5% threshold again is reached. Note that the
output voltage is regulated hysteretically while in PSAVE
mode between VOUT and VOUT + 2.5%. The period and duty
cycle while in PSAVE mode are determined by VIN and VOUT
until PWM mode resumes. This can result in the switching
frequency being much lower than the PWM mode
frequency.
If the output load current increases enough to cause VOUT
to decrease below the PSAVE exit threshold (VOUT - 4%),
the device automatically exits PSAVE and operates in continuous PWM mode. Figure 2 illustrates the transitions
from PWM mode to PSAVE mode and back to PWM
mode.
Load
(IOUT)
V O U T +2 .5%
OFF
VOUT
V O U T - 4%
BURST
VLX
P W M M ode at
M edium /H igh
Load
PSAVE
E X IT
P S A V E M ode at
Light Load
T im e
P W M M ode at
M edium /H igh
Load
Figure 2 — Transitions Between PWM and PSAVE Modes
Protection Features
The SC195B provides these protection features:
•
•
•
•
•
Soft-Start Operation
Over-Voltage Protection
Current Limit
Thermal Shutdown
Under-Voltage Lockout
Soft-Start
The soft-start sequence is activated by a transition from
an all zeros CTL code to a non-zero CTL code, which
enables the device. Switching begins after an internal
20μs start-up period. During switching, the PMOS current
limit steps through four levels of 25%, 40%, 60%, and
100% of the Current Limit Threshold. Each current level is
maintained for 256 clock cycles (73μs).
During each level, switching is not based on the internal
3.5MHz clock. Instead, the PMOS transistor is on until the
current ramps up to the corresponding level. The PMOS
then turns off and the low-side NMOS is on until the
current returns to zero. The PMOS transistor then turns on
and the pattern repeats. With this method, the inductor
current is a series a triangular current pulses, at a frequency lower than the internal 3.5MHz clock, each pulse
going from zero up to the corresponding level. Note that
this operation is similar to the Power Save Mode
Operation.
13
SC195B
Applications Information (continued)
The full start-up period is 260μs, including the 20μs
needed to initialize the internal circuitry. The output
voltage may reach the regulation point before the full
260μs period has passed. If the internal feedback signal
derived from VOUT reaches 86% of the target during the
soft-start sequence, the device will then switch to forced
PWM operation until the sequence is completed. The
switch-over point may correspond to a voltage lower than
86% as seen at VOUT due to internal impedance connected
between the VOUT pin and the internal feedback signal.
Note the VOUT ripple in PSAVE mode can be larger than the
ripple in PWM mode.
Note that the limited current available during Soft-Start
will limit the maximum supportable capacitance and load.
The inductor current must charge the output capacitor as
well as provide any start-up load current. When the regulator reaches the end of the 4th current level (100%), the
output capacitor must be charged sufficiently to prevent
the regulator from going into Current Limit protection. If
the Current Limit is reached and extends for 32 clock
cycles, the regulator will enter Fold-back protection.
Figure 3 shows a picture of this start-up behavior.
Inductor Current
32 cycles OCP when Vout low
100%
Start of
switching
60%
40%
Fold-back
current
25%
256 cycles
Figure 3 — Soft-start Cycle
For a selected Vout and load current, the maximum output
capacitance can be determined from the following equation, with Load in amperes, VOUT in volts and COUT in μF.
&287
§ ·
˜¨
˜ /RDG¸ 9287 © 9287
¹
Over-Voltage Protection
Over-voltage protection disables the PWM drive when
VOUT exceeds the regulation voltage by 15%. When the
output voltage falls below the 15% threshold the device
resumes previous switching operation. If the device was
operating in PSAVE mode then switching will be disabled
until the voltage falls to lower hysteresis level used in
PSAVE operation. If the device was operating in PWM
mode, switching will resume to actively bring the output
back to regulation.
Current Limit
The SC195B switching stage is protected by a current limit
function. If the output load exceeds the PMOS current
limit for 32 consecutive switching cycles, the device enters
fold-back current limit mode and the output current is
limited to approximately 215mA. Note that the fold-back
current is moderately affected by the actual DC output
voltage. During fold-back conditions, the output voltage
will be the product of IFB-LIM and the load resistance. The
load must fall below IFB-LIM for the device to exit fold-back
current limit mode. This function makes the device
capable of sustaining an indefinite short circuit on its
output under fault conditions.
Thermal Shutdown
The SC195B has a thermal shutdown feature to protect
the device if the junction temperature exceeds 160°C.
During thermal shutdown, the PMOS and NMOS switches
are both disabled, tri-stating the LX output. When the
junction temperature drops by the hysteresis value (20°C),
the device goes through the soft-start process and
resumes normal operation.
Under-Voltage Lockout
Under-Voltage Lockout (UVLO) activates when the supply
voltage drops below the UVLO threshold. This prevents
the device from entering an ambiguous state in which
regulation cannot be maintained. Hysteresis of approximately 200mV is included to prevent chattering near the
threshold.
Inductor Selection
The SC195B is designed to operate with a 1µH inductor
between the LX pin and the OUT pin. Other values may
lead to instability, malfunction, or out-of-specification
14
SC195B
Applications Information (continued)
performance. The specified current levels for PSAVE entry,
PSAVE exit, and current limit are dependent on the inductor value.
The SC195B converter has internal loop compensation.
The compensation is designed to work with a specific
single-pole output filter corner frequency defined by the
equation
I&
S / u &287
where L = 1μH and COUT = 10μF.
When selecting output filter components, the LC product
should not vary over a wide range. Selection of smaller
inductor and capacitor values will move the corner frequency, potentially impacting system stability.
It is also important to consider the change in inductance
with DC bias current when choosing an inductor. The
inductor saturation current is specified as the current at
which the inductance drops a specific percentage from
the nominal value (approximately 30%). Except for shortcircuit or other fault conditions, the peak current must
always be less than the saturation current specified by the
manufacturer. The peak current is the maximum load
current plus one half of the inductor ripple current at the
maximum input voltage. Load and/or line transients can
cause the peak current to exceed this level for short durations. Maintaining the peak current below the inductor
saturation specification keeps the inductor ripple current
and the output voltage ripple at acceptable levels.
Manufacturers often provide graphs of actual inductance
and saturation characteristics versus applied inductor
current. The saturation characteristics of the inductor can
vary significantly with core temperature. Core and
ambient temperatures should be considered when examining the core saturation characteristics.
When selecting the inductor, the DC resistance (DCR) must
also be examined. Efficiency can be optimized by lowering the inductor’s DCR as much as possible. Low DCR in
an inductor requires either more surface area for the
increased wire diameter or fewer turns to reduce the
length of the copper winding. Fewer turns requires an
inductor core with a larger cross-sectional area in order to
maintain the same saturation characteristics. The inductor
size must always be considered when examining the
inductor DCR to determine the best compromise between
DCR and component area on a PCB. Note that the ripple
component of the inductor is a small percentage of the
DC load. AC losses in the inductor core and winding do
not contribute significantly to the total losses.
Magnetic fields associated with the output inductor can
interfere with nearby circuitry. This can be minimized by
the use of low-noise shielded inductors which use the
minimum gap possible to limit the distance that magnetic
fields can radiate from the inductor. Shielded inductors,
however, typically have a higher DCR and are, therefore,
less efficient than a similar sized non-shielded inductor.
Final inductor selection depends on various design considerations such as efficiency, EMI, size, and cost. Table 2
lists the manufacturers of recommended inductor options.
The inductors with larger packages tend to provide better
overall efficiency, while the smaller package inductors
provide decent efficiency with reduced footprint or height.
The saturation current ratings and DC characteristics are
also shown.
Table 2 — Recommended Inductors
Manufacturer
Part Number
L
(μH)
DCR
(Ω)
Saturation
Current
(mA)
L at
400mA
(μH)
Dimensions
LxWxH
(mm)
Murata
LQM21PN1R0MC0
1.0±20%
0.19
800
0.75
2.0x1.25x0.55
Murata
LQM2HPN1R0MJ0
1.0±20%
0.09
1500
0.95
2.5x2.0x1.1
Murata
LQM31PN1R0M00
1.0±20%
0.12
1200
0.95
3.2x1.6x0.85
Taiyo Yuden
CKP25201R0M-T
1.0±20%
0.08
800
0.88
2.5x2.0x1.0
Toko
MDT2012-CR1R0N
1.0±30%
0.08
1350
1.00
2.0x1.25x1.0
FDK
MIPSZ2012D1R0
1.0±30%
0.09
1100
1.00
2.0x1.25x1.0
FDK
MIPSU2520D1R0
1.0±30%
0.08
1300
0.78
2.5x2.0x0.5
Taiyo Yuden
BRC1608T1R0M
1.0±20%
0.18
850
0.90
1.6x0.8x0.8
15
SC195B
Applications Information (continued)
COUT Selection
The internal voltage loop compensation in the SC195B
limits the minimum output capacitor value to 10μF. This
is due to its influence on the loop crossover frequency,
phase margin, and gain margin. Increasing the output
capacitor above this minimum value will reduce the crossover frequency and provide greater phase margin. A
capacitor between 10μF and 22μF will usually be adequate
in stabilizing the output during large load transitions.
Note that in some cases the maximum output capacitance
may be limited due to load current that is applied during
the Soft-Start sequence, as described in the Soft-Start
section.
Capacitors with X7R or X5R ceramic dielectric are recommended for their low ESR and superior temperature and
voltage characteristics. Y5V capacitors should not be used
as their temperature coefficients make them unsuitable
for this application.
In addition to ensuring stability, the output capacitor
serves other important functions. This capacitor determines the output voltage ripple — as capacitance
increases, ripple voltage decreases. It also supplies current
during a large load step for a few switching cycles until
the control loop responds (typically 3 switching cycles).
Once the loop responds, regulation is restored and the
desired output is reached. During the period prior to PWM
operation resuming, the relationship between output
voltage and output capacitance can be approximated
using the equation
COUT
3 u 'ILOAD
VDROOP u f
This equation can be used to approximate the minimum
output capacitance needed to ensure voltage does not
droop below an acceptable level. For example, a load step
from 200mA to 500mA requiring droop less than 40mV
would require the minimum output capacitance to be
&287
u u u ȝ) In this example, using a standard 10µF capacitor would be
adequate to keep voltage droop below the desired limit.
Note that if the voltage droop limit were decreased from
40mV to 20mV, the output capacitance would need to be
increased to at least 12.8µF (twice as much capacitance
for half the droop). Capacitance will decrease from the
nominal value when a ceramic capacitor is biased with a
DC voltage, so it is important to select a capacitor whose
value exceeds the necessary capacitance value when
biased at the programmed output voltage. Check the
manufacturer’s capacitance vs. DC voltage graphs when
selecting an output capacitor to ensure the capacitance
will be adequate. Table 3 lists the manufacturers of recommended output capacitor options.
Table 3 — Recommended Output Capacitors
Value
(μF)
Type
Rated
Voltage
(VDC)
Dimensions
LxWxH (mm)
Case Size
Murata
GRM188R60J106ME47D
10±20%
X5R
6.3
1.6x0.8x0.8
0603
Murata
GRM21BR60J106K
10±10%
X5R
6.3
2.0x1.25x1.25
0805
Taiyo Yuden
JMK107BJ106MA-T
10±20%
X5R
6.3
1.6x0.8x0.8
0603
TDK
C1608X5R0J106MT
10±20%
X5R
6.3
1.6x0.8x0.8
0603
Manufacturer
Part Number
CIN Selection
The SC195B input source current will appear as a series of
current pulses approximately equal to the load current. To
prevent large input voltage ripple, a low ESR ceramic
capacitor is required. A minimum value of 4.7μF should
be used. It is important to consider the DC voltage coefficient characteristics when determining the actual required
value. For example, a 10μF, 6.3V, X5R ceramic capacitor
with 5V DC applied may exhibit a capacitance as low as
4.5μF. The value of required input capacitance is estimated
by determining the acceptable input ripple voltage and
calculating the minimum value required for CIN using the
equation
CIN
VOUT § VOUT ·
¨1 ¸
VIN ¨©
VIN ¸¹
§ 'V
·
¨¨
ESR ¸¸f
© IOUT
¹
For a given VOUT the input voltage ripple is maximum when
the VIN is twice VOUT, (at 50% duty cycle).
16
SC195B
Applications Information (continued)
The input capacitor provides a low impedance loop for
the edges of pulsed current drawn by the PMOS switch.
Low ESR/ESL X5R ceramic capacitors are recommended
for this function. To minimize stray inductance, the capacitor should be placed as closely as possible to the IN and
GND pins.
PCB Layout Considerations
Table 4 lists the recommended input capacitor options
from different manufacturers.
. Place CIN as close as possible to the IN and GND pins.
This capacitor provides a low impedance loop for the
pulsed currents present at the buck converter’s input.
Use short wide traces to minimize trace impedance.
This will also minimize EMI and input voltage ripple
by localizing the high frequency current pulses.
2. Place COUT close to the GND and OUT pins.
3. The LX trace can go underneath the input capacitor
to one terminal of the inductor. The other terminal of
the inductor connects to the VOUT copper pad.
4. Use a ground plane to improve thermal performance.
5. Use a heavy copper trace to directly connect from
the output capacitor to the load point to reduce the
copper voltage drop. The regulation sense point for
the SC195B is at the OUT pin.
6. Traces for the CTL pins should avoid these high noise
traces: the LX trace between the inductor and the LX
pin, the VIN trace between CIN and the IN pin, and the
GND trace between and the GND pin.
Table 4 — Recommended Input Capacitors
Manufacturer
Part Number
Value
(μF)
Type
Rated
Voltage
(VDC)
Dimensions
LxWxH (mm)
Case Size
Murata
GRM188R60J475K
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
Murata
GRM188R60J106K
10±10%
X5R
6.3
1.6x0.8x0.8
0603
Taiyo Yuden
JMK107BJ475KA
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
TDK
C1608X5R0J475KT
4.7±10%
X5R
6.3
1.6x0.8x0.8
0603
Poor PCB layout can result in poor output voltage regulation and other noise problems.
The following guidelines are recommended for designing
a PCB layout and component placement, see Figure 4:
Figure 4 — PCB Layout and Component Placement
A
1
2
3
C T L2
C T L0
C T L1
C T L3
IN
B
LX
GND
OUT
C
V IN
S C 1 9 5B
V OUT
C IN
C OUT
in d u cto r
LX
17
SC195B
Outline Drawing — WLCSP8-0.80X0.80
Land Pattern — WLCSP8
18
SC195B
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19