SC286 - Semtech

SC286
Dual Channel 4A Synchronous
Step-Down Regulator
POWER MANAGEMENT
Features
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Description
Input Voltage Range — 2.9 to 5.5V
Output Voltage Range — 0.8V to 3.3V
Output Current — up to 4A for each channel
Ultra-Small Footprint — <1mm Height Solution
Switching Frequency — 1.6MHz
Automatic Power Save Mode
Efficiency Up to 95%
Low Output Noise Across Load Range
Excellent Transient Response
Start Up into Pre-Bias Output
Duty-Cycle Low Dropout Operation — 100%
Shutdown Current — <1µA
Externally Programmable Soft Start Time
Power Good indicator
Input Under-Voltage Lockout
Output Over-Voltage, Current Limit Protection
Over-Temperature Protection
Thermally Enhanced 4 x 4 x 0.6 (mm)
MLPQ-UT28 package
Lead-free, Halogen free, and RoHS/WEEE compliant
Applications
Routers and Network Cards
LCD TV
 Office Automation
 Printers


The SC286 is a dual channel 4A synchronous step-down
regulator designed to operate with an input voltage
range of 2.9V to 5.5V. Each channel offers fifteen predetermined output voltages via separate control pins
programmable from 0.8 to 3.3 Volts. The control pins
allow for on-the-fly voltage changes, enabling system
designers to implement dynamic power savings. The
device is also capable of adjusting output voltage via an
external resistor divider.
The SC286 is optimized for maximum efficiency over a
wide range of load currents. During full load operation,
the device operates in PWM mode with fixed 1.6MHz
oscillator frequency, allowing the use of small surface
mount external components. As the load decreases, the
regulator will transition into Power Save mode maintaining high efficiency.
Connecting the control pins to logic low forces the device
into shutdown mode reducing the supply current to less
than 1μA. Connecting any of the control pins to logic high
enables the converter and sets the output voltage according to Table 1. Other features include under-voltage
lockout, programmable soft-start to limit in-rush current,
power good indicator, over-temperature protection, and
output short circuit protection.
The SC286 is available in a thermally-enhanced, 4 x 4 x 0.6
(mm) MLPQ-UT28 package and has a rated temperature
range of -40 to +85°C.
Typical Application Circuit
VINA
CINA
22µF
RPGOODA
100kΩ
RAVINA 1Ω
CAVINA 0.1µF
LA 1.0µH
PVINA
AVINA
SC286
AGNDA
PGOODA
VINB
CINB
22µF
RPGOODB
100kΩ
RAVINB 1Ω
CAVINB 0.1µF
PVINB
AVINB
AGNDB
CTL0A
CTL1A
CTL2A
CTL3A
Revision 2.0
PGOODB
CTL0A
CTL1A
CTL2A
CTL3A
LXA
VOUTA
LB 1.0µH
LXB
VOUTB
SSA
PGNDA
SSB
PGNDB
CTL0B
CTL1B
CTL2B
CTL3B
© 2011 Semtech Corporation
CSSA
1nF
COUTA
47µF
COUTB
47µF
VOUTA
VOUTB
CSSB
1nF
CTL0B
CTL1B
CTL2B
CTL3B
SC286
LXA
PGNDA
VOUTB
SSB
PGOODB
CTL3B
Ordering Information
LXA
Pin Configuration
28
28
26
25
24
23
22
2
20
CTL1B
AGNDA
3
19
CTL0B
AVINA
4
18
AVINB
CTL0A
5
17
AGNDB
CTL1A
6
16
PVINB
CTL2A
7
15
PVINB
10
11
12
13
Package
SC286ULTRT(1)(2)
4 x 4 x 0.6 (mm) MLPQ-UT28
SC286EVB
Evaluation Board
Notes:
(1) Available in tape and reel only. A reel contains 3,000 devices.
(2) Device is lead-free, Halogen free, and RoHS/WEEE compliant.
14
LXB
9
LXB
8
PGNDB
PVINA
VOUTA
CTL2B
SSA
21
PGOODA
1
CTL3A
PVINA
Device
4 x 4 x 0.6 (mm) MLPQ-UT28
θJA = 32.5°C/W; θJC = 7°C/W
Marking Information
SC286
yyww
XXXXX
XXXXX
yyww = Date code
XXXXX = Semtech Lot number
XXXXX = Semtech Lot number
Table 1 – Output Voltage Settings for Each Channel
CTL3A/B CTL2A/B CTL1A/V CTL0A/B
Output Voltage
0
0
0
0
Shutdown
0
0
0
1
0.8
0
0
1
0
1.00
0
0
1
1
1.025
0
1
0
0
1.05
0
1
0
1
1.20
0
1
1
0
1.25
0
1
1
1
1.30
1
0
0
0
1.50
1
0
0
1
1.80
1
0
1
0
2.20
1
0
1
1
2.50
1
1
0
0
2.60
1
1
0
1
2.80
1
1
1
0
3.00
1
1
1
1
3.30
SC286
Absolute Maximum Ratings
Recommended Operating Conditions
PVINA/B and AVINA/B Supply Voltages (V) . . . -0.3 to +6.0
PVINA/B and AVINA/B Supply (V) . . . . . . . . . . 2.9 to +5.5
LXA, LXB (V) (1) . . . . . . . . . . . . . . . . -0.3 to PVIN +0.3V, 6V Max
Maximum Output Current, Each Channel (A). . . . . . . . . 4.0
VOUTA, VOUTB (V). . . . . . . . . . . . . . . . . . . -0.3 to AVIN + 0.3
Input Capacitor, Each Channel (µF). . . . . . . . . . . . . . . . . . 22
CTLxA, CTLxB pins (V). . . . . . . . . . . . . . . . . -0.3 to AVIN + 0.3
Output Capacitor, Each Channel (µF) . . . . . . 47 or 2 x 22
VOUTA, VOUTB Short Circuit Duration . . . . . . Continuous
Output Inductor, Each Channel (µH) . . . . . . . . . . . . . . . . 1.0
ESD Protection Level(2) (kV) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Thermal Information
Thermal Resistance, Junction to Ambient(3) (°C/W) . . 32.5
Thermal Resistance, Junction to Case (°C/W) . . . . . . . . . . . 7
Maximum Junction Temperature (°C). . . . . . . . . . . . . . . +150
Storage Temperature Range (°C) . . . . . . . . . . . . -65 to +150
Peak IR Reflow Temperature (10s to 30s) (°C) . . . . . . . +260
Exceeding the absolute maximum ratings may result in permanent damage to the device and/or device malfunction. Operation outside of the
parameters specified in the Electrical Characteristics section is not recommended.
Notes:
(1) Due to parasitic board inductance, the transient LX pin voltage at the point of measurement may appear larger than that which exists on silicon. The device is
designed to tolerate the short duration transient voltages that will appear on the LX pin due to the deadtime diode conduction, for inductor currents up to the
current limit setting of the device.
(2) Tested according to JEDEC standard JESD22-A114-B.
(3) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards.
Electrical Characteristics
Unless specified: PVIN = AVIN = 5.0V, VOUT = 1.50V, CIN = 22µF, COUT = 2 x 22µF; L = 1.0µH; -40°C≤ TJ ≤ +125 °C; Per Channel Unless otherwise noted; Typical values are
TA = +25 °C.
Parameter
Symbol
Under-Voltage Lockout
Conditions
Min
Typ
Max
Units
Rising AVINA/B; PVINA/B=AVINA/B
2.70
2.80
2.90
V
UVLO
Hysteresis
Output Voltage Tolerance(1)
300
ΔVOUT
PVINA/B= AVINA/B= 2.9 to 5.5V; IOUT=0A
-1.25
ILIMIT
Peak LX current
5.0
IQ
IOUTA/B = 0A
100
ISHDN
CTL3-0A/B = AGNDA/B
1
High Side Switch Resistance(2)
RDSON_P
ILXA./B= 100mA, TJ= 25 °C
50
Low Side Switch Resistance(2)
RDSON_N
ILXA/B= -100mA, TJ= 25 °C
35
PVINA/B = AVINA/B= 5.5V; LXA/B= 0V; CTL3-0A/B =
AGNDA/B
1
Current Limit
Supply Current
Shutdown Current
LX Leakage Current
(2)
ILK(LX)
PVINA/B = AVINA/B = 5.5V; LXA/B = 5.0V; CTL3-0A/B =
AGNDA/B
6.0
mV
+1.25
%
7.0
A
µA
10
µA
mΩ
10
µA
-20
-1
SC286
Electrical Characteristics (continued)
Parameter
Symbol
Conditions
Load Regulation
ΔVLOAD-REG
PVINA/B = AVINA/B = 5.0V, IOUT=800mA to 4A
Oscillator Frequency
fOSC
Soft-Start Charging Current(2)
ISS
Max
±0.3
1.275
1.600
Units
%
1.925
MHz
µA
1
A
10
Ω
VOUTA/B rising
90
%
Asserted
2
ms
PGOODA/B= Low
20
µs
tEN_DLY
From CTLX Input High to SS starts rising
50
µs
ICTLx
CTLX =AVINA/B or AGNDA/B
ICL_HOLD
Impedance of PGOOD Low
RPGOOD_LO
PGOOD Threshold
VPG_TH
PGOOD Delay
VPG_DLY
CTLX Input Current(2)
Typ
+5
Foldback Holding Current
CTLX Delay
Min
CTLX Input High Threshold
VCTLx_HI
CTLX Input Low Threshold
VCTLx_LO
Average LX Current
-2.0
2.0
1.2
V
115
0.4
V
120
%
VOUTA/B Over Voltage Protection
VOVP
Thermal Shutdown Temperature
TSD
160
°C
TSD_HYS
10
°C
Thermal Shutdown Hysteresis
110
µA
Notes:
(1) The “Output Voltage Tolerance” includes output voltage accuracy, voltage drift over temperature and the line regulation.
(2) A negative current means the current flows into the pin and a positive current means the current flows out from the pin.
SC286
Pin Descriptions
Pin #
Pin Name
Pin Function
1, 2
PVINA
Input supply voltage for the converter power stage
3
AGNDA
Ground connection for the internal circuitry — AGNDA needs to be connected to PGNDA directly.
4
AVINA
Power supply for the internal circuitry — AVINA is required to be connected to PVINA through an R-C filter of
1Ω and 100nF.
5, 6, 7, 8
CTLXA
Control bit — see Table 1 for decoding. These pins have 500kΩ internal pull-down resistors which are switched
into the circuit whenever CTLXA is low or when the part is in under-voltage lockout.
9
PGOODA
Power good indicator — when the output voltage reaches the PGOODA threshold, this pin will be open-drain
(after the PGOODA delay), otherwise, it is pulled low internally.
10
SSA
Soft Start — connect a soft-start capacitor to program the soft start time. There is a 5µA charging current
flowing out of the pin.
11
VOUTA
Output voltage sense pin
12
PGNDB
Ground connection for converter power stage
13, 14
LXB
15, 16
PVINB
Input supply voltage for the converter power stage
17
AGNDB
Ground connection for the internal circuitry — AGNDB needs to be connected to PGNDB directly.
18
AVINB
Power supply for the internal circuitry — AVINB is required to be connected to PVINB through an R-C filter of
1Ω and 100nF.
19, 20, 21, 22
CTLXB
Control bit — see Table 1 for decoding. These pins have 500kΩ internal pull-down resistors which are switched
into the circuit whenever CTLXB is low or when the part is in under-voltage lockout.
23
PGOODB
Power good indicator — when the output voltage reaches the PGOODB threshold, this pin will be open-drain
(after the PGOODB delay), otherwise, it is pulled low internally.
24
SSB
Soft Start — connect a soft-start capacitor to program the soft start time. There is a 5µA charging current
flowing out of the pin.
25
VOUTB
Output voltage sense pin
26
PGNDA
Ground connection for converter power stage
27, 28
LXA
T
Thermal Pad
Switching node — connect an inductor between this pin and the output capacitor.
Switching node — connect an inductor between this pin and the output capacitor.
Thermal pad for heat sinking purposes — recommend to connect to PGND. It is not connected internally.
SC286
Block Diagram
Current Amp
AVINA
A
PVINA
B
LXA
26
PGNDA
9
PGOODA
C
PVINB
D
LXB
12
PGNDB
23
PGOODB
4
Plimit Amp
Oscillator and
Slope Generator
VOUTA
Control
Logic
11
PWM
CTL0A
CTL1A
5
6
CTL2A
7
CTL3A
8
SSA
10
AGNDA
3
Error Amp
Voltage
Select
c Comp
500mV
Ref
PGOOD Detector
Delay
Current Amp
AVINB
18
Plimit Amp
Oscillator and
Slope Generator
VOUTB
25
CTL0B
19
Control
Logic
PWM
CTL1B
20
CTL2B
21
CTL3B
22
SSB
24
AGNDB
17
Error Amp
Voltage
Select
500mV
Ref
NOTES:
A = Pins 1,2
B = Pins 27, 28
c Comp
PGOOD Detector
Delay
C = Pins 15, 16
D = Pins 13, 14
SC286
Typical Characteristics
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0), each device
Total Loss
Efficiency
TA = 25 °C
100
TA = 25 °C
2000
VIN = 5V; VOUT = 3.3V
95
1600
VIN = 5V; VOUT = 3.3V
85
VIN = 3V; VOUT = 1.5V
80
VIN = 3.3V; VOUT = 1.5V
1200
VIN = 5V; VOUT = 1.5V
Loss (mW)
Efficiency (%)
90
75
800
VIN = 5V; VOUT = 1.5V
70
400
65
60
0
0
0.1
Output current (A)
1.0
10.0
0
ILX = ±100mA, TA = 25°C
20
2.5
3.5
3.0
4.0
ILX = ±100mA, TA = 25°C
15
25
10
20
P-Channel
Variation (%)
Variation (%)
2.0
RDS(ON) Variation vs. Temperature
30
15
10
5
0
P-Channel
-5
5
N-Channel
-10
0
N-Channel
-15
-5
-10
1.5
1.0
Output current (A)
RDS(ON) Variation vs. Input Voltage
35
0.5
3.5
3.0
2.5
4.0
4.5
Input Voltage (V)
5.5
5.0
-20
-40
-15
35
10
Ambient Temperature (°C)
60
85
Load Regulation
2.0
TA = 25 °C
Regulation (%)
1.5
VIN = 5V; VOUT = 1.5V
VIN = 3.3V; VOUT = 1.5V
1.0
VIN = 5V; VOUT = 3.3V
0.5
0
-0.5
0
0.5
1
1.5
2
2.5
Output current (A)
3
3.5
4
4.5
SC286
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0), each device
Output Voltage Ripple (VOUT=1.5V)
Output Voltage Ripple (VOUT=1.5V)
VIN = 5V, = IOUT = 0
VIN = 3.3V, = IOUT = 0
VOUT (50mV/div)
VOUT (50mV/div)
VIN (2V/div)
VIN (2V/div)
LX (2V/div)
LX (2V/div)
ISW (1A/div)
ISW (1A/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
Output Voltage Ripple (VOUT=1.5V) @ Full Load
Output Voltage Ripple (VOUT=1.5V) @ Full Load
VIN = 3.3V, = IOUT = 4A
VIN = 5V, = IOUT = 4A
VOUT (10mV/div)
VOUT (10mV/div)
IL (1A/div)
IL (1A/div)
VIN (2V/div)
VIN (2V/div)
LX (1V/div)
LX (1V/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
SC286
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0), each device
Output Voltage Ripple (VOUT = 3.3V) @ No Load
Output Voltage Ripple (VOUT = 3.3V) @ Full Load
VIN = 5V, = IOUT = 4A; VOUT = 3.3V
VIN = 5V, = IOUT = 0; VOUT = 3.3V
VOUT (20mV/div)
VOUT (50mV/div)
VIN (2V/div)
VIN (2V/div)
LX (2V/div)
ISW (1A/div)
LX (2V/div)
ISW (1A/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
Start Up (CTLX) — Full Load
Start Up (CTLX) — No Load
VIN = 5V, = IOUT = 0; VOUT = 1.5V
VIN = 5V, = IOUT = 4A; VOUT = 1.5V
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
VOUT (1V/div)
VOUT (1V/div)
IOUT (5V/div)
IOUT (5V/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
SC286
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0), each device
Start Up (CTLX) — Full Load
Start Up (CTLX) — No Load
VIN = 5V, = IOUT = 0; VOUT = 3.3V
VIN = 5V, = IOUT = 0; VOUT = 3.3V
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
VOUT (2V/div)
VOUT (2V/div)
IOUT (5A/div)
IOUT (5A/div)
Time (500µ������
s�����
/div)
Start Up into Pre-Biased Output (VOUT=1.5V)
Time (500µ������
s�����
/div)
Start Up into Pre-Biased Output (VOUT=3.3V)
VCTLx (5V/div)
VCTLx (5V/div)
PGOOD (5V/div)
PGOOD (5V/div)
VOUT (1V/div)
VOUT (2V/div)
IOUT (5V/div)
IOUT (5V/div)
Time (500n������
s�����
/div)
Time (500n������
s�����
/div)
Start Up into Output Short Circuit
VIN = 5V
LX (5V/div)
VOUT (500mV/div)
VSS (1V/div)
ILX (2A/div)
Time (500n������
s�����
/div)
10
SC286
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0), each device
Recovery from Short Circuit
Output Short Circuit
VIN = 5V; VOUT = 1.5V
VIN = 5V; VOUT = 1.5V
VLX (5V/div)
VLX (5V/div)
PGOOD (5V/div)
VOUT (1V/div)
PGOOD (5V/div)
VOUT (1V/div)
IOUT (5V/div)
IOUT (2V/div)
Time (20µ������
s�����
/div)
Time (20µ������
s�����
/div)
Output Short Circuit
Recovery from Short Circuit
VIN = 5V; VOUT = 3.3V
VIN = 5V; VOUT = 3.3V
VLX (5V/div)
VLX (5V/div)
VOUT (2V/div)
PGOOD (5V/div)
VOUT (2V/div)
IOUT (2V/div)
IOUT (5V/div)
Time (20µ������
s�����
/div)
Time (20µ������
s�����
/div)
Transient Response (VOUT=1.5V, ISTEP=2A)
Transient Response (VOUT=3.3V, ISTEP=2A)
VIN = 5V; IOUT = 1A to 3A to 1A
VIN = 5V; IOUT = 1A to 3A to 1A
VOUT (100mV/div)
VOUT (100mV/div)
IOUT (1A/div)
IOUT (1A/div)
Time (20µ������
s�����
/div)
Time (20µ������
s�����
/div)
11
SC286
Typical Characteristics (continued)
Circuit Conditions: CIN = 22µF/6.3V, COUT = 2 x 22µF/6.3V, CSS = 10nF. Unless otherwise noted, L = 1.0µH (TOKO: FDV0530S-1R0), each device
Transient Response (VOUT=1.5V, ISTEP=3A)
Transient Response (VOUT=3.3V, ISTEP=3A)
VOUT = 5V; IOUT = 0A to 3A to 0A
VIN = 5V; IOUT = 0A to 3A to 0A
VID Transition — Full Load
VID Transition — No Load
VIN = 5V; VOUT = 1.5V to 1.8V to 1.5V
VIN = 5V; VOUT = 1.5V to 1.8V to 1.5V
VOUT (200mV/div)
VOUT (200mV/div)
IOUT (2A/div)
IOUT (2A/div)
Time (400m������
s�����
/div)
Time (100m������
s�����
/div)
12
SC286
Applications Information
Detailed Description
The SC286 is a two channel synchronous step-down PWM
(Pulse Width Modulated), DC-DC converter utilizing a
1.6MHz fixed-frequency voltage mode architecture. Both
channels are designed to operate in fixed-frequency PWM
mode and will enter PSAVE (power save) mode at light
loads to maximize efficiency. The switching frequency is
chosen to minimize the size of the external inductor and
capacitors while maintaining high efficiency. Both channels run independently
Operation
During normal operation, the PMOS MOSFET is activated
on each rising edge of the internal oscillator. The period is
set by the onboard oscillator when in PWM mode. The
device has an internal synchronous NMOS rectifier and
does not require a Schottky diode on the LX pin. The device
operates as a buck converter in PWM mode with a fixed frequency of 1.6MHz at medium to high loads. At light loads
the part will enter PSAVE mode to maximize efficiency.
If the output load current increases enough to cause VOUT
to decrease below the PSAVE exit threshold (VOUT -4%), the
device automatically exits PSAVE and operates in continuous PWM mode. Note that the PSAVE high and low threshold levels are both set at or above V OUT to minimize
undershoot when the SC286 exits PSAVE. Figure 1 illustrates the transitions from PWM mode to PSAVE mode and
back to PWM mode.
Load
Demand
(IOUT )
VOUT +2%
VOUT
BURST
VOUT -4%
Power Save Mode Operation
When the load current decreases below the PSAVE threshold, PWM switching stops and each channel automatically
enters PSAVE mode. This threshold varies depending upon
the input voltage and output voltage setting, optimizing
efficiency for all possible load currents. While in PSAVE
mode, output voltage regulation is controlled by a series of
bursts in switching. During a burst, the inductor current is
limited to a peak value which controls the on-time of the
PMOS switch. After reaching this peak, the PMOS switch is
disabled and the inductor current is forced to near 0mA.
Switching bursts continue until the output voltage climbs
to VOUT +2% or until the PSAVE current limit is reached.
Switching is then stopped to eliminate switching losses,
enhancing overall efficiency. Switching resumes when the
output voltage reaches the lower threshold of VOUT and
continues until the upper threshold again is reached. Note
that the output voltage is regulated hysteretically while in
PSAVE mode between VOUT and VOUT + 2%. The period and
duty cycle while in PSAVE mode are solely determined by
VIN and VOUT until PWM mode resumes. This can result in the
switching frequency being much lower than the PWM
mode frequency.
OFF
VLX
PWM Mode at
Medium / High
Load
PSAVE
EXIT
PSAVE Mode at
Light Load
PWM Mode at
Medium / High
Load
Time
Figure 1 — Transitions between PWM and PSAVE Modes
Protection Features
The SC286 provides the following protection features for
each independent channel:
•
•
•
•
Current Limit
Over-Voltage Protection
Soft-Start Operation
Thermal Shutdown
Current Limit & OCP
The internal PMOS power device in the switching stage for
each channel is protected by a current limit feature. If the
inductor current is above the PMOS current limit for 16
consecutive cycles, the part enters foldback current limit
mode and the output current is limited to the current limit
holding current
(ICL_HOLD) which is approximately 1A.
13
SC286
Applications Information (continued)
Under this condition, the output voltage will be the product
of ICL_HOLD and the load resistance. When the load presented
falls below the current limit holding level, the output will
charge to the upper PSAVE voltage threshold and return to
normal operation. The SC286 is capable of sustaining an
indefinite short circuit without damage. During soft start, if
current limit has occurred before the SS voltage has reached
400mV, the part enters foldback current limit mode.
Foldback current limit mode will be disabled during softstart after the SS voltage is higher than 400mV.
VINA
CINA
22µF
The SC286 has fifteen pre-determined output voltage
values which can be individually selected for each channel
by programming the CTL input pins (see Table 1 — Output
Voltage Settings). Each CTL pin has an active 500kΩ internal
pull-down resistor. The 500kΩ resistor is switched in circuit
whenever the CTL input voltage is below the input threshold, or when the part is in under voltage lockout. It is
recommended to tie all high CTL pins together and use an
external pull-up resistor to AVIN if there is no enable signal
or if the enable input is an open drain/collector signal. The
CTL pins may be driven by a microprocessor to allow
dynamic voltage adjustment for systems that reduce the
supply voltage when entering sleep states. Avoid all zeros
being present on the CTL pins when changing programmable output voltages as this would disable the device.
SC286 is also capable of regulating a different (higher)
output voltage, which is not shown in the Table 1, via an
external resistor divider for each channel. There will be a
typical 2μA current flowing into the VOUTA/B pin. The
typical schematic for an adjustable output voltage option
from the standard 1.0V with CTLXA/B = [0010], is shown in
Figure 2. RFB1A/B and RFB2A/B are used to adjust the
desired output voltage. If the RFB2A/B current is such that
the 2μA VOUTA/B pin current can be ignored, then RFB1A/
B can be found using the next equation. RFB2A/B needs to
be low enough in value for the current through the resistor chain to be at least 20μA in order to ignore the VOUTA/B
pin current.
RAVINA 1Ω
CAVINA
0.1µF
PVINA
L
SC286
AVINA
AGNDA
VINB
CINB
22µF
RPGOODA
100kΩ
RAVINB 1Ω
CAVINB
0.1µF
VOUTA
LXA
CFFA
RFB1A
VOUTA
PGOODA
RFB2A
10kΩ
RFB1A = (VOUTA -1)
x RFB2A
for CTLAX = 0010
(1.0V)
PVINB
AVINB
COUTA
L
VOUTB
LXB
AGNDB
CFFB
RFB1B
COUTB
PGOODB
Enable A
CTL0A
VOUTB
CTL1A
RFB2B
10kΩ
RFB1B = (VOUTB -1)
x RFB2B
for CTLBX = 0010
(1.0V)
CTL2A
Over-Voltage Protection
In the event of a 15% over-voltage on each independent
output, the PWM drive is disabled with the LX pin floating.
Switching does not resume until the output voltage falls
below the nominal VOUT regulation voltage.
Programmable Output Voltage
RPGOODA
100kΩ
CTL3A
Enable B
SSA
PGNDA
CTL0B
CTL1B
CTL2B
CTL3B
SSB
PGNDB
CSS
1nF
CSS
1nF
Figure 2 — Output Voltage Programming
R FB1
VOUT VOSTD
u R FB2
VOSTD
where VOSTD is the pre-determined output voltage via the
CTL pins.
CFF is needed to maintain good transient response performance. The correct value of CFF can be found using the
following equation.
CFF [nF]
2
VOUT 0.5 VOSTD
2 .5 u
u(
)
R FB1 [k:] u VOUT VOSTD VOSTD 0.5
To simplify the design, it is recommended to program the
desired output voltage from a standard 1.0V as shown in
Figure 2 with a proper CFF calculated from Equation 2. For
programming the output voltage from other standard
voltages, RFB1, RFB2 and CFF need to be adjusted to conform
to the previous equations.
Maximum Power Dissipation
Each channel of SC286 has its own ΘJA of 32.5°C/W when
only one channel is in operation. Since both channels
are within the same package, there is about 50% of the
heat generated which will be transferred to the adjacent
channel. The equivalent total thermal impedance will be
higher when the neighboring channel is also in operation.
14
SC286
Applications Information (continued)
To guarantee an operating junction temperature of less
than 125°C, Figure 3 shows the maximum allowable total
power loss versus temperature. The curve is based upon
the junction temperature of either channel reaching a
maximum of 125°C. Each channel of SC286 can support
up to 4A load current. Figure 4 shows the maximum
allowable power loss in channel B versus power loss in
channel A for a range of temperatures.
4.5
Total Power Loss (W)
4
VIN = 5V; VOUT = 1.2V
3.5
3
2.5
25
35
45
55
65
75
Ambient Temperature (°C)
85
95
105
Figure 3 — Maximum allowable total loss versus
temperature for a maximum junction temperature of
125°C
1.8
Power Loss of Channel B (W)
1.6
TA = 25°C
1.4
TA = 55°C
TA = 70°C
1.2
1
TA = 85°C
0.8
When all CTL pins for a channel are low, the device will run
in shutdown mode, drawing less than 1μA from the input
power supply. The internal switches and band-gap voltage
will be immediately turned off.
Thermal Shutdown
The device has an independent thermal shutdown feature
for each channel to protect the SC286 if the junction temperature exceeds 160°C. During thermal shutdown, the
on-chip power devices are disabled, floating the LX
output. When the temperature drops by 10°C, it will initiate a soft start cycle to resume normal operation.
Under-Voltage Lockout
VIN = 5V; VOUT = 3.3V
VIN = 3.3V; VOUT = 1.2V
2
Shut Down
Under-Voltage Lockout (UVLO) is enabled when the input
voltage for each channel drops below the UVLO threshold.
This prevents the device from entering an ambiguous
state in which regulation cannot be maintained. Hysteresis
of approximately 300mV is included to prevent chattering
near the threshold. When the AVIN voltage rises back to
the turn-on threshold and CTLX is high, the soft-start mode
is initiated.
Power Good
The power good (PGOOD) for each channel is an opendrain output. When the output voltage for each channel
drops below 10% of the nominal voltage, the PGOOD pin
for that channel is pulled low after a 20μs delay. During
start-up, PGOOD will be asserted 1.8ms (typ.) after the
output voltage reaches 90% of the final regulation voltage.
The faults of over voltage, fold-back current limit mode
and thermal shutdown will force PGOOD low after a 20µs
delay. When recovering from a fault, PGOOD will be
asserted 2ms (typ.) after Vout reaches 90% of the final
regulation voltage.
0.6
0.4
0.2
0
0
0.2
0.4
0.6
0.8
1
1.2
Power Loss of Channel A (W)
1.4
1.6
1.8
Figure 4 — Maximum allowable power loss in channel
B versus power loss in channel A for a range of
temperatures (both channels same current)
15
SC286
Applications Information (continued)
Soft-Start
The soft-start mode is activated for each channel after
AVIN reaches it’s UVLO voltage threshold and CTLXA/B is set
high to enable the part. Recovery from a thermal shutdown event will also activate the soft start sequence. The
soft-start mode controls the slew-rate of the output
voltage during start-up thus limiting in-rush current on
the input supply. During start-up, the reference voltage
for the error amplifier is clamped by the voltage on SS pin.
The output voltage slew rate during soft-start is determined by the value of the external capacitor connected to
the SS pin and the internal 5µA charging current. The
device requires a minimum soft-start time from enable to
final regulation in the order of 200µs, including the 50µs
enable delay. As a result the soft start capacitor, Css, should
be higher than 1.5nF. During start up, the chip operates in
forced PWM mode.
In general, the inductor is chosen to set the inductor ripple
current to approximately 30% of the maximum output
current. It is recommended to use a typical inductor value
of 1μH to 2.2μH with output ceramic capacitors of 44μF or
higher capacitance. Lower inductance should be considered in applications where faster transient response is
required. More output capacitance will reduce the output
deviation for a particular load transient. When using low
inductance, the maximum peak inductor current at any
condition (normal operation and start up) can not exceed
5A which is the guaranteed minimum current limit. The
saturation current rating of the inductor needs to be at
least larger than the peak inductor current which is the
maximum output current plus half of inductor ripple
current.
100% Duty-Cycle Operation
SC286 is capable of operating at 100% duty-cycle. When
the difference between the input voltage and output
voltage is less than the minimum dropout voltage, the
PMOS switch is turned completely on, operating in 100%
duty-cycle. The minimum dropout voltage is the output
current multiplied by the on-resistance of the internal
PMOS switch and the DC-resistance of the inductor when
the PMOS switch is on continuously.
Output L-C filter Selection
SC286 has fixed internal loop-gain compensation for
each channel. It is optimized for X5R or X7R ceramic
output capacitors and an output L-C filter corner
frequency of less than 34kHz. The output L-C corner
frequency can be determined by the following
equation.
1
fC
2S
L u C OUT
16
SC286
Applications Information (continued)
PCB Layout Considerations
The layout diagram in Figure 5 shows a recommended
top-layer PCB for the SC286 and supporting components.
Figure 6 shows the bottom layer for this PCB. Fundamental
layout rules must be followed since the layout is critical for
achieving the performance specified in the Electrical
Characteristics table. Poor layout can degrade the performance of the DC-DC converter and can contribute to EMI
problems, ground bounce, and resistive voltage losses.
Poor regulation and instability can result.
The following guidelines are recommended when developing a PCB layout:
1. The input capacitor, CIN (for applicable channel) should
be placed within 1mm of the PVIN and PGND pins.
This capacitor provides a low impedance loop for the
pulsed currents present at the buck converter’s input.
Use short wide traces to connect as closely to the IC
as possible. This will minimize EMI and input voltage
ripple by localizing the high frequency current pulses.
2. Keep the LX pin traces as short as possible to minimize
pickup of high frequency switching edges to other
parts of the circuit. COUT and L (for applicable channel)
should be connected as close as possible between the
LX and PGND pins, with a direct return to the PGND
pin from COUT. The gap between the LX trace and the
other traces should be at least 0.25mm (10 mils).
3. Route the output voltage feedback/sense path away
from the inductor and LX node to minimize noise and
magnetic interference.
4. Use a ground plane referenced to the SC286 PGND
pin. Use several vias to connect to the component
side ground to further reduce noise and interference
on sensitive circuit nodes.
5. If possible, minimize the resistance from the VOUT and
PGND pins to the load (for applicable channel). This
will reduce the voltage drop on the ground plane and
improve the load regulation. And it will also improve
the overall efficiency by reducing the copper losses
on the output and ground planes.
6. The filter capacitor, CAVIN, should be placed as close
to the AVIN and AGND pins as possible. This reduces
noise coupling into the internal circuit.
Figure 5 — Recommended PCB Layout (Top Layer)
Figure 6 — Recommended PCB Layout (Bottom Layer)
17
SC286
Outline Drawing – 4x4 MLPQ-UT28
DIMENSIONS
A
D
PIN 1
INDICATOR
(LASER MARK)
DIM
B
A
A1
A2
b
D
D1
E
E1
e
L
N
aaa
bbb
E
A2
A
aaa
INCHES
MIN
.020
.000
.006
.154
.100
.154
.100
.012
NOM MAX
.024
.001
(.006)
.008
.010
.157
.161
.104
.108
.157
.161
.104 .108
.016 BSC
.016
.020
28
.003
.004
MILLIMETERS
MIN
0.50
0.00
NOM
(0.152)
0.15
0.20
3.90
4.00
2.55 2.65
3.90 4.00
2.55
2.65
0.40 BSC
0.30
0.40
28
0.08
0.10
MAX
0.60
0.02
0.25
4.10
2.75
4.10
2.75
0.50
SEATING
C
C
A1
PLANE
LxN
D1
E/2
E1
2
1
N
e
bxN
D/2
bbb
C
A
B
NOTES:
1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
2. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS.
18
SC286
Land Pattern – 4x4 MLPQ-UT28
K
DIMENSIONS
(C)
G
H
DIM
INCHES
MILLIMETERS
C
(.156)
(3.95)
G
.122
3.10
H
.104
2.65
K
.104
2.65
P
.016
0.40
X
.008
0.20
Y
.033
0.85
Z
.189
4.80
Z
Y
X
P
NOTES:
1.
2.
CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES).
THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY.
CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR
COMPANY'S MANUFACTURING GUIDELINES ARE MET.
3.
THERMAL VIAS IN THE LAND PATTERN OF THE EXPOSED PAD
SHALL BE CONNECTED TO A SYSTEM GROUND PLANE.
FAILURE TO DO SO MAY COMPROMISE THE THERMAL AND/OR
FUNCTIONAL PERFORMANCE OF THE DEVICE.
4.
SQUARE PACKAGE-DIMENSIONS APPLY IN BOTH X AND Y DIRECTIONS.
19
SC286
© Semtech 2011
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Contact Information
Semtech Corporation
Power Management Products Division
200 Flynn Road, Camarillo, CA 93012
Phone: (805) 498-2111 Fax: (805) 498-3804
www.semtech.com
20