SC3203 3A EcoSpeed® Step-Down Regulator with Power Save POWER MANAGEMENT Features Description The SC3203 is an integrated, synchronous 3A EcoSpeed® step-down regulator. It incorporates Semtech’s advanced, patented adaptive on-time architecture to achieve bestin-class dynamic performance using point-of-load applications. The input voltage range is 9V to 16V, and the output voltage is adjustable from 0.75V to 7.5V. The device features an internal LDO and automatic PSAVE mode for high efficiency across the output load range. Input voltage — 9V to 16V Programmable VIN UVLO Output voltage adjustable from 0.75V to 7.5V Output current — Up to 3A Internal reference — + 2% Supports ceramic capacitors Low component count Power good output (open-drain) Low RDSON mosfets 65mΩ low-side/100mΩ high-side ENABLE input Programmable VIN UVLO and hysteresis VIN Under-Voltage Lock Out 500kHz switching frequency Adaptive on-time control: Excellent transient response Pseudo-fixed frequency during CCM Fault protection features: Over-current/Over-voltage/Under-voltage Over-temperature Automatic Restart (Hiccup) Internal soft-start Start-up into pre-bias output Power Save and Smart Power Save Internal LDO for bias voltage SOIC8-EP5 lead-free package WEEE and RoHS compliant and halogen-free • • • Switching frequency is internally programmed to 500kHz. Semtech’s adaptive on-time control provides pseudo-fixed frequency operation in continuous conduction combined with excellent transient performance. • • Additional features include cycle-by-cycle current limit, soft start, output over voltage and over temperature protection, and automatic fault recovery. The open-drain PGOOD pin provides output status. • • • Typical Application Circuit Applications Consumer Electronics, DTV and Set-top Boxes Networking Equipment, Embedded Systems Medical Equipment, Office Automation Instrumentation, Portable Systems Point of Load Converters 3.3 V SC3203 R PGOOD PGOOD PGOOD E n a b le EN V IN BST LX 1µ BYP PAD 1 0n L V OUT C TOP V IN C IN Rev 2.1 The device is available in a lead-free SOIC8-EP5 package. VFB AGND 4 9 .9 Ω © 2015 Semtech Corporation R TOP R BOT C OUT SC3203 Pin Configuration Ordering Information TOP VIEW EN 1 8 VFB BST 2 7 PGOOD LX 3 6 BYP V IN 4 5 AGND Device (1)(2) Package SC3203SETRC SOIC8-EP5 SC3203EVB Evaluation Board Notes: (1) Available in tape and reel only. A reel contains 3,000 devices. (2) Lead-free packaging only. Device is WEEE and RoHS compliant and halogen-free. PGND PAD SOIC8-EP5 Marking Information T o p M a rk S C 3203 yyw w xxxxx yyww = Date code xxxxx = Lot code SC3203 Absolute Maximum Ratings Recommended Operating Conditions LX to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18 Supply Input Voltage (V) . . . . . . . . . . . . . . . . . . . . . . . 9 to 16 EN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18 Maximum Continuous Output Current (A). . . . . . . . . . . . 3.0 VIN to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +18 Maximum Peak Inductor Current (A). . . . . . . . . . . . . . . 4.0 BST to LX (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 BST to PGND (V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +23 BYP to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 PGOOD to AGND (V). . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to +6.0 VFB to AGND (V). . . . . . . . . . . . . . . . . . . . . . . . -0.3 to BYP +0.3 AGND to PGND (V). . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3 to 0.3 Maximum Peak Inductor Current (A). . . . . . . . . . . . . . . . . 5.0 Peak IR Reflow Temperature (°C ). . . . . . . . . . . . . . . . . . . . . 260 BST to LX Capacitance (nF). . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Thermal Information Storage Temperature (°C ). . . . . . . . . . . . . . . . . . -60 to +150 Maximum Junction Temperature (°C ). . . . . . . . . . . . . . . . 150 Operating Junction Temperature (°C ). . . . . . . -40 to +125 Thermal Resistance Junction to Ambient(2) (°C/W ). . . . .36 Thermal Resistance Junction to Case(2) (°C/W ). . . . . . . .5.5 ESD Protection Level (kV)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . 5kV Exceeding the above specifications may result in permanent damage to the device or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not recommended. NOTES: (1) Tested according to JEDEC standard JESD22-A114-B. (2) Calculated from package in still air, mounted to 3 x 4.5 (in), 4 layer FR4 PCB with thermal vias under the exposed pad per JESD51 standards. Electrical Characteristics Unless specified: VIN =12V, TA=+25°C for Typ, -40°C to +85°C for Min and Max, TJ < 125°C, per detailed application circuit Parameter Conditions Typ Max Units VIN rising edge, EN = VIN 4.40 4.55 V Hysteresis, EN = VIN 0.30 Min Input Supply VIN UVLO Threshold VEN = 0V VIN Supply Current V 10 No switching, IOUT = 0A, VFB 5% higher than the VFB On-time Threshold 0.35 μA mA Controller VFB On-Time Threshold Accuracy VFB Input Bias Current 736 750 0.2 766 mV μA SC3203 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units VIN = 12V, VOUT = 3.3V 476 560 644 ns Timing On-time accuracy Minimum Off-Time 260 ns Automatic Restart Cycle Time 32 ms 1.8 ms Soft start Soft start Time From PWM Switching to Output Regulation Current Sense Zero-Crossing Detector Threshold LX - PGND -10 0 +10 mV Fault Protection Output Under-Voltage Threshold VFB with respect to nominal, 8 Consecutive Switching Cycles 75 %VREF Output Over-Voltage Threshold VFB with respect to nominal 120 %VREF Smart PowerSave Protection Threshold VFB with respect to nominal 110 %VREF OV, UV Fault Noise Immunity Delay 2.5 μs Over-Temperature Shutdown 160 °C From EN rising edge to PGOOD high 3.3 ms FB rising edge 90 % FB falling edge 85 % FB rising edge 120 % EN Input Logic High Threshold (VEN_BYP) VIN = 12V; EN rising edge; BYP on; Switcher off 1.0 V EN Input Logic High Threshold (VEN_ON) VIN = 12V; EN rising edge; BYP on, Switcher on 1.5 V EN Input Voltage Hysteresis Hysteresis at VEN_ON threshold 100 mV EN Input Current Hysteresis Hysteresis at VEN_ON threshold 1.75 μA PGOOD Output PGOOD Startup Delay Time PGOOD Under-voltage Threshold PGOOD Over-voltage Threshold Enable Input(1) EN Input Bias Current EN Input Resistance VEN = 12V EN < VEN_ON Threshold; EN rising edge -1 10 810 μA kΩ SC3203 Electrical Characteristics (continued) Parameter Conditions Min Typ Max Units Boost Switch BST Switch On-Resistance BYP = 5V 12 Ω Internal Power mosfets Current Limit Inductor Valley Current Limit, LDO=5V High Side LX Leakage Current 3.0 3.75 4.5 A VIN=16V, LX=0V, High Side mosfet off 1 5 µA High Side 100 Low Side 65 Switch Resistance mΩ Note: (1) See Applications Information for a description of the EN input operation. SC3203 Detailed Application Circuit V e xt R PGOOD SC3203 PGOOD PGOOD E n a b le EN V IN V IN C IN 1µ BYP PAD 1 0nF BST LX VFB AGND V O U T @ 3A L V OUT R TOP 4 9.9 Ω C TOP C OUT R BOT Component Selection VOUT (V) 0.9V 1.0V 1.1V 1.2V 1.5V 1.8V 2.5V 3.3V 5.0V L (µH) 2.2 4.7 COUT (µF) 2x22uF X5R, 0805 case, 10V 2x10uF X5R, 0805 case, 10V RTOP (kΩ) 39.2 66.5 31.6 30.1 24.3 20.5 19.6 16.5 26.1 RBOT (kΩ) 200 200 69.8 51.1 24.9 15 8.66 4.99 4.75 CTOP (pF) 22 18 27 33 39 47 68 82 82 SC3203 Typical Characteristics Efficiency vs Load — 2.5V, 3.3V, 5V output Efficiency vs Load — 1V, 1.5V, 1.8V output VIN = 12V 100 100 90 90 80 80 70 1V 1.5V 1.8V 60 50 Effciency (%) Effciency (%) 70 40 30 20 VIN = 12V 60 2.5V 3.3V 5V 50 40 30 0.0 0.5 1.0 1.5 2.0 2.5 20 3.0 Load (A) 0.0 2.0% 1.5% 1.0% 1.0% 0.5% 0.5% VOUT accuracy (%) VOUT accuracy (%) VIN = 12V 0.0% -0.5% 1V -1.0% 1.5V 1.8V -1.5% 0.0 0.5 1.0 1.5 2.0 2.5 -0.5% 3.3V 5V -1.5% 3.0 -2.0% 0.0 0.5 1.0 500 450 450 400 350 Frequency (kHz) Frequency (kHz) 550 500 1V 300 1.5V 250 1.8V 200 150 3.0 250 200 150 50 2.5 3.0 2.5V 3.3V 5V 300 100 2.0 VIN = 12V 350 50 Load (A) 2.5 400 100 1.5 2.0 Switching Frequency vs Load - 2.5V, 3.3V, 5V 600 1.0 1.5 Load (A) 550 0.5 3.0 2.5V -1.0% VIN = 12V 0.0 2.5 0.0% Switching Frequency vs Load - 1V, 1.5V, 1.8V 0 2.0 VIN = 12V Load (A) 600 1.5 Load Regulation - 2.5V, 3.3V, 5V output 1.5% -2.0% 1.0 Load (A) Load Regulation - 1V, 1.5V, 1.8V output 2.0% 0.5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 Load (A) SC3203 Typical Characteristics (continued) Load Transient, 0A to 3A to 0A - 3.3VOUT Load Transient, 1.5A to 3A to 1.5A - 3.3VOUT VOUT = 3.3V, VIN = 12V VOUT = 3.3V, VIN = 12V VOUT (100mV/div) VOUT (100mV/div) LOAD (2A/div) LOAD (2A/div) LX (20V/div) LX (20V/div) Time (200µs/div) Time (200µs/div) Load Transient, 0A to 3A to 0A - 1.5VOUT Load Transient, 1.5A to 3A to 1.5A - 1.5VOUT VOUT = 1.2V, VIN = 12V VOUT = 1.2V, VIN = 12V VOUT (50mV/div) VOUT (50mV/div) LOAD (2A/div) LOAD (2A/div) LX (20V/div) LX (20V/div) Time (1ms/div) Time (200µs/div) Startup - EN controlled Startup - VIN ramp VOUT = 3.3V, VIN ramp-up to 12V, EN connected to VIN VOUT = 3.3V, VIN = 12V EN(5V/div) VIN, EN(10V/div) VOUT (2V/div) VOUT (2V/div) PGOOD(5V/div) PGOOD(5V/div) LX (20V/div) LX (20V/div) Time (1ms/div) Time (1ms/div) SC3203 Typical Characteristics (continued) Power Save Switching - 100mA Load Power Save Switching - No Load VOUT = 3.3V, VIN = 12V, 100mA load VOUT = 3.3V, VIN = 12V, no load VOUT (100mV/div) VOUT (100mV/div) LX (10V/div) LX (10V/div) Time (1ms/div) Time (4µs/div) Continuous Mode Switching - 3A Load Hiccup Recovery from Over-Current VOUT = 1.2V, VIN = 12V VOUT = 3.3V, VIN = 12V, 3A Load VOUT (50mV/div) VOUT (100mV/div) LOAD (2A/div) LX (10V/div) LX (10V/div) Time (1µs/div) Time (20ms/div) Pre-bias Startup Shutdown via EN control VOUT = 1.2V, VIN = 12V, Load = 1A VOUT = 1.2V, VIN = 12V, Load = 10mA EN(5V/div) EN(5V/div) VOUT (500mV/div) VOUT (1V/div) PGOOD(5V/div) PGOOD(5V/div) LX (20V/div) LX (20V/div) Time (1ms/div) Time (400µs/div) SC3203 Pin Descriptions Pin # Pin Name Pin Function 1 EN Enable input for switching regulator —Pull EN high to enable the LDO and PWM. Connect to PGND to disable the PWM. Connect a resistor divider from VIN to program the external VIN Under-voltage threshold. 2 BST Boost Supply pin — Connect a 10nF capacitor between BST and LX to develop the floating voltage for the high-side gate drive. 3 LX Switching (phase) node. LX is also the sense point for the Zero Current Detector. 4 VIN Power input for the High Side Mosfet and for the input to the LDO. VIN is the also sense point for the internal VIN Under-voltage Lockout and the VIN input for the On-time Generator. 5 AGND 6 BYP 7 PGOOD 8 VFB Feedback input — Connect this pin to a resistor/capacitor divider between the output voltage and AGND. See the Table on the Typical Application Circuit for recommended values. PAD PGND Power ground connection. PAD is ground for the power circuits of the IC. The PGND pad should connect directly to the AGND pin, see Layout Guidelines. Ground for the internal analog circuitry. Connect this directly to the PAD for the PGND connection. Bypass pin for the internal 5V LDO which supplies bias voltage for the analog and gate drive circuits— A 1uF decoupling capacitor is required — The LDO is enabled when the EN pin exceeds typically 1V. Open-drain Power Good output. 10 SC3203 Block Diagram EN 1 PGOOD BST 7 2 V IN V IN U V L O BYP 6 LDO FB LDO 5V L D O P W M C o n tro l a n d S ta tu s F a u lt D e te ct a n d H iccu p R e fe re n ce S o ft S ta rt LX REF VFB 8 V IN FB C o m p a ra to r G a te D rive C o n tro l 4 V IN 3 LX LDO O n -T im e G e n e ra to r PAD PGND Z e ro C ro ss D e te cto r R ILIM V a lle y C u rre n t L im it 5 AGND IL IM 11 SC3203 Applications Information Synchronous Buck Converter The SC3203 is a step down synchronous buck DC-DC regulator. The device supports 3A operation at high efficiency in an SOIC-8 package. The buck regulator employs pseudofixed frequency adaptive on-time control. The 500kHz operating frequency enables the user to optimize the design for minimal board space and optimum efficiency. The adaptive on-time control provides fast transient response and allows reduced size for the power filter. The on-time pulse width is determined by the DC voltage of LX and by VIN. The pulse width is proportional to the DC voltage of LX and inversely proportional to the input voltage. With this adaptive on-time design, the device automatically anticipates the on-time needed to regulate VOUT for the present VIN condition. The on-time is approximated by the following equation: Input Voltage Range The SC3203 operates over the input range of 9V to 16V. The internal LDO generates a fixed 5V output that provides bias power for the device. Adaptive On-time Control The pseudo-fixed frequency, adaptive on-time control is shown in Figure 1. The ripple voltage generated at the output capacitor is divided down by the feedback resistor network and used as a PWM ramp signal. When the FB pin falls to the FB threshold a single on-time pulse for the high-side mosfet Q1 is triggered. V IN TON 9 /; 9,1 uN+] W 21 When the on-time completes, the low-side mosfet Q2 (Figure 1) is turned on. Q2 must stay on for the minimum off-time of 260nsec, and remains on until one of the following occurs: • • VFB falls below the 750mV reference. If this occurs, Q2 turns off and Q1 turns on for another high-side on-time. If operating in PSAVE mode, Q2 turns off if the inductor current falls to zero. If the FB pin is above the 750mV reference, both Q2 and Q1 remain off, and the output current is supplied by the output capacitor. V LX VOUT Voltage Selection C IN V IN V FB F B T hreshold Q1 LX V LX Q2 PGND V OUT L C OUT R TOP C TOP FB S C 3203 The output voltage is regulated by comparing the voltage at the FB pin to the internal 750mV reference voltage, see Figure 2. V OUT R to p C TOP R BOT Figure 1 — Adaptive On-time Control One-Shot Timer and Operating Frequency T o F B p in Rbot 49 .9Ω Figure 2 — Output Voltage Selection When the FB pin falls to the FB Threshold (750mV), the device sends a single on-time pulse to the high-side mosfet. 12 SC3203 Applications Information (continued) The output voltage is approximated by the following equation: 9287 § 5 · u ¨¨ 723 ¸¸ © 5%27 ¹ Note that the Adaptive On-time control regulates the valley of the FB ripple voltage, not the DC value. In practice the DC value of FB and VOUT can be slightly higher than the value predicted by DC equations; this is easily corrected by reducing the value of RTOP slightly. For recommended values of the FB components for different VOUTs, see the Table in the Detailed Application Circuit. Power-save Operation At light loads the SC3203 enters power-save mode to improve efficiency. During the low-side on-time, the internal zero-cross comparator monitors inductor current via the LX voltage across the low-side mosfet. If the inductor current falls to zero for 8 consecutive switching cycles, the controller enters power-save (PSave) mode. In PSave mode, after the high-side on-time has completed and the low-side mosfet is on, the low-side is turned off when the inductor current reaches zero. At this time both mosfets remain off until VFB drops to the 750mV threshold. While the mosfets are off, the load is supplied by the output capacitor. Figure 4 shows power-save operation at light loads. Continuous Mode Operation The SC3203 operates in CCM (Continuous Conduction Mode) when the load current exceeds 50% of the inductor ripple current (Figure 3). In this mode one of the power mosfets is always on, with no intentional dead time other than to avoid cross-conduction. This mode of operation results in typically 500kHz operation. F B R ipple V oltage (V F B ) D ead tim e varies according to load F B R ipple V oltage (V F B ) F B threshold (750 m V ) Inductor C urrent F B threshold (750 m V ) Z ero (0A ) O n-tim e (T O N ) L X rin g in g (p a ra sitic L C ) LX = V OUT LX Inductor C urrent D C Load C urrent LX on -tim e is triggered w hen V F B reaches the F B T hreshold . L X tri-sta te s w h e n in d u cto r cu rre n t re a ch e s ze ro. L X d rive s to P G N D w h e n o n -tim e is co m p le te d. Figure 4 — Power-save Operation O n-tim e LX on -tim e is triggered w hen V F B reaches the F B T hreshold . (T O N ) LX LX drives to P G N D w hen on -tim e is com pleted . LX rem ains low (P G N D ) until V F B falls to the F B threshold . Figure 3 — Continuous Mode Operation While operating in power-save mode, after each high-side on-time, the low-side turns on for at least the minimum 260nsec off-time. After this, if the inductor current has not reached zero and the FB pin falls below the FB threshold, power-save operation is terminated. The controller immediately generates a high-side on-time and returns to Continuous Mode Operation, resulting in a rapid response to large step load increases. 13 SC3203 Smart Power Save Protection Loads or circuits which are connected to more than one DC source may leak current from a higher voltage into a lower voltage. If the SC3203 provides the lower voltage and is operating in PSave mode, this leakage can cause V OUT to slowly rise during the dead-time when both mosfets are off. If the leakage is high it can drive VOUT up to the over-voltage threshold, resulting in a shutdown. Smart power save prevents this condition. When the FB pin exceeds 10% above nominal (exceeds 825mV), the device immediately disables power-save and turns on the low-side mosfet. This draws current from VOUT through the inductor and causes VOUT to fall. When VFB drops back to the 750mV trip point, a normal on-time switching cycle begins. Typically the device will return to normal powersave operation. This method prevents a hard OVP shutdown and also cycles energy from VOUT back to VIN. Figure 5 shows typical Smart PSave operation. V O U T a n d V F B rise d u e to le a ka g e cu rre n t flo w in g in to C O U T S m a rt P o w e r S a ve T h re sh o ld (8 2 5m V ) Inductor Current Applications Information (continued) IP E A K I LO A D I LIM Time Figure 6 — Valley Current Limit Enable Input and VIN UVLO The EN input is used to enable or disable the switching regulator. The EN pin has two thresholds. The first threshold at typically 1V activates the internal LDO. The second threshold at 1.5V turns on the switcher. The EN input also features a programmable input UnderVoltage Lockout (VIN UVLO). A resistor divider to the EN pin allows the user to select a VIN point at which the switcher will turn off. The EN circuit is shown in Figure 7. V O U T d isch a rg e s via in d u cto r th ro u g h L X to P G N D . N o rm a l V O U T rip p le F B th re sh o ld 1.5 V R E F V IN L X tri-sta te d H ysteresis 100 m V LX L X d rive s lo w (P G N D ) w h e n S m a rt P S A V E th re sh o ld is re a ch e d S in g le L X o n-tim e p u lse L X d rive s lo w (P G N D ) a fte r L X o n-tim e a n d w h e n F B re a ch e s F B re tu rn s to P o w e r S a ve th re sh o ld R1 EN R2 Figure 5 — Smart Power Save R EN EN C om parator O n /O ff Current Limit Protection Current limiting is accomplished by sensing the low-side mosfet current. If this mosfet current exceeds the Current Limit value (typically 3.75A), the mosfet is kept on. The controller will not allow another high-side on-time until the current in the low-side mosfet falls to 3.75A. This method controls the inductor valley current as shown by ILIM in Figure 6. Figure 7 — Enable Input Circuit 14 SC3203 Applications Information (continued) When the EN input is below 1.5V, the switcher is off. mosfet Q1 is on and resistor REN is connected to the EN pin. When the EN pin reaches 1.5V, the comparator output drives high and the switcher is enabled. mosfet Q1 is then switched off, removing REN from the circuit which immediately raises the voltage at the EN pin and provides VIN hysteresis. An additional hysteresis of 100mV is provided internally at the comparator input. ramps up. If the output reaches normal levels, the PGood output will switch to high (open circuit) typically 3.3msec after the EN pin drives high to begin a soft start cycle. The equations for selecting the VIN_ON and VIN_OFF thresholds are shown below. Note that REN has a typical value of 810kΩ and tolerance of +/- 20%. Output Over-Voltage Protection § 5 5 · 9,1B21 9 u ¨ ¸ © 5 5(1 ¹ § 5 · 9,1B2)) 9 u ¨ ¸ © 5 ¹ Soft Start of PWM Regulator On startup, the FB rising edge threshold for PGood is 750mV -10% (675mV). Once PGood drives high, the FB pin must fall to 750mV -15% (638mV) before the PGood output will drive low. OVP (Over-Voltage Protection) becomes active as soon as the switcher is enabled. The OVP threshold is set at 750mV + 20% (900mV). When the FB pin exceeds the 900mV the low-side mosfet turns on. It will remain on while the lowside current is negative (remain on while current flows out of the LX pin). When the low-side current reaches zero or becomes positive (current into the LX pin), the low-side mosfet turns off and the LX pin is tri-stated. LX remains tri-stated until the FB pin falls below the 750mV +15% (863mV), which starts the Hiccup Mode timer and forces a 32msec delay before a new soft start cycle begins. The PGOOD output also drives low when the FB pin exceeds the OVP threshold. Soft start is achieved in the PWM regulator by ramping the internal FB Comparator reference from zero to 750mV. When the ramp voltage reaches 750mV, the ramp is ignored and the FB comparator switches over to a fixed 750mV threshold. During soft start the FB pin follows the internal ramp, which limits the start-up inrush current and provides a controlled soft start profile for a wide range of applications. Typical soft start ramp time is 1.8msec. Output Under-Voltage Protection During soft start the regulator turns off the low-side mosfet during any cycle if the inductor current falls to zero. This prevents negative inductor current, allowing the device to start into a pre-biased output with negligible drooping on the output. If the internal temperature rises to 160°C the device will shut down. The device remains off until the temperature drops to 150°C, which starts the Hiccup Mode timer and forces a 32msec delay before a new soft start cycle begins. Power Good Output The Power Good (PGood) output is an open-drain indicator. The output is open (high impedance) when the output is within normal regulation. During startup the PGood output is held low at AGND while the output When the FB pin falls to 75% of its nominal voltage (falls to 563mV) for eight consecutive clock cycles, the mosfets are turned off and the controller enters Hiccup Mode operation. Under-Voltage faults are normally caused by an output overload; the controller will automatically recover on the next soft start cycle after the overload is removed. Over-Temperature Protection Hiccup Mode (Automatic Fault Recovery) The SC3203 includes Hiccup Mode fault protection. If the switcher output shuts down due to a fault condition, the device remains off until the fault condition is removed, which begins the 32ms Hiccup Mode timer. After 32msec 15 SC3203 Applications Information (continued) has passed a new soft start cycle is attempted. After soft start, if the output is still in a fault condition the switcher will again shut down and wait another 32msec before attempting the next soft-start. The 32msec delay between soft start cycles reduces power loss and heating in the power components. Note that an external VIN UVLO event is treated internally as a fault condition and triggers the Hiccup Mode feature. This will lead to a delay on restart when VIN has recovered to a normal level. The EN pin can rise above the VIN UVLO threshold but the controller must complete a 32msec time-out before the switcher will start up. The same delay also occurs for OVP and Over-Temperature shut down. BYP UVLO and POR The BYP UVLO (Under-Voltage Lock-Out) circuitry inhibits switching and tri-states the power mosfets until the BYP voltage rises above 4.0V. An internal POR (Power-On Reset) occurs when BYP exceeds 4.0V, which resets the fault latch and enables the soft start ramp. The SC3203 then begins a soft start cycle. The PWM will shut off if BYP falls below 3.7V. Boost Supply The Boost supply provides bias for the high-side mosfet driver. Connect a 10nF between Boost and LX. Larger values of Boost capacitance should not be used, the Boost driver circuit is designed for 10nF. BYP Regulator The SC3203 has an internal regulator that supplies the bias voltage for the PWM controller. Although this voltage is available externally, the BYP regulator is designed for internal use only. The BYP pin requires a 1 μF bypass capacitor. When the EN pin exceeds typically 1V, the BYP regulator is enabled and goes through a start-up sequence. During start-up while the BYP output voltage remains below 4V, the BYP short-circuit protection is active and limits the current to typically 35mA. After BYP exceeds 4.0V the LDO operates in voltage regulation mode with output current limited to typically 100mA (see Figure 9). B Y P V o lta g e (V ) 5V 4V V o lta g e re g u la tin g w ith 1 0 0m A cu rre n t lim it S h o rt-circu it P ro te ctio n 3 5 m A Figure 9 — LDO Start-Up 16 SC3203 PCB Layout Guidelines The optimum layout for the SC3203 is shown in Figure 12. This layout shows an integrated mosfet buck regulator with a maximum current of 3A. The total PCB area is approximately 19.1mm x 11.3mm. • • • • • The VIN capacitor should be located immediately next to the VIN and PGND pins, and mounted on the same side of the pcb. Use wide traces or copper areas to connect between the capacitor and the IC pins. Place the inductor near the LX pin and route directly to the pin using wide, short traces. A 1μF BYP capacitor should be located at and directly connected to the BYP and AGND pins, and mounted on the same side of the pcb. A 0.01 μF Boost capacitor should be located at and directly connected to the BST and LX pins, and mounted on the same side of the pcb. Using the placement shown below, the power Ground plane can be a solid area that directly connects the ground points for CIN, COUT, the PGND PAD, and AGND pin. • • Connect the AGND pin directly to the PGND pad. For the RBOT connection to ground, route this to the AGND pin while avoiding the high-noise current path between CIN, the PGND PAD, and COUT. The FB trace and FB components should not be placed or routed near the high-noise switching nodes (LX, BST, VIN). Do not route FB traces under or near the inductor: magnetic fields from the inductor can induce switching noise into the FB signal and cause erratic operation. EN trace, 2nd layer FB trace for VOUT sense 2nd layer PGOOD trace, 2nd layer Figure 12 — PCB Layout 17 SC3203 Outline Drawing — SOIC8-EP5 A E /2 D e D IM A A1 A2 b c D E E1 e F H h L L1 N 01 aaa bbb ccc N E1 1 E 2 ccc C 2 X N /2 T IP S e /2 B D aaa C S E A T IN G P LA N E A2 A A1 b xN bbb C C A -B D F EXPOSED PAD D IM E N S IO N S M IL L IM E T E R S M IN N O M M A X 1 .2 5 1 .7 5 0 .0 0 0 .1 5 1 .2 5 1 .6 5 0 .3 1 0 .5 1 0 .1 7 0 .2 5 4 .8 0 4 .9 0 5 .0 0 6 .0 0 B S C 3 .8 0 3 .9 0 4 .0 0 1 .2 7 B S C 3 .8 5 2 .9 5 2 .1 5 2 .7 0 0 .2 5 0 .5 0 0 .4 0 0 .7 2 1 .2 7 (1.0 5) 8 0° 8° 0 .1 0 0 .2 5 0 .2 5 h 1 h H H c GAUGE P LA N E L 0 .2 5 (L1) S E E D E T A IL S ID E V IE W A D E T A IL 01 A NOTES: 1 . C O N T R O L LIN G D IM E N S IO N S A R E IN M ILLIM E T E R S (A N G LE S IN D E G R E E S ). 2 . D A T U M S -A - A N D -B - T O B E D E T E R M IN E D A T D A T U M P LA N E -H - . 3 . D IM E N S IO N S "E 1" A N D "D " D O N O T IN C L U D E M O LD F LA S H , P R O T R U S IO N S O R G A T E B U R R S . 4 . T H E M E A S U R E M E N T O F D IM E N S IO N "F " D O E S N O T IN C LU D E E X P O S E D T IE B A R . 18 SC3203 Land Pattern — SOIC8-EP5 E S O LD E R MASK D (C ) G F Z Y T H E R M A L V IA Ø 0.36m m P X D IM E N S IO N S D IM M ILLIM E T E R S (5.3 0) C 3.50 D 5.10 E 2.60 F 3.20 G P 1.27 0.60 X 2.10 Y 7.40 Z NOTES: 1 . C O N T R O LLIN G D IM E N S IO N S A R E IN M ILLIM E T E R S (A N G LE S IN D E G R E E S ). 2 . T H IS LA N D P A T T E R N IS F O R R E F E R E N C E P U R P O S E O N LY . C O N S U LT Y O U R M A N U F A C T U R IN G G R O U P T O E N S U R E Y O U R C O M P A N Y 'S M A N U F A C T U R IN G G U ID E LIN E S A R E M E T . 3 . T H E R M A L V IA S IN T H E LA N D P A T T E R N O F T H E E X P O S E D P A D S H A LL B E C O N N E C T E D T O A S Y S T E M G R O U N D P LA N E . F A ILU R E T O D O S O M A Y C O M P R O M IS E T H E T H E R M A L A N D /O R F U N C T IO N A L P E R F O R M A N C E O F T H E D E V IC E . 4 . R E F E R E N C E IP C -S M -782A , S E C T IO N 9.1, R LP N O . 300A . 19 SC3203 © Semtech 2015 All rights reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. 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