BL6312 2.7 W/CH Stereo Filter-Free Class-D Audio Power Amplifier Features Output power: 2.7W/Ch with 4Ω loader at VDD=5V 1.5W/Ch with 8Ω loader at VDD=5V Low supply current (Typical 7mA quiescent current) Low shutdown current (Typical 0.4µA shutdown current) Thermal protection and output over current protection are designed Optimized PWM output stage eliminates LC output filter Independent shutdown control for each channel Select gain of 6, 12, 18, 24 dB Internally generated 300-kHz switching frequency eliminates capacitor and resistor Internal pull-down resistor on shutdown terminal General Description The BL6312 is a 2.7-W high efficiency, stereo, filter-free class-D audio power amplifier in QFN20 package that requires only two external components. Features like 88% efficiency, improved RF-rectification immunity make the BL6312 ideal for cellular handsets. In cellular handsets, the earpiece, speaker phone, and melody ringer can each be driven by the BL6312. Applications Mobile phone、PDA MP3/4、PMP Portable electronic devices USB Speakers Educational toys Notebook PC http://www.belling.com.cn - Page 1 of 8 - Ver1.1 BL6312 Pin Diagrams 20 19 18 17 16 INL+ INL- AGND INR- INR+ QFN20 PACKAGE (Top View) VOR+ 14 3 PVDD PVDD 13 4 PGND PGND 12 5 VOL- VOR- 11 NC VOL+ AVDD 2 SDBR G0 SDBL G1 NC 1 6 7 8 9 10 15 Pin Description Pin # Name Description 1 G1 Gain select (MSB) 2 VOL+ Left channel positive differential output 3 PVDD Power Supply (Must be the same voltage as AVDD) 4 PGND Power Ground 5 VOL- Left channel negative differential output 6 NC No internal connection 7 SDBL Left channel Shutdown terminal (low active) 8 SDBR Right channel Shutdown terminal (low active) 9 AVDD Analog supply (Must be the same voltage as PVDD) 10 NC No internal connection 11 VOR- Right channel negative differential output 12 PGND Power Ground 13 PVDD Power Supply (Must be the same voltage as AVDD) 14 VOR+ Right channel positive differential output 15 G0 Gain select (LSB) 16 INR+ Right channel positive input 17 INR- Right channel negative input 18 AGND Analog Ground 19 INL- Left channel negative input 20 INL+ Left channel positive input Thermal PAD http://www.belling.com.cn Connect the thermal pad of QFN package to GND - Page 2 of 8 - Ver1.1 BL6312 Function Block Diagram PVDD PGND AVDD + INR+ Gain Adjust INR- Av2 = 2 V/V VoR- ShutDown Control SDBR VoR+ PWM Modulator and Power Driver Amp + - Start up & Protection OC Detect 300k Bias & Reference OSC & RAMP + INL+ Amp + - Gain Adjust INL- Av2 = 2 V/V VoL- ShutDown Control SDBL VoL+ PWM Modulator and Power Driver Start up & Protection OC Detect 300k AGND PVDD PGND Notes: Total Voltage Gain G1 G0 V/V dB 0 0 2 6 0 1 4 12 1 0 8 18 1 1 16 24 Figure 1. Function Block Diagram http://www.belling.com.cn - Page 3 of 8 - Ver1.1 BL6312 Application Circuit To Battery 4 .7 u 1u PVDD Ci Right Chann el Differenti al Input 0 .1 u AVDD INR + VoR+ INR - VoR- INL + VoL+ INL - VoL- Ci Ci Right Chann el Differenti al Input Ci G ain select LSB G0 G ain select MSB G1 Right cha nnel shutdown SDB R Left ch annel shutdown SDB L PGND AGND Figure 2. BL6312 Application Schematic With Differential Input To Battery 4 .7 u 1u Right Channel Single-ended Input Ci Left Channel Single-ended Input PVDD Ci 0 .1 u AVDD INR+ VoR+ INR- VoR- INL+ VoL+ INL- VoL- Ci Ci Gain select LSB G0 Gain select MSB G1 Right channel shutdown SDBR Left channel shutdown SDBL PGND AGND Figure 3. BL6312 Application Schematic With Single-Ended Input http://www.belling.com.cn - Page 4 of 8 - Ver1.1 BL6312 Electrical Characteristics The following specifications apply for the circuit shown in Figure 5. TA = 25℃, unless otherwise specified. Symbol ISD IQ VOS Parameter Shutdown Current Quiescent Current Output Offset Voltage CMRR Common Mode Rejection Ratio Channel crosstalk FSW AV TWU Conditions Typ. Max. VIN=0V, VSDB=0V, No Load 0.1 1.5 VDD = 2.5V, VIN = 0V, No Load 3.5 6 VDD = 3.6V, VIN = 0V, No Load 4.3 7.5 VDD = 5.5V, VIN = 0V, No Load 7 11 VDD = 2.5V to 5.5V 7 25 VDD = 2.5V to 5.5V f=1k Hz Modulation frequency Closed-loop voltage gain Wake-up time from shutdown Drain-Source resistance (on-state) Input impedance Min. Inputs shorted together, uA mA mV dB -110 dB 250 300 350 G1=0.35v, G0=0.35v 5.5 6 6.5 G1=0.35v, G0= VDD 11.5 12 12.5 G1= VDD , G0=0.35v 17.5 18 18.5 G1= VDD , G0= VDD 23.5 24 24.5 VDD = 3.6V Units -70 VDD = 2.5V to 5.5V Resistance from SDBR/SDBL to GND rDS(on) Spec kHz dB 1 142 150 VDD = 5.5V 400 VDD = 3.6V 500 VDD = 2.5V 700 AV=6 dB 28.1 AV=12dB 17.3 AV=18dB 9.8 AV=24dB 5.2 mS 158 kΩ mΩ kΩ Operating Characteristics VDD = 5V, TA = 25℃, unless otherwise specified. Symbol PO THD+N KSVR CMRR Parameter Conditions Spec Min. Typ. Output Power THD+N=10%, f=1KHz, RL = 4Ω 2.7 ( per channel ) THD+N=10%, f=1KHz, RL = 8Ω 1.6 Total Harmonic Po=1.0Wrms, f=1kHz, RL = 8Ω, AV=6dB 0.12 Distortion + Noise Po=0.5Wrms, f=1kHz, RL = 8Ω, AV=6dB 0.13 Supply ripple VDD = 5V, AV=6dB f=217Hz, rejection ratio V(Ripple)=200mVPP Common Mode Rejection Ratio http://www.belling.com.cn VDD = 5V, VIC = 1 VPP, f=217Hz - Page 5 of 8 - Max. Units W % -63 dB -70 dB Ver1.1 BL6312 VDD = 3.6V, TA = 25℃, unless otherwise specified. Symbol PO KSVR CMRR Vn Parameter Spec Conditions Output Power Min. Typ. THD+N=10%, f=1KHz, RL = 8Ω ( per channel ) W -63 dB VDD = 3.6V, VIC = 1 VPP, f=217Hz -70 dB VDD = 3.6V, input ac-grounded No weighting 50 with CI = 2uF, f=20~20kHz 38 VDD = 3.6V, input ac-grounded with CI = 2uF rejection ratio f=217Hz, V(Ripple)=200mVPP Rejection Ratio Output voltage noise Units 0.8 Supply ripple Common Mode Max. A weighting uVRMS Test Circuit 2u Signal input from measurement INR+ VoR+ 2u INR2u 2u INL- Gain select LSB G0 Gain select MSB G1 Right channel shutdown SDBR Left channel shutdown SDBL 30KHz LPF VO RL 30KHz LPF VO VoR- INL+ BL6312 Signal input from measurement Output to measurement RL VoL+ Output to measurement VoL- PVDD 1u AVDD PGND AGND 0.1u 4.7u Power + Supply - Figure 4. BL6312 test set up circuit http://www.belling.com.cn - Page 6 of 8 - Ver1.1 BL6312 VO+ 100 47nF VO- VO 100 47nF 30kHz LPF Figure 5. 30-kHz LPF for BL6312 test Notes: 1>. A 1uF capacitor should be placed as close as possible to PVDD pin, and a 0.1uF capacitor should be placed as close as possible to AVDD pin of the device 2>. Ci should be shorted for any Common-Mode input voltage measurement 3>. A 33uH inductor should be used in series with RL for efficiency measurement 4>. The 30 kHz LPF (shown in figure 5) is required even if the analyzer has an internal LPF http://www.belling.com.cn - Page 7 of 8 - Ver1.1 BL6312 Package Dimensions http://www.belling.com.cn - Page 8 of 8 - Ver1.1