BL6311B 3 Watt Mono Filter-Free Class-D Audio Power Amplifier Features Efficiency With an 8-Ω Speaker: 88% at 400 mW 80% at 100 mW 2.6mA Quiescent Current 0.4µA Shutdown Current Optimized PWM Output Stage Eliminates LC Output Filter Internally Generated 250-kHz Switching Frequency Eliminates Capacitor and Resistor Improved PSRR (−75 dB) and Wide Supply Voltage (2.8 V to 5.5 V) Eliminates Need a Voltage Regulator Fully Differential Design Reduces RF Rectification and Eliminates Bypass Capacitor Improved CMRR Eliminates Two Input Coupling Capacitors Available in space-saving package: 9-bump WLCSP for General Description The BL6311B is a 3-W high efficiency filter-free class-D audio power amplifier in a wafer chip scale package (WCSP) that requires only three external components. Features like 88% efficiency, −75dB PSRR, and improved RF-rectification immunity make the BL6311B ideal for cellular handsets. In cellular handsets, the earpiece, speaker phone, and melody ringer can each be driven by the BL6311B. Applications Mobile phone、PDA MP3/4、PMP Portable electronic devices Pin Diagrams http://www.belling.com.cn - Page 1 of 8 - Ver1.2 BL6311B Pin Description Pin # Name Description A1 IN+ Positive differential input A2 GND Power Ground A3 VO- Negative BTL output B1 VDD Power Supply B2 PVDD Power Supply B3 PGND Power Ground C1 IN- Negative differential input C2 SDB Shutdown terminal (low active) C3 VO+ Positive BTL output Function Block Diagram Av1 = 150k/Ri (B1) VDD 150k (B2) PVDD (C1) IN- (A3) Vo- PWM Modulator and Power Driver Amp1 (A1) IN+ (C3) Vo+ Av2 = 2 V/V (B3) PGND 150k (C2) SDB ShutDown Control 300k Start up & Protection Bias & Reference OSC & RAMP Notes: Total Voltage Gain = Av1 × Av 2 = 2 × (A2) GND OC Detect 150k RI Figure 1. Function Block Diagram http://www.belling.com.cn - Page 2 of 8 - Ver1.2 BL6311B Application Circuit VDD Ri Vi- + Differential Input Vi+ + ) p o Lo TL B &d e Ms Wo Pl C ( To Battery Cs Vo+ Vo- Ri GND Bias & ShutDown SDB OSC & RAMP Figure 2. BL6311B Application Schematic With Differential Input VDD Ci Ri Vi- + Differential Input Vi+ Ci + ) p Lo o T BL &d Me s W Po l C ( To Battery Cs Vo+ Vo- Ri GND Bias & ShutDown SDB OSC & RAMP Figure 3. BL6311B Application Schematic With Differential Input and Input Capacitors VDD Ci Sin le-ended Input Ri Vi- + Vi+ + ) p Lo o T BL &d Me s W Po l C ( To Battery Cs Vo+ Vo- Ri Ci GND SDB Bias & ShutDown OSC & RAMP Figure 4. BL6311B Application Schematic With Single-Ended Input http://www.belling.com.cn - Page 3 of 8 - Ver1.2 BL6311B Absolute Maximum Ratings Supply voltage -0.3V to 6V Input voltage -0.3V to VDD+0.3V Junction Temperature -40 to +150 Storage Temperature -65 to +150 Note: Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. Recommended Operating Conditions Min Max Unit Supply Voltage 2.8 5.5 V Shutdown Voltage Input High 1.3 VDD V Shutdown Voltage Input Low 0 0.4 V Electrical Characteristics The following specifications apply for the circuit shown in Figure 5. TA = 25 , unless otherwise specified. Symbol ISD IQ Parameter Shutdown Current Quiescent Current VOS Output Offset Voltage PSRR Power Supply Rejection Ratio Conditions Spec Min. Typ. Max. VIN=0V, VSDB=0V, No Load 0.4 2 VDD = 2.8V, VIN = 0V, No Load 2.2 VDD = 3.6V, VIN = 0V, No Load 2.6 VDD = 5.5V, VIN = 0V, No Load 4.0 8 2 25 VIN = 0V, AV = 2V/V, VDD = 2.8V to 5.5V VDD = 2.8V to 5.5V Units uA mA mV -75 dB -68 dB VDD = 2.8V to 5.5V, CMRR Common Mode Rejection Ratio VIC = VDD/2 to 0.5V, VIC = VDD/2 to VDD - 0.8V FSW Modulation frequency VDD = 2.8V to 5.5V 200 250 300 kHz AV Voltage gain VDD = 2.8V to 5.5V 285k RI 300k RI 315k RI V/V RSDB ZI TWU rDS(on) Resistance from SDB to GND 300 Input impedance Wake-up time from shutdown 142 150 VDD = 3.6V 32 VDD = 2.8V 700 Drain-Source resistance (on-state) VDD = 3.6V 500 VDD = 5.5V 400 http://www.belling.com.cn - Page 4 of 8 - kΩ 158 kΩ mS mΩ Ver1.2 BL6311B Operating Characteristics VDD = 5V, RI = 150kΩ, TA = 25 Symbol PO THD+N SNR Spec Conditions Min. Typ. Max. Units THD+N=10%, f=1KHz, RL = 4Ω 3.0 THD+N=1%, f=1KHz, RL = 4Ω 2.4 THD+N=10%, f=1KHz, RL = 8Ω 1.7 THD+N=1%, f=1KHz, RL = 8Ω 1.4 Po=1.0Wrms, f=1kHz, RL = 8Ω 0.1 % Signal-to-Noise ratio VDD=5V, Po=1.0Wrms, RL = 8Ω 97 dB Output Power Total Harmonic Distortion + Noise W VDD = 3.6V, RI = 150kΩ, TA = 25 , unless otherwise specified. Symbol PO THD+N KSVR Vn CMRR Parameter , unless otherwise specified. Parameter Output Power Total Harmonic Distortion + Noise Spec Conditions Min. THD+N=1%, f=1KHz, RL = 4Ω 1.2 THD+N=10%, f=1KHz, RL = 8Ω 0.9 THD+N=1%, f=1KHz, RL = 8Ω 0.7 Po=0.5Wrms, f=1kHz, RL = 8Ω 0.1 % -68 dB rejection ratio f=217Hz, V(Ripple)=200mVPP Rejection Ratio Units 1.5 VDD = 3.6V, input ac-grounded with CI = 2uF Common Mode Max. THD+N=10%, f=1KHz, RL = 4Ω Supply ripple Output voltage noise Typ. VDD = 3.6V, input ac-grounded No weighting 48 with CI = 2uF, f=20~20kHz 36 A weighting VDD = 3.6V, VIC = 1 VPP, f=217Hz W uVRMS -70 dB VDD = 2.8V, RI = 150kΩ, TA = 25 , unless otherwise specified. Symbol PO THD+N Parameter Output Power Total Harmonic Distortion + Noise http://www.belling.com.cn Conditions Spec Min. Typ. THD+N=10%, f=1KHz, RL = 4Ω 0.92 THD+N=1%, f=1KHz, RL = 4Ω 0.75 THD+N=10%, f=1KHz, RL = 8Ω 0.52 THD+N=1%, f=1KHz, RL = 8Ω 0.41 Po=0.2Wrms, f=1kHz, RL = 8Ω 0.1 - Page 5 of 8 - Max. Units W % Ver1.2 BL6311B Test Circuit Ci Ri IN+ 2uF Si nal input from measurement VO+ 150K Vin BL6311B Ci Ri IN2uF 30 P RL Output to measurement VO VO- 150K Shutdown si nal SDB VDD GND CS 1uF Power + Supply - Figure 5. BL6311B test setup circuit VO+ 100 47nF VO VO- 100 47nF 30kHz LPF Figure 6. 30-kHz LPF for BL6311B test Notes: 1>. CS should be placed as close as possible to VDD/GND pad of the device 2>. Ci should be shorted for any Common-Mode input voltage measurement 3>. A 33uH inductor should be used in series with RL for efficiency measurement 4>. The 30 kHz LPF (shown in figure 5) is required even if the analyzer has an internal LPF Component Recommended Due to the weak noise immunity of the single-ended input application, the differential input application should be used whenever possible. The typical component values are listed in the table: RI CI CS 150 k 3.3 nF 2.2 uF http://www.belling.com.cn - Page 6 of 8 - Ver1.2 BL6311B (1) CI should have a tolerance of ±10% or better to reduce impedance mismatch. (2) Use 1% tolerance resistors or better to keep the performance optimized, and place the RI close to the device to limit noise injection on the high-impedance nodes. Input Resistors (RI) & Capacitors (CI) The input resistors (RI) set the total voltage gain of the amplifier according to Eq1 Gain = 2 × 150kΩ RI V V Eq1 The input resistor matching directly affects the CMRR, PSRR, and the second harmonic distortion cancellation. If a differential signal source is used, and the signal is biased from 0.5V ~ VDD-0.8V (shown in Figure2), the input capacitor (CI) is not required. If the input signal is not biased within the recommended common-mode input range in differential input application (shown in Figure3), or in a single-ended input application (shown in Figure4), the input coupling capacitors are required. If the input coupling capacitors are used, the RI and CI form a high-pass filter (HPF). The corner frequency (fC) of the HPF can be calculated by Eq2 fC = 1 2π ⋅ R I ⋅ C I (Hz ) Eq 2 Decoupling Capacitor (CS) A good low equivalent-series-resistance (ESR) ceramic capacitor (CS), used as power supply decoupling capacitor (CS), is required for high power supply rejection (PSRR), high efficiency and low total harmonic distortion (THD). Typically CS is 2 2µF, placed as close as possible to the device VDD pin. Order Information Part Number Package Shipping BL6311B CSP9 3000 pcs / Tape & Reel http://www.belling.com.cn - Page 7 of 8 - Ver1.2 BL6311B Package Dimensions http://www.belling.com.cn - Page 8 of 8 - Ver1.2