HD74LS162A Synchronous Decade Counter (synchronous clear) REJ03D0446–0300 Rev.3.00 Jul.15.2005 This synchronous decade counter features an internal carry look-ahead for application in high-speed counting designs. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs changes coincident with each other when so instructed by the count-enable inputs and internal gating. This mode is operation eliminates the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. This counter is fully programmable; that is, the outputs may be preset to either level. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse regardless of the levels of the enable inputs. Low-to-high transitions at the load input should be avoided when the clock is low if the enable inputs are high at or before the transition. The clear function is asynchronous and a low level at the clear input sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily as decoding the maximum count desired can be accomplished with one external NAND gate. The gate output is connected to the clear input to synchronously clear the counter to LLLL. Low-to-high transitions at the clear input should be avoided when the clock is low if the enable and load inputs are high at or before the transition. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional getting. Instrumental in accomplishing this function are two count-enable inputs and a ripple carry output. Both count-enable inputs (P and T) must be high to count, and input T is fed forward to enable the ripple carry output. The ripple carry output thus enabled will produce a high-level output pulse with a duration approximately equal to the high-level portion of the QA output. This high-level overflow ripple carry pulse can be used to enable successive cascaded stages. High-to-low-level transitions at the enable P or T inputs should occur only when the clock input is high. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS162AFPEL SOP-16 pin (JEITA) PRSP0016DH-B (FP-16DAV) FP EL (2,000 pcs/reel) Rev.3.00, Jul.15.2005, page 1 of 10 HD74LS162A Pin Arrangement Clear 1 CLR CK Ripple Carry 16 VCC 15 Ripple Carry Output Clock 2 A 3 A QA 14 QA B 4 B QB 13 QB C 5 C QC 12 QC D 6 D QD 11 QD Enable P 7 P T 10 Enable T GND 8 9 Load Data Inputs Outputs Load (Top view) Block Diagram Clock Clear D Q CK Q Load Enable Output QA P T A D CK Q Output QB Q B D Data Inputs CK C D CK D Q Output QC Q Q Output QD Q Ripple Carry Output Rev.3.00, Jul.15.2005, page 2 of 10 HD74LS162A Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Item VCC 7 V Input voltage VIN 7 V Power dissipation PT 400 mW Tstg –65 to +150 °C Storage temperature Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Clock pulse width Clear pulse width Symbol Min Typ VCC 4.75 5.00 5.25 V IOH — — –400 µA IOL — — 8 mA –20 25 75 °C ƒclock 0 — 25 MHz tw (clock) 25 — — ns tw (clear) Enable P, T Load tsu Clear Hold time Unit Topr A, B, C, D Setup time Max th 20 — — ns 20 — — ns 20 — — ns 20 — — ns 20 — — ns 3 — — ns Typical Clear, Preset, and Inhibit Sequence Clear Load A Data Inputs B C D Clock Enable P Enable T QA QB Outputs QC QD Ripple Carry Output 7 Clear Rev.3.00, Jul.15.2005, page 3 of 10 Preset (Load) 8 9 0 1 Count 2 Inhibit HD74LS162A Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH VIL min. 2.0 — typ.* — — max. — 0.8 Unit V V VOH 2.7 — — V IIH — — — — — — — — 0.4 0.5 20 40 µA VCC = 5.25 V, VI = 2.7 V IIL — — — — — — 40 –0.4 –0.8 mA VCC = 5.25 V, VI = 0.4 V II — — — — — –0.8 0.1 0.2 mA VCC = 5.25 V, VI = 7 V IOS ICCH — –20 — — — 18 0.2 –100 31 mA mA VCC = 5.25 V VCC = 5.25 V Output voltage VOL Input current Data, Enable P Load, Clock, Enable T Clear Data, Enable P Load, Clock, Enable T Clear Data, Enable P Load, Clock, Enable T Clear Short-circuit output current Supply current** V Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA IOL = 4 mA VCC = 4.75 V, VIH = 2 V, IOL = 8 mA VIL = 0.8 V ICCL — 19 32 mA VCC = 5.25 V Input clamp voltage VIK — — –1.5 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** ICCH is measured with the load input high, then again with the load input low, with all other inputs high and all outputs open. ICCL is measured with the clock input high, then again with the clock input low, with all other inputs low and all outputs open. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Maximum clock frequency Propagation delay time Symbol ƒmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPHL Rev.3.00, Jul.15.2005, page 4 of 10 Inputs Clock Outputs QA to QD Clock Ripple Carry Clock (Load = “H”) QA to QD Clock (Load = “L”) QA to QD Enable T Ripple Carry Clear QA to QD min. 25 — — — — typ. 32 20 18 13 18 max. — 35 35 24 27 Unit MHz ns ns ns ns — — 13 18 24 27 ns ns — — — 9 9 20 14 14 28 ns ns ns Condition CL = 15 pF, RL = 2 kΩ HD74LS162A Timing Method tw (CK) 3V Clock 1.3V 1.3V 1.3V 1.3V 0V tsu th 3V Clear 1.3V 1.3V tsu 0V th 3V Load 1.3V 1.3V tsu 0V th 3V Data Outputs A to D 1.3V 1.3V 0V tsu Enable P or T 1.3V th 3V 1.3V 0V Testing Method Test Circuit VCC Output QA 4.5V Load CK P.G. Zout = 50Ω See Testing Table Input QA A B C D Output QB QB QC P T 1. CL includes probe and jig capacitance. 2. All diodes are 1S2074(H). Rev.3.00, Jul.15.2005, page 5 of 10 Output QC Output QD QD Ripple CLR Carry Notes: Load circuit 1 CL Input P.G. Zout = 50Ω RL Same as Load Circuit 1. Same as Load Circuit 1. Same as Load Circuit 1. Ripple Carry Same as Load Circuit 1. HD74LS162A Testing Table Item From input to output ƒmax tPLH tPHL CK Ripply → Carry CK → Q CK → Q Enable → T CLR → Q Ripple Carry Inputs Clear Load 4.5V Enable 4.5V P 4.5V T 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V 4.5V GND 4.5V IN Clock Data IN A GND B GND C GND D GND 4.5V IN GND GND GND GND 4.5V GND 4.5V GND IN IN GND IN* GND IN* GND IN* GND IN* GND 4.5V IN IN** 4.5V GND GND 4.5V GND GND GND IN** 4.5V 4.5V 4.5V 4.5V Notes: *. Measuring outputs correspond to this condition, each outputs (QA, QB, QC, and QD) must not be over the following rate, “H”, “L”, “L”, and “H”. **. For initialized Item From input to output QA QB QC QD Ripple Carry CK→Ripple Carry CK→Q CK→Q Enable T→Ripple Carry OUT — OUT OUT — OUT — OUT OUT — OUT — OUT OUT — OUT — OUT OUT — OUT OUT — — OUT CLR→Q OUT OUT OUT OUT — ƒmax tPLH tPHL Outputs Rev.3.00, Jul.15.2005, page 6 of 10 HD74LS162A Waveforms 1 ƒmax, tPLH, tPHL, (Clock→Q, Ripple Carry) tTLH Clock 10% tPLH tTHL 3V 90% 90% 1.3V 1.3V 10% (Measure at tn + 1) 1.3V tw (CK) 1.3V 0V tPHL (Measure at tn + 2) VOH QA 1.3V tPHL tPLH (Measure at tn + 2) (Measure at tn + 4) QB 1.3V VOL VOH 1.3V VOL tPLH (Measure at tn + 4) tPHL (Measure at tn + 8) QC 1.3V VOH 1.3V VOL tPHL (Measure at tn + 10) QD tPLH (Measure at tn + 8) 1.3V VOH 1.3V VOL tPLH (Measure at tn + 9) Ripple Carry tPHL (Measure at tn + 10) VOH 1.3V 1.3V VOL Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle 50% and : ƒmax tTLH = tTHL ≤ 2.5 ns. tn is reference bit time when all outputs are low. Rev.3.00, Jul.15.2005, page 7 of 10 HD74LS162A Waveforms 2 tPLH, tPHL, (Clock→Q) tTLH tTHL 90% Clock 3V 90% 1.3V 10% tTLH 1.3V 10% 0V tTHL 90% Data Inputs A, B, C or D 3V 90% 10% 10% 0V tPLH tPHL VOH Outputs QA, QB, QC or QD 1.3V 1.3V VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, Clock input: PRR = 1 MHz, duty cycle 50%, Data input: PRR = 500 kHz, duty cycle 50% Waveforms 3 tPLH, tPHL, (Enable T→Ripple Carry) tTLH tTHL 90 % 1.3 V Enable T 3V 90 % 1.3 V 10 % 10 % tPLH 0V tPHL VOH Ripple Outputs Note: 1.3 V Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz Rev.3.00, Jul.15.2005, page 8 of 10 1.3 V VOH HD74LS162A Waveforms 4 tPHL, (Clear→Q) tTLH tTHL 90% Clock 3V 90% 1.3V 10% tTHL 10% tw (CLR) Clear ≥ 20ns 90% 1.3V 10% tTLH 90% 1.3V 10% 0V 3V 0V tPHL VOH QA to QD 1.3V VOL Note: Input pulse: tTLH ≤ 15 ns, tTHL ≤ 6 ns Rev.3.00, Jul.15.2005, page 9 of 10 HD74LS162A Package Dimensions JEITA Package Code P-SOP16-5.5x10.06-1.27 RENESAS Code PRSP0016DH-B *1 Previous Code FP-16DAV MASS[Typ.] 0.24g NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. D F 16 9 c HE *2 E bp Index mark Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) 1 Z *3 bp Nom D 10.06 E 5.50 Max 10.5 A2 8 e Dimension in Millimeters Min x A1 M 0.00 0.10 0.34 0.40 0.46 0.15 0.20 0.25 7.80 8.00 A L1 0.20 2.20 bp b1 c A c A1 θ y L Detail F 1 θ 0° HE 7.50 e 1.27 x 0.12 y 0.15 0.80 Z L L Rev.3.00, Jul.15.2005, page 10 of 10 8° 0.50 1 0.70 1.15 0.90 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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