HD74LS73A Dual J-K Flip-Flops (with Clear) REJ03D0414–0300 Rev.3.00 Jul.22.2005 Features • Ordering Information Part Name Package Type HD74LS73AP DILP-14 pin Package Code (Previous Code) PRDP0014AB-B (DP-14AV) Package Abbreviation Taping Abbreviation (Quantity) P — PRSP0014DE-A RP (FP-14DNV) Note: Please consult the sales office for the above package availability. HD74LS73ARPEL EL (2,500 pcs/reel) SOP-14 pin (JEDEC) Pin Arrangement 1CK 1CLR 1 J 2 1K 3 VCC 4 2CK 5 14 1J Q 13 1Q Q 12 1Q 11 GND Q 10 2K Q 9 2Q 8 2Q CLR CK K K CK 2CLR 6 2J 7 J CLR (Top view) Function Table Inputs Outputs Clear L Clock X J X K X Q L Q H H H ↓ ↓ L H L L Q0 H Q0 L H H ↓ ↓ L H H H L H H H X X QO Toggle H; high level, L; low level, X; irrelevant, ↓; transition from high to low level, Q0; level of Q before the indicated steady-state input conditions were established. Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established. Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓. Rev.3.00, Jul.22.2005, page 1 of 6 QO HD74LS73A Block Diagram (1/2) Q Q Clear K J Clock Absolute Maximum Ratings Symbol Ratings Unit Supply voltage Input voltage Item VCC VIN 7 7 V V Power dissipation Storage temperature PT Tstg 400 –65 to +150 mW °C Note: Voltage value, unless otherwise noted, are with respect to network ground terminal. Recommended Operating Conditions Item Supply voltage Output current Operating temperature Clock frequency Pulse width Setup time Hold time Symbol Min Typ Max Unit VCC IOH 4.75 — 5.00 — 5.25 –400 V µA IOL Topr — –20 — 25 8 75 mA °C fclock tw (Clock High) 0 20 — — 30 — MHz tw (Clear Low) tsu (“H” Data) 25 20↓ — — — — tsu (“L” Data) th 20↓ 0↓ — — — — Note: ↓; The arrow indicates the falling edge. Rev.3.00, Jul.22.2005, page 2 of 6 ns ns ns HD74LS73A Electrical Characteristics (Ta = –20 to +75 °C) Item Input voltage Symbol VIH min. 2.0 typ.* — max. — Unit V VIL — — 0.8 V VOH 2.7 — — V VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V, IOH = –400 µA VOL — — — — 0.5 0.4 V IOL = 8 mA IOL = 4 mA — — — — 20 60 µA VCC = 5.25 V, VI = 2.7 V — — — — 80 –0.4 — — — — –0.8 –0.8 mA VCC = 5.25 V, VI = 0.4 V — — 0.1 0.3 Output voltage J, K Clear IIH Clock J, K Input current IIL Clear Clock J, K Clear Condition VCC = 4.75 V, VIH = 2 V, VIL = 0.8 V II — — mA VCC = 5.25 V, VI = 7 V Clock Short-circuit output current IOS — –20 — — 0.4 –100 mA VCC = 5.25 V Supply current** Input clamp voltage ICC VIK — — 4 — 6 –1.5 mA V VCC = 5.25 V VCC = 4.75 V, IIN = –18 mA Notes: * VCC = 5 V, Ta = 25°C ** With all outputs open, ICC is measured with the Q and Q outputs high in turn. At time of measurement, the clock input is founded. Switching Characteristics (VCC = 5 V, Ta = 25°C) Item Symbol Maximum clock frequency fmax tPLH Propagation delay time Inputs Clear Clock tPHL Outputs Q, Q min. typ. max. Unit Condition 30 — 45 15 — 20 MHz ns CL = 15 pF, RL = 2 kΩ — 15 20 ns Timing Definition tw 3V 1.3 V 1.3 V 1.3 V Clock tsu th tsu 0V th 3V 1.3 V 1.3 V 1.3 V J, K 0V "H" Data Rev.3.00, Jul.22.2005, page 3 of 6 "L" Data HD74LS73A Testing Method Test Circuit 1. ƒmax, tPLH, tPHL, (Clock→Q, Q) VCC Output Q Input 4.5V RL J P.G. Q CL CK Zout=50Ω Load circuit 1 Output Q K CLR Notes: Q Same as Load Circuit 1. 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). 2. tPHL (Clear→Q), tPLH (Clear→Q) VCC Output Q 4.5V Input RL J P.G. Q CL CK Zout=50Ω Input Output Q K CLR Q P.G. Zout=50Ω Notes: 1. Test is put into the each flip-flop. 2. CL includes probe and jig capacitance. 3. All diodes are 1S2074(H). Rev.3.00, Jul.22.2005, page 4 of 6 Load circuit 1 Same as Load Circuit 1. HD74LS73A Waveforms 1 tTLH Clock tTHL tw(L) 90% 90% 1.3 V 1.3 V tw(H) 10% 3V 1.3 V 1.3 V 10% 0V tPLH tPHL VOH 1.3 V Q 1.3 V tPHL VOL tPLH Q VOH 1.3 V 1.3 V VOL Note: Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax, tTLH = tTHL ≤ 2.5 ns Waveforms 2 tTHL Clear tTLH 3V 90% 1.3V 10% 90% 1.3V 10% 0V tw (CLR) tTLH tTHL 3V Clock 10% 90% 90% 1.3V 1.3V tw (CK) ≥ 20ns tPHL 10% 0V VOH Q 1.3V tPLH VOL VOH 1.3V Q Note: Crear and clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, Rev.3.00, Jul.22.2005, page 5 of 6 VOL HD74LS73A Package Dimensions JEITA Package Code P-DIP14-6.3x19.2-2.54 RENESAS Code PRDP0014AB-B Previous Code DP-14AV MASS[Typ.] 0.97g D 8 E 14 1 7 b3 Z A1 A Reference Symbol Nom e1 7.62 D 19.2 E 6.3 A1 0.51 bp 0.40 L e1 0.48 c 0.19 θ 0° JEITA Package Code P-SOP14-3.95x8.65-1.27 RENESAS Code PRSP0014DE-A *1 0.56 e 2.29 0.31 2.54 2.79 15° 2.39 L 2.54 MASS[Typ.] 0.13g Previous Code FP-14DNV NOTE) 1. DIMENSIONS"*1 (Nom)"AND"*2" DO NOT INCLUDE MOLD FLASH. 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. F D 14 7.4 0.25 Z ( Ni/Pd/Au plating ) 20.32 1.30 b3 c Max 5.06 A θ bp e Dimension in Millimeters Min 8 c *2 Index mark HE E bp Reference Symbol Terminal cross section ( Ni/Pd/Au plating ) Dimension in Millimeters Min Nom Max D 8.65 9.05 E 3.95 A2 A1 7 1 Z e *3 bp 0.10 0.14 A x M bp L1 0.25 1.75 0.34 0.40 0.46 0.15 0.20 0.25 6.10 6.20 b1 c A c1 A1 θ L y Detail F θ 0° HE 5.80 1.27 e x 0.25 y 0.15 0.635 Z L L Rev.3.00, Jul.22.2005, page 6 of 6 8° 0.40 1 0.60 1.08 1.27 Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. 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