RENESAS HD74LS78A

HD74LS78A
Dual J-K Flip-Flops
(with Preset, Common Clear, and Common Clock)
REJ03D0419–0300
Rev.3.00
Jul.22.2005
Features
• Ordering Information
Part Name
Package Type
HD74LS78AFPEL
SOP-14 pin (JEITA)
Package Code
(Previous Code)
PRSP0014DF-B
(FP-14DAV)
Package
Abbreviation
Taping Abbreviation
(Quantity)
FP
EL (2,000 pcs/reel)
Note: Please consult the sales office for the above package availability.
Pin Arrangement
CK
1
1PR
2
1J
3
VCC
4
CLR
5
2PR
6
2K
7
K CK J
CLR
PR
Q
Q
K CK J
PR
Q
CLR
Q
14
1K
13
1Q
12
1Q
11
GND
10
2J
9
2Q
8
2Q
(Top view)
Function Table
Preset
Clear
Inputs
Clock
Outputs
J
K
Q
Q
L
H
H
L
X
X
X
X
X
X
H
L
L
H
L
H
L
H
X
↓
X
L
X
L
H*
Q0
H*
Q0
H
H
H
H
↓
↓
H
L
L
H
H
L
L
H
H
H
H
H
↓
H
H
X
H
X
Toggle
Q0
Q0
Notes: H; high level, L; low level, X; irrelevant, ↓; transition from high to low level,
Q0; level of Q before the indicated steady-state input conditions were established.
Q0; complement of Q0 or level of Q before the indicated steady-state input conditions were established.
Toggle; each output changes to the complement of its previous level on each active transition indicated by ↓.
* This configuration is nonstable; that is, it will not persist when preset and clear inputs return to their inactive (high) level.
Rev.3.00, Jul.22.2005, page 1 of 6
HD74LS78A
Block Diagram (1/2)
Q
Q
Clear
Preset
K
J
Clock
To Other F·F
Absolute Maximum Ratings
Item
Symbol
Ratings
Unit
Supply voltage
Input voltage
VCC
VIN
7
7
V
V
Power dissipation
Storage temperature
PT
Tstg
400
–65 to +150
mW
°C
Note: Voltage value, unless otherwise noted, are with respect to network ground terminal.
Recommended Operating Conditions
Item
Symbol
Min
Typ
Max
Unit
VCC
IOH
4.75
—
5.00
—
5.25
–400
V
µA
IOL
Topr
—
–20
—
25
8
75
mA
°C
fclock
tw
0
20
—
—
30
—
MHz
Clear Preset Low
“H” Data
tw
tsu
25
20↓
—
—
—
—
“L” Data
tsu
th
20↓
0↓
—
—
—
—
Supply voltage
Output current
Operating temperature
Clock frequency
Pulse width
Setup time
Clock High
Hold time
Rev.3.00, Jul.22.2005, page 2 of 6
ns
ns
ns
HD74LS78A
Electrical Characteristics
(Ta = –20 to +75 °C)
Item
Input voltage
Symbol
VIH
min.
2.0
typ.*
—
max.
—
Unit
V
VIL
—
—
0.8
V
VOH
2.7
—
—
V
VCC = 4.75 V, VIH = 2.7 V, VIL = 0.8 V,
IOH = –400 µA
VOL
—
—
—
—
0.5
0.4
V
IOL = 8 mA
IOL = 4 mA
—
—
—
—
20
120
—
—
—
—
60
160
µA
VCC = 5.25 V, VI = 2.7 V
—
—
—
—
–0.4
–1.6
—
—
—
—
–0.8
–1.6
mA
VCC = 5.25 V, VI = 0.4 V
—
—
—
—
0.1
0.6
—
—
—
—
0.3
0.8
mA
VCC = 5.25 V, VI = 7 V
IOS
–20
—
–100
mA
VCC = 5.25 V
ICC
—
4
6
mA
VCC = 5.25 V
Output voltage
J, K
Clear
Preset
Clock
Input
current
J, K
Clear
Preset
Clock
J, K
Clear
Preset
Clock
Short-circuit output
current
Supply current***
IIH
IIL**
II
Condition
VCC = 4.75 V, VIH = 2 V,
VIL = 0.8 V
Input clamp voltage
VIK
—
—
–1.5
V
VCC = 4.75 V, IIN = –18 mA
Notes: * VCC = 5 V, Ta = 25°C
** IIL should not be measured when preset and clear inputs are low at same time.
*** With all outputs open, ICC is measured with the Q and Q outputs high in turn.
At the time of measurement, the clock input is grounded.
Switching Characteristics
(VCC = 5 V, Ta = 25°C)
Item
Symbol
Maximum clock frequency
fmax
tPLH
Propagation delay time
Inputs
Clear
Preset
Clock
tPHL
Outputs
Q, Q
min.
typ.
30
45
max.
Unit
—
15
20
ns
—
15
20
ns
Condition
MHz
CL = 15 pF, RL = 2 kΩ
Timing Definition
tw
3V
1.3 V
1.3 V
1.3 V
Clock
tsu
th
tsu
0V
th
3V
1.3 V
1.3 V
1.3 V
J, K
0V
"H" Data
Rev.3.00, Jul.22.2005, page 3 of 6
"L" Data
HD74LS78A
Testing Method
Test Circuit
1. ƒmax, tPLH, tPHL, (Clock→Q, Q)
VCC
Output Q
Input 4.5V
RL
J
P.G.
PR
Q
CL
CK
Zout=50Ω
Load circuit 1
Output Q
K
Q
CLR
Notes:
Same as Load Circuit 1.
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
2. tPHL, tPLH (Clear, Preset→ Q, Q)
VCC
Input
Output Q
P.G.
Zout=50Ω
RL
PR
J
Load circuit 1
Q
CL
4.5V
Input
CK
K
CLR
Output Q
Q
P.G.
Zout=50Ω
Notes:
1. Test is put into the each flip-flop.
2. CL includes probe and jig capacitance.
3. All diodes are 1S2074(H).
Rev.3.00, Jul.22.2005, page 4 of 6
Same as Load Circuit 1.
HD74LS78A
Waveforms 1
tTLH
tTHL
tw(L)
90% 90%
1.3 V 1.3 V
Clock
3V
1.3 V
10%
1.3 V
10%
0V
tw(H)
tPLH
tPHL
VOH
1.3 V
Q
1.3 V
tPHL
VOL
tPLH
Q
VOH
1.3 V
1.3 V
VOL
Note:
Clock input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz, duty cycle = 50% and for fmax.,
tTLH = tTHL ≤ 2.5 ns
Waveforms 2
tTHL
Clear
tTLH
3V
90%
1.3V
10%
90%
1.3V
10%
tw (clear)
0V
tTHL
tTLH
90%
1.3V
10%
Preset
90%
1.3V
10%
tw (preset)
3V
0V
tPHL
tPLH
1.3V
Q
VOH
1.3V
tPLH
VOL
VOH
Q
Note:
1.3V
1.3V
tPHL
Crear and preset input pulse; tTLH ≤ 15 ns, tTHL ≤ 6 ns, PRR = 1 MHz,
Rev.3.00, Jul.22.2005, page 5 of 6
VOL
HD74LS78A
Package Dimensions
JEITA Package Code
P-SOP14-5.5x10.06-1.27
RENESAS Code
PRSP0014DF-B
*1
Previous Code
FP-14DAV
D
MASS[Typ.]
0.23g
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
F
14
8
c
HE
*2
E
bp
Index mark
Reference
Symbol
Terminal cross section
( Ni/Pd/Au plating )
1
Z
*3
Nom
Max
D
10.06
10.5
E
5.50
A2
7
e
A1
bp
Dimension in Millimeters
Min
x
M
0.00
0.10
0.34
0.40
0.46
0.15
0.20
0.25
7.80
8.00
A
L1
0.20
2.20
bp
b1
c
A
c
A1
θ
y
L
Detail F
1
θ
0°
HE
7.50
e
1.27
x
0.12
y
0.15
1.42
Z
L
L
Rev.3.00, Jul.22.2005, page 6 of 6
8°
0.50
1
0.70
1.15
0.90
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Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan
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