FSA2457 — Dual DPDT, 5 Analog Data Switch Features Description The FSA2457 is a bi-directional, low-power, dual double-pole double-throw (4PDT) analog switch targeted at dual 1-bit SIM/SD/MMC card and/or GPS signal multiplexing. It is optimized for switching the WLAN-SIM data and control signals at 52Mbps. Low On Capacitance for Data Path: 12pF Typical Low On Resistance for Data Path: 5Ω Typical Low Power Quiescent Consumption: 1μA Maximum Wide -3db Bandwidth: > 160MHz Packaged in Green 16-Lead UMLP (1.8 x 2.6mm) 4kV JEDEC: JESD22-A114 HBM 2kV JEDEC: JESD22-C101 CDM Applications Cell Phone, PDA, Digital Camera, Portable GPS LCD Monitor, TV, Set-Top Box IMPORTANT NOTE: For additional information, [email protected]. please contact The FSA2457 is compatible with the requirements of 1bit SIM/SD/MMC cards and is ideal for interfacing to GPS baseband processors. The FSA2457 features a low on capacitance (CON) of 12pF to ensure high-speed data transfer. The FSA2457 contains special circuitry that minimizes current consumption even when the control voltage applied to the SEL pin is lower than the supply voltage (VCC). This feature is especially valuable in ultra-portable applications, such as cell phones; allowing direct interface with the general-purpose I/Os of the baseband processor. Other applications include switching and connector sharing in portable cell phones, PDAs, digital cameras, printers, and portable GPS systems. Ordering Information Part Number Top Mark FSA2457UMX GD Eco Status Green Operating Temperature Range Package -40 to +85°C 16-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 1.8 x 2.6mm For Fairchild’s definition of Eco Status, please visit: http://www.fairchildsemi.com/company/green/rohs_green.html. 1B1 2B1 1A 1B2 2B2 2A 1B3 2B3 3A 1B4 2B4 /OE 4A Sel Figure 1. Analog Symbol © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 www.fairchildsemi.com FSA2457 — Dual DPDT, 5Analog Data Switch March 2013 /OE VCC Sel 1B1 16 15 14 13 2 11 2B4 1B2 3 10 4A 2B2 4 9 5 6 7 8 2B3 1A 3A 12 1B4 GND 1 2A 2B1 1B3 Figure 2. Pad Assignment UMLP16 (Top Through View) FSA2457 — Dual DPDT, 5Analog Data Switch Pin Configuration Pin Definitions Pin Description 1Bn, 2Bn Multiplexed Data Source Inputs nA Common Data Ports Sel Switch Select /OE Output Enable (Active LOW) Truth Table Sel /OE Logic LOW Logic LOW 1B1 = 1A, 1B2 = 2A, 1B3 = 3A, 1B4 = 4A Logic HIGH Logic LOW 2B1 = 1A, 2B2 = 2A, 2B3 = 3A, 2B4 = 4A X Logic HIGH Data Ports Disconnected © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 Function www.fairchildsemi.com 2 Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VCNTRL Parameter Supply Voltage DC Input Voltage (Sel, /OE)(1) Min. Max. Unit -0.5 +4.6 V -0.5 +4.6 V VCC + 0.5 V (1) VSW DC Switch I/O Voltage 1Bn, 2Bn, nA -0.5 IIK DC Input Diode Current -50 IOUT DC Output Current – VSW TSTG Storage Temperature MSL Moisture Sensitivity Level (JEDEC J-STD-020A) -65 mA 128 mA +150 °C 1 Level All Pins 4 I/O to GND 8 Human Body Model, JEDEC: JESD22-A114 ESD Charged Device Model, JEDEC: JESD22-C101 kV 2 FSA2457 — Dual DPDT, 5Analog Data Switch Absolute Maximum Ratings Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VCNTRL Parameter Supply Voltage Control Input Voltage (Sel, /OE) VSW Switch I/O Voltage 1Bn, 2Bn, nA IOUT DC Output Current 1Bn, 2Bn, nA TA (2) Operating Temperature Min. Max. Unit 2.7 3.6 V 0 VCC V -0.5 VCC V 25 mA 85 °C -40 Note: 2. The control input must be held HIGH or LOW; it must not float. © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 www.fairchildsemi.com 3 All typical values are at 25°C, 3.3V VCC unless otherwise specified. Symbol VIK VIH Parameter Clamp Diode Voltage Conditions IIN = -18mA VCC (V) TA = - 40ºC to +85ºC Min. Typ. 2.7 -1.2 2.7 to 3.0 1.8 3.3 to 3.6 2.0 Input Voltage High Input Voltage Low IIN Control Input Leakage (Sel) VSW = 0 to VCC 3.6 Off State Leakage 1Bn, 2Bn = 0V or Vcc Figure 4 3.6 RON Data Path Switch On Resistance(3) VSW = 0, 2.0V, ION = -20mA Figure 3, Figure 12 2.7 5.0 ∆RON Data Path Delta On Resistance(4) VSW = 0V, ION = -20mA 2.7 0.3 Quiescent Supply Current VCNTRL = 0 or VCC, IOUT = 0 3.6 ICC Units V V VIL Inc(off), Ino(off), Max. 2.7 to 3.6 0.8 V -1 1 µA -1 1 µA 7.0 1.0 FSA2457 — Dual DPDT, 5Analog Data Switch DC Electrical Characteristics µA Notes: 3. Measured by the voltage drop between nB0, 1Bn and relative common port pins at the indicated current through the switch. On resistance is determined by the lower voltage on the relative ports. 4. Guaranteed by characterization. © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 www.fairchildsemi.com 4 All typical value are for VCC = 3.3V at 25°C unless otherwise specified. Symbol Conditions tON Turn-On Time Sel or /OE to Output (nA) RL = 50Ω, CL = 30pF VSW = 1.5V Figure 5, Figure 6 2.7 to 3.6 7.0 ns tOFF Turn-Off Time Sel or /OE to Output (nA) RL = 50Ω, CL = 30pF VSW = 1.5V Figure 5, Figure 6 2.7 to 3.6 4.0 ns OIRR Off Isolation(5) (nA) RL = 50Ω, f = 25MHz, CL = 30pF Figure 9, Figure 13 2.7 to 3.6 -45 dB Xtalk Non-Adjacent Channel Crosstalk(5) (nA) RL = 50Ω, f = 25MHz, CL = 30pF Figure 7 2.7 to 3.6 -54 dB -3db Bandwidth(5) (nA) RL = 50Ω, CL = 30pF Figure 8, Figure 14 2.7 to 3.6 >160 MHz BW VCC (V) TA = - 40ºC to +85ºC Parameter Min. Typ. Max. Units FSA2457 — Dual DPDT, 5Analog Data Switch AC Electrical Characteristics Note: 5. Guaranteed by characterization. Capacitance Symbol CIN Parameter Control Pin Input Capacitance (6) Conditions TA = - 40ºC to +85ºC Min. Typ. Max. Units VCC = 0V 1.8 pF CON On Capacitance (nA) VCC = 3.3V, f = 1MHz Figure 10 12.0 pF COFF Off Capacitance(6) (nA) VCC = 3.3V Figure 9 6.0 pF Note: 6. Guaranteed by characterization. © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 www.fairchildsemi.com 5 V ON InA(OFF) NC 1Bn, 2Bn A nA VSW VSW ION GND R ON = VON / I ON GND GND VSel = 0 or VCC V Sel Figure 3. On Resistance = 0 or V CC Figure 4. Off Leakage tFALL = 2.5ns tRISE = 2.5ns 1Bn, 2Bn VCC nA VSW V RL OUT CL GND VCC /2 10% VOH RL and CL are functions of the application environment (see tables for specific values). CL includes test fixture and stray capacitance. Figure 5. 90% VCC /2 10% GND GND Sel 90% Input – VCNTRL FSA2457 — Dual DPDT, 5Analog Data Switch Test Diagrams VOL AC Test Circuit Load Figure 6. 90% 90% Output – VOUT t ON t OFF Turn-On / Turn-Off Waveforms Network Analyzer RS NC GND VIN VS GND VSel GND RT GND GND RS and RT are functions of the application environment (see tables for specific values). RT VOUT GND Crosstalk= 20 Log (VOUT / VIN) Figure 7. © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 Non-Adjacent Channel-to-Channel Crosstalk www.fairchildsemi.com 6 Network Analyzer RS VIN Network Analyzer RS VS GND RT GND VSEL GND RS and RT are functions of the application environment (see tables for specific values). Figure 8. Capacitance Meter VS GND VOUT GND GND RS and RT are functions of the application environment (see tables for specific values). RT GND RT GND Off Isolation = 20 Log (VOUT / VIN) Bandwidth Figure 9. Channel Off Isolation nA nA f = 1MHz VIN VSel VOUT GND GND Capacitance Meter VSel = 0 or VCC FSA2457 — Dual DPDT, 5Analog Data Switch Test Diagrams (Continued) VSel = 0 or VCC f = 1MHz 1Bn, 2Bn 1Bn, 2Bn Figure 10. Channel On Capacitance © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 Figure 11. Channel Off Capacitance www.fairchildsemi.com 7 RON (Ohms) 7.00 6.00 85°C 5.00 25°C 4.00 -40°C 3.00 2.00 -1.00 0.00 1.00 2.00 VIN VCC = 2.7V Figure 12. RON 3.00 4.00 FSA2457 — Dual DPDT, 5Analog Data Switch Typical Performance Characteristics Figure 13. Off Isolation Figure 14. Bandwidth © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 www.fairchildsemi.com 8 0.10 C 2.100 A 1.80 2X B 15X 0.563 0.663 1 PIN #1 IDENT 2.900 2.60 0.400 0.10 C 2X 16X 0.225 TOP VIEW 0.55 MAX. RECOMMENDED LAND PATTERN 0.10 C 0.152 0.08 C SEATING PLANE 0.050 C SIDE VIEW TERMINAL SHAPE VARIANTS FSA2457 — Dual DPDT, 5Analog Data Switch Physical Dimensions 0.40 0.60 5 0.15 0.25 9 0.100 0.100 15X PIN 1 0.40 0.30 15X 0.50 0.15 0.25 NON-PIN 1 Supplier 1 1 16 13 ALL TERMINALS 0.30 0.50 0.15 0.25 0.15 PIN 1 0.10 C A B 0.05 C 0.30 15X 0.50 15X 0.25 NON-PIN 1 Supplier 2 BOTTOM VIEW A. THIS PACKAGE IS NOT CURRENTLY REGISTERED WITH ANY STANDARDS COMMITTEE B. DIMENSIONS ARE IN MILLIMETERS. C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994 D. TERMINAL SHAPE MAY VARY ACCORDING TO PACKAGE SUPPLIER, SEE TERMINAL SHAPE VARIANTS E. LAND PATTERN IS A MINIMAL TOE DESIGN F. DRAWING FILE NAME : UMLP16AREV3 Figure 15. 16-Lead Ultrathin Molded Leadless Package (UMLP) Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/, © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 www.fairchildsemi.com 9 FSA2457 — Dual DPDT, 5Analog Data Switch © 2007 Fairchild Semiconductor Corporation FSA2457 Rev. 1.0.5 www.fairchildsemi.com 10