FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration Features Description The FSA641 is a 2:1 MIPI switch made for 2-data lane and 1-data lane modules. This part is configured as a single-pole, double-throw switch (SPDT) and is optimized for switching between two high-speed or low-power MIPI sources. The FSA641 has specially been designed for the MIPI specification and allows connection to either a CSI or DSI module. The FSA641 features an extremely low on capacitance (CON) of 8 pF. The wide bandwidth (1 GHz) results in signals with minimum edge and phase distortion. Superior channel-to-channel crosstalk minimizes interference. Switch Type: 2:1 Signal Types MIPI, DPHY VCC: 2.65 to 4.3 V Input Signals 0 to VCC RON: - 7 Ω Typical HS MIPI - 10 Ω Typical LS MIPI ∆RON: 0.75 Ω Typical HS & LS MIPI ICC: 1 µA Maximum Related Resources OIRR: -50 dB Typical For samples and questions, please contact: [email protected]. XTALK: -40 dB Typical FSA641 Demonstration Board Bandwidth: 1 GHz Typical Channel-to-Channel Skew: 15 ps Typical CON: 8 pF Typical Package 20-Lead UMLP Applications Cellular Phones, Smartphones Displays Ordering Information Part Number Top Mark Operating Temperature Range FSA641UMX F641 -40 to +85°C © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 Package 20-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 3.0 x 3.0 mm www.fairchildsemi.com FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration June 2014 FSA641 CLK MIPI Module #1 (Higher Bandwidth) Data [1:2] Ex. 5 Megapixel camera CLK MIPI Switch MIPI Module #2 (Low Bandwidth) Data [1:2] Processor CLK Data [1] Ex. VGA camera Figure 1. Mobile Phone Example © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 2 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration Typical Application F S A 64 1 CLKP CLKBN CLKBP D B 1N D B 1P 20 19 18 17 16 C LK A P C LK A N C LK P C LK N D A 1P D A 1N D A 2P D A 2N D 1P D 1N C LK B P C LK B N D B 1P D B 1N D 2P D 2N /O E S w itch C o ntro l SE L 0.1µF CLKN 1 15 C L K AP D 1P 2 14 C L K AN D 1N 3 13 D A1P D 2P 4 12 D A1 N D 2N 5 11 D A2P GND VCC Figure 2. Functional Block Diagram 6 7 8 9 10 /O E GND VC C SE L D A2 N Figure 3. Pin Assignments (Top Through View) Pin Descriptions Pin # Pin Name Type Description 20 CLKP I/O Common positive clock path 1 CLKN I/O Common negative clock path 2 D1P I/O Common positive data 1 path 3 D1N I/O Common negative data 1 path 4 D2P I/O Common positive data 2 path 5 D2N I/O Common negative data 2 path 15 CLKAP I/O A-port positive clock path 14 CLKAN I/O A-port negative clock path 13 DA1P I/O A-port positive data 1 path 12 DA1N I/O A-port negative data 1 path 11 DA2P I/O A-port positive data 2 path 10 DA2N I/O A-port negative data 2 path 18 CLKBP I/O B-port positive clock path 19 CLKBN I/O B-port negative clock path 16 DB1P I/O B-port positive data 1 path 17 DB1N I/O B-port negative data 1 path Output Enable (Active Low) 6 /OE Input 7 GND Ground Ground 8 VCC Supply Power; 0.1 µF decoupling capacitor to ground recommended 9 SEL Input Paddle n/a NC A-port or B-port Select pin 0=A-port, 1= B-port Not Connected Truth Table SEL /OE Function Don’t Care LOW HIGH HIGH LOW LOW Disconnect D1, D2, CLK=DA1, DA2, CLKA D1, CLK=DB1, CLKB; D2 OPEN © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 3 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration Pin Configuration Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be operable above the recommended operating conditions and stressing the parts to these levels is not recommended. In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. The absolute maximum ratings are stress ratings only. Symbol VCC VCNTRL Parameter Supply Voltage (1) DC Input Voltage (SEL, /OE) (1) VSW DC Switch I/O Voltage IIK DC Input Diode Current IOUT DC Output Current TSTG Storage Temperature ESD Min. Max. Unit -0.50 +5.25 V -0.5 VCC V -0.5 VCC + 0.3 V -50 -65 Human Body Model, JEDEC: JESD22-A114 mA 50 mA +150 °C All Pins 6.5 I/O to GND 8.0 Power to GND 16.0 Charged Device Model, JEDEC: JESD22-C101 kV 2.0 Note: 1. The input and output negative ratings may be exceeded if the input and output diode current ratings are observed. Recommended Operating Conditions The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not recommend exceeding them or designing to Absolute Maximum Ratings. Symbol VCC VCNTRL VSW TA Parameter Min. Max. 2.65 4.30 V 0 VCC V Switch I/O Voltage -0.5 VCC-1 V V Operating Temperature -40 +85 °C Supply Voltage (2) Control Input Voltage (SEL, /OE) Unit Note: 2. The control input must be held HIGH or LOW; it must not float. © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 4 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration Absolute Maximum Ratings All typical values are TA=25°C unless otherwise specified. Symbol Parameter Conditions VIK Clamp Diode Voltage IIN=-18 mA IIN Control Input Leakage VSW=0 to 4.3 V VCC (V) TA=-40 to +85ºC Min. Typ. 2.775 4.3 -1 2.650 to 2.775 1.3 4.3 1.7 VIH Input Voltage High VIN=0 to VCC VIL Input Voltage Low VIN=0 to VCC IOZ Off-State Leakage A, B=0+0.3 V to VCC-0.3 4.3 ICC Quiescent Supply Current VCNTRL=0 or VCC, IOUT=0 ICCT Increase in ICC Current Per Control Voltage and VCC VCNTRL=1.8 V Max. Units -1.2 V 1 µA V 2.650 to 2.775 0.5 V 2 µA 4.3 1.0 µA 2.775 1.5 µA -2 DC Electrical Characteristics, Low-Speed Mode All typical values are TA=25°C unless otherwise specified. Symbol RON ∆RON Parameter LS Switch On Resistance LS Delta Conditions (3) (4) RON VCC (V) TA=-40 to +85ºC Min. Typ. Max. 14 VSW=1.2 V, ION=-10 mA, Figure 4 2.65 10 VSW=1.2 V, ION=-10 mA (Intra-pair) 2.65 0.75 Units Ω Ω Notes: 3. Measured by the voltage drop between A/B and CLK/Dn pins at the indicated current through the switch. 4. Guaranteed by characterization. DC Electrical Characteristics, High-Speed Mode All typical values are TA=25°C unless otherwise specified. Symbol Parameter Conditions (5) RON HS Switch On Resistance ∆RON (6) RON HS Delta VCC (V) TA=-40 to +85ºC Min. Typ. Max. 9.5 VSW=0.4 V, ION=-10 mA, Figure 4 2.65 7.0 VSW=0.4 V, ION=-10 mA (Intra-pair) 2.65 0.75 Units Ω Ω Notes: 5. Measured by the voltage drop between A, B, and Dn pins at the indicated current through the switch. 6. Guaranteed by characterization. © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 5 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration DC Electrical Characteristics All values are at RL=50 Ω and RS=50 Ω and all typical values are VCC=2.775 V at TA=25°C unless otherwise specified. Symbol Parameter Conditions (7) OIRR Off Isolation Xtalk Non-Adjacent Channel (7) Crosstalk (7) VCC (V) Min. Typ. Max. Units f=100 MHz, RT=50 Ω Figure 14 2.775 -50 dB f=100 MHz, RT=50 Ω Figure 15 2.775 -40 dB CL=0 pF, RT=50 Ω Figure 13 2.775 1.0 GHz BW -3db Bandwidth tON Turn-On Time SEL, /OE to Output CL=5 pF, VSW=1.2 V Figure 6, Figure 7 tOFF Turn-Off Time SEL, /OE to Output CL=5 pF, VSW=1.2 V Figure 6, Figure 7 tPD Propagation Delay CL=5 pF Figure 6, Figure 8 tBBM Break-Before-Make Time CL=5 pF, VSW1=VSW2=1.2 V Figure 12 (7) TA=-40ºC to +85ºC 2.650 to 2.775 20 37 ns 2.650 to 2.775 15 27 ns 2.775 0.25 2.650 to 2.775 7 9 ns 12 ns Note: 7. Guaranteed by characterization. AC Electrical Characteristics, High-Speed All typical values are VCC=2.775 V at TA=25°C unless otherwise specified. Symbol Parameter Conditions TA=-40ºC to +85ºC Min. Typ. Max. Units tSK(Part_Part) Channel-to-Channel Skew Across (8,9) Multiple Parts TDR-Based Method (VSW -0.2VPP,CL=CON) 40 80 ps tSK(Chl_Chl) Channel-to-Channel Skew Within a (8) Single Part TDR-Based Method (VSW -0.2VPP,CL=CON) 15 30 ps tSK(Pulse) Skew of Opposite Transitions in the (8) Same Differential Channel TDR-Based Method (VSW -0.2VPP,CL=CON) 10 20 ps Notes: 8. Guaranteed by characterization. 9. Assumes the same VCC and temperature for all devices. Capacitance Symbol Parameter Conditions (10) CIN Control Pin Input Capacitance CON Dn/CLK- On Capacitance COFF Dn/CLK Off Capacitance (10) (9) TA=-40ºC to +85ºC Min. Typ. VCC=0 V 1.5 VCC=2.775 V, /OE=0V, f=1 MHz Figure 11 8.0 VCC=2.775 V, /OE=2.775 V, f=1 MHz Figure 10 2.5 Max. Units pF Note: 10. Guaranteed by characterization. © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 6 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration AC Electrical Characteristics VON I Dn(OFF) NC A DA/Bn VSW Dn VSW Select GND RON = VON / ION V Sel = GND I ON Select V Sel = GND V cc 0 orV 0 orV cc **Each switch port is tested separately Figure 4. On Resistance Figure 5. Off Leakage tFALL = 2.5ns tRISE = 2.5ns DA B Dn VCC VSW CL GND RS RL V OUT Input – V/OE , VSel GND 10% GND VSel 90% 90% VCC /2 VCC /2 10% VOH 90% GN D 90% Output- VOUT RL , RS , a n C L a r fu ct ion s o f th a p licat ion VOL env iro nme nt (s e A C Ta b le s fo r spe ific v lue s) CL inclu es test f ixtu re a n stra ca pa cita nce Figure 6. AC Test Circuit Load tON tOFF Figure 7. Turn-On / Turn-Off Waveforms 400mV 50% Input 50% 0V tPLH tPHL VOH Output 50% 50% VOL Figure 8. Propagation Delay (tRtF – 500 ps) Figure 9. Channel-to-Channel Skew DA/Bn Capacitance DA/Bn Meter S Capacitance Meter S VSEL =0 or VCC VSEL =0 or VCC DA/Bn DA/Bn Figure 10. Channel Off Capacitance Figure 11. Channel On Capacitance © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 7 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration Test Diagrams FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration Test Diagrams (Continued) tRISE= 2 .5 ns Vcc HSDn Dn VSW1 GND 1 % 0V VOUT CL VSW2 9 % Vcc /2 I np ut - VS el RL VOUT GND GND 0.9*Vo 0.9*Vo t RS t tBBM VSel RL , RS , and CL ar functions of the application environment (see AC Tables for specific values). CL includes test fixture and stray capacitance. GND Figure 12. Break-Before-Make Interval Timing Network Analyzer RS V IN VS GND GND VSel GND VOUT GND RT GND RS and RT are functions of the application environment (see AC Tables for specific values). Figure 13. Bandwidth Network Analyzer RS VSel V IN GND RT VS GND GND V OUT GND GND RT RS and RT are functions of the application environment (see AC Tables for specific values). GND Off isolation = 20 Log (V OUT / VIN) Figure 14. Channel Off Isolation Network Analyzer NC RS GND V IN VS VSel GND GND RT GND GND RS and RT are functions of the application environment (see AC Tables for specific values). RT V OUT GND Crosstalk = 20 Log (VOUT / VIN) Figure 15. Non-Adjacent Channel-to-Channel Crosstalk © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 8 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration Physical Dimensions 0.10 C 3.00 2X A 3.00 B PIN1 IDENT 1.80 3.00 3.00 1.80 0.10 C 2X 0.80 20X TOP VIEW 0.40 0.20 20X 0.08 C 0.55 MAX 0.10 C RECOMMENDED LAND PATTERN (0.15) 0.05 0.00 C SIDE VIEW SEATING PLANE NOTES: 1.75 1.65 6 A. PACKAGE CONFORMS TO JEDEC MO-248 VARIATION UEEE. 10 5 B. DIMENSIONS ARE IN MILLIMETERS. 11 C. DIMENSIONS AND TOLERANCES PER ASME Y14.5M, 1994. 0.25 20X 0.15 D. LAND PATTERN RECOMMENDATION IS FROM PCB MATRIX CALCULATOR V2009. 1.75 1.65 E. DRAWING FILENAME: MKT-UMLP20Brev1. 15 1 PIN 1 IDENT 20 16 0.40 0.45 20X 0.35 0.10 0.05 C A B C BOTTOM VIEW Figure 16. 20-Lead, Quad, Ultrathin Molded Leadless Package (UMLP), 3.0 x 3.0 mm Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/dwg/UM/UMLP20B.pdf. For current tape and reel specifications, visit Fairchild Semiconductor’s online packaging area: http://www.fairchildsemi.com/packaging/3.0x3.0_UMLP_Pack_TNR_Spec.pdf. © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 9 FSA641 — 2:1 MIPI Switch, Featuring 2-Data and 1-Data Lane Configuration © 2010 Fairchild Semiconductor Corporation FSA641 • Rev. 1.0.5 www.fairchildsemi.com 10