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FOD8012A
High CMR, Bi-Directional, Logic Gate Optocoupler
Features
Description
• Half Duplex, Bi-Directional
• 20 kV/μs Minimum Common Mode Rejection
• High Speed:
– 15 Mbit/sec Data Rate (NRZ)
– 60 ns Maximum Propagation Delay
– 15 ns Maximum Pulse Width Distortion
– 30 ns Maximum Propagation Delay Skew
• 3.3 V and 5 V CMOS Compatibility
• Extended Industrial Temperate Range, -40 to +110°C
Temperature Range
• Safety and Regulatory Approvals
– UL1577, 3750 VACRMS for 1 min.
– DIN EN/IEC60747-5-2 (approval pending)
The FOD8012A is a half duplex, bi-directional, highspeed logic gate Optocoupler, which supports isolated
communications allowing digital signals to communicate
between systems without conducting ground loops or
hazardous voltages. It utilizes Fairchild’s patented coplanar packaging technology, Optoplanar®, and optimized
IC design to achieve minimum 20 kV/μs Common Mode
Noise Rejection (CMR) rating.
Applications
• Industrial Fieldbus Communications
– DeviceNet, CAN, RS485
• Microprocessor System Interface
– SPI, I2C
• Programmable Logic Control
• Isolated Data Acquisition System
• Voltage Level Translator
This high-speed logic gate optocoupler is highly integrated with 2 optically coupled channels arranged in
bi-directional configuration, and housed in a compact
8-pin small outline package. Each optocoupler channel
consists of a high-speed AlGaAs LED driven by a CMOS
buffer IC coupled to a CMOS detector IC. The detector
IC comprises of an integrated photodiode, a high-speed
trans-impedance amplifier and a voltage comparator with
an output driver. The CMOS technology coupled to the
high efficiency of the LED achieves low power consumption as well as very high speed (60 ns propagation delay,
15 ns pulse width distortion).
Related Resources
• FOD8001, High Noise Immunity, 3.3 V/5 V Logic Gate
Optocoupler Datasheet
• www.fairchildsemi.com/products/optoelectronics/
Functional Schematic
VDD1
1
8
VDD2
Truth Table
VOA
2
7
VINA
VINB
3
6
VOB
GND1
4
5
GND2
VIN
LED
VO
High
OFF
High
Low
ON
Low
When not communicating, VIN must be
in static high logic condition.
0.1µF bypass capacitor required from VDD to GND
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
July 2015
Pin
Number
Pin
Name
1
VDD1
Supply Voltage to Channel-A detector IC and Channel-B buffer IC
2
VOA
Output Voltage from Channel-A detector IC
3
VINB
Input Voltage to Channel-B buffer IC
4
GND1
Ground for Channel-A detector IC and Channel-B buffer IC
5
GND2
Ground for Channel-A buffer IC and Channel-B detector IC
6
VOB
Output Voltage from Channel-B detector IC
7
VINA
Input Voltage to Channel-A buffer IC
8
VDD2
Supply Voltage to Channel-A buffer IC and Channel-B detector IC
Description
Absolute Maximum Ratings
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only. TA = 25°C unless otherwise specified.
Symbol
Parameter
Value
Unit
-40 to +125
°C
TSTG
Storage Temperature
TOPR
Operating Temperature
-40 to +110
°C
Junction Temperature
-40 to +130
°C
260 for 10sec
°C
TJ
TSOL
VDD1, VDD2
VIA, VIB
IIA, IIB
VOA, VOB
IOA, IOB
PDI
PDO
Lead Solder Temperature
(Refer to Reflow Temperature Profile)
Supply Voltage
Input Voltage
0 to 6.0
V
-0.5 to VDD+0.5
V
-10 to +10
μA
Input DC Current
Output Voltage
-0.5 to VDD+0.5
V
Average Output Current
10
mA
Input Power Dissipation(1)
60
mW
60
mW
Output Power
Dissipation(1)
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
TA
VDD1, VDD2
Parameter
Ambient Operating Temperature
Supply Voltages (3.3 V
Operation)(2)
(2)
Min.
Max.
Unit
-40
+110
°C
3.0
3.6
V
4.5
5.5
V
VIH
Logic High Input Voltage
2.0
VDD
V
VIL
Logic Low Input Voltage
0
0.8
V
tr, tf
Input Signal Rise and Fall Time
1.0
ms
Supply Voltages (5.0 V Operation)
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
2
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Pin Definitions
Apply over all recommended conditions, typical value is measured at TA = 25°C
Symbol
Parameter
Conditions
VISO
Input-Output Isolation Voltage
freq = 60 Hz, t = 1.0 min,
II-O ≤ 10 μA(3)(4)
RISO
Isolation Resistance
VI-O = 500 V(3)
CISO
Isolation Capacitance
VI-O = 0 V, freq = 1.0 MHz
Min.
Typ.
Max.
3750
VacRMS
1011
(3)
Unit
Ω
0.2
pF
Electrical Characteristics
TA = -40°C to +110°C, 3.0 V ≤ VDD ≤ 5.5 V, unless otherwise specified.
Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3 V, TA = 25°C
Symbol
Parameter
Conditions
Min.
IDD1L, IDD2L Logic Low Supply Current VIA, VIB = 0 V
IDD1H, IDD2H Logic High Supply Current VIA, VIB = VDD
IIA, IIB
VOH
VOL
Input Current
Logic High Output Voltage
Logic Low Output Voltage
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
Typ.
Max.
Unit
5.8
8.0
mA
2.5
4.0
mA
+10
μA
-10
IO = –20 μA, VDD = 3.3 V, VI = VIH
3.2
3.3
V
IO = –4 mA, VDD = 3.3 V, VI = VIH
3.0
3.1
V
IO = –20 μA, VDD = 5 V, VI = VIH
4.9
5.0
V
IO = –4 mA, VDD = 5 V, VI = VIH
4.7
4.8
V
IO = 20 μA, VDD = 3.3 V or 5 V,
VI = VIL
0
0.1
V
IO = 4 mA, VDD = 3.3 V or 5 V,
VI = VIL
0.26
0.6
V
www.fairchildsemi.com
3
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Isolation Characteristics
TA = -40°C to +110°C, 3.0 V ≤ VDD ≤ 5.5 V, unless otherwise specified.
Apply over all recommended conditions, typical value is measured at VDD1 = VDD2 = +3.3 V, TA=25°C
Symbol
Parameter
Conditions
Min.
Typ.
Data Rate
Max.
Unit
15
Mbit/s
tPHL
Propagation Delay Time
to Logic Low Output
PW = 66.7 ns, CL = 15 pF
37
60
ns
tPLH
Propagation Delay Time
to Logic High Output
PW = 66.7 ns, CL = 15 pF
40
60
ns
PWD
Pulse Width Distortion,
| tPHL – tPLH |
PW = 66.7 ns, CL = 15 pF(5)
3
15
ns
tPSK(CC)
Channel-Channel Skew
PW = 66.7 ns, CL = 15 pF(6)
12
25
ns
tPSK(PP)
Part-Part Skew
PW = 66.7 ns, CL = 15 pF(7)
30
ns
tR
Output Rise Time
(10% to 90%)
PW = 66.7 ns, CL = 15 pF
6.5
ns
tF
Output Fall Time
(90% to 10%)
PW = 66.7 ns, CL = 15 pF
6.5
ns
|CMH|
Common Mode Transient
Immunity at Output High
VI = VDD1, VO > 0.8 VDD1,
VCM = 1000 V(8)
20
40
kV/μs
|CML|
Common Mode Transient
Immunity at Output Low
VI = 0 V, VO < 0.8 V,
VCM = 1000 V(8)
20
40
kV/μs
Notes:
1. No derating required.
2. 0.1 μF bypass capacitor must be connected between Pin 1 and 4, and 5 and 8. The capacitors should be kept close
to the supply pins.
3. Device is considered a two terminal device: Pins 1, 2, 3 and 4 are shorted together and Pins 5, 6, 7 and 8 are shorted
together.
4. 3,750 VACRMS for 1 minute duration is equivalent to 4,500 VACRMS for 1 second duration.
5. PWD is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen for one channel
switching, while holding the other channel output at a low or high state, or while both channels are in synchronous
data transmission mode.
6. tPSK(CC) is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between the two
channels within a single device.
7. tPSK(PP) is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between any two
units from the same manufacturing date code that are operated at same case temperature, at same operating
conditions, with equal loads.
8. Common mode transient immunity at output high is the maximum tolerable positive dVcm/dt on the leading edge of
the common mode impulse signal, Vcm, to assure that the output will remain high. Common mode transient
immunity at output low is the maximum tolerable negative dVcm/dt on the trailing edge of the common pulse signal,
Vcm, to assure that the output will remain low.
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
4
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Switching Characteristics
4.0
2.0
VITH – INPUT VOLTAGE SWITCHING
THRESHOLD (V)
VO – OUTPUT VOLTAGE (V)
VDD1 = VDD1 = 3.3V
3.0
2.0
1.0
0
0
1
2
3
4
1.6
1.4
1.2
1.0
3.0
5
3.5
4.0
4.5
5.0
5.5
VI – INPUT VOLTAGE (V)
VDD – SUPPLY VOLTAGE (V)
Fig. 1 Typical Output Voltage vs. Input Voltage
(Channel A & B)
Fig. 2 Typical Input Voltage Switching Threshold
vs. Input Supply Voltage (Channel A & B)
54
2
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
50
1
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
0
46
tPHL – tPLH (ns)
tP – PROPAGATION DELAY (ns)
1.8
42
tPLH
38
-1
-2
-3
tPHL
-4
34
-5
30
-40
-20
0
20
40
60
80
-6
-40
100 110
-20
TA – AMBIENT TEMPERATURE (°C)
20
40
60
80
100 110
Fig. 4 Typical tPHL – tPLH vs. Ambient Temperature
(Channel A & B)
Fig. 3 Typical Propagation Delay vs.
Ambient Temperature (Channel A & B)
7.0
6.5
0
TA – AMBIENT TEMPERATURE (°C)
9.0
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
8.5
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
tF – FALL TIME (ns)
tR – RISE TIME (ns)
8.0
6.0
tR
5.5
5.0
7.5
7.0
tF
6.5
6.0
4.5
5.5
4.0
-40
-20
0
20
40
60
80
5.0
-40
100 110
TA – AMBIENT TEMPERATURE (°C)
0
20
40
60
80
100 110
TA – AMBIENT TEMPERATURE (°C)
Fig. 6 Typical Fall Time vs. Ambient Temperature
(Channel A & B)
Fig. 5 Typical Rise Time vs. Ambient Temperature
(Channel A & B)
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
-20
www.fairchildsemi.com
5
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Typical Performance Curves
45
0
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
43
-1
tPLH
41
tPHL – tPLH (ns)
tP – PROPAGATION DELAY (ns)
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
tPHL
39
-2
-3
37
-4
35
15
20
25
30
35
40
45
50
-5
15
55
CL – OUTPUT LOAD CAPACITANCE (pF)
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
Fig. 7 Typical Propagation Delay vs. Output Load
Capacitance (Channel A & B)
Fig. 8 Typical tPHL – tPLH vs. Output Load Capacitance
(Channel A & B)
12
16
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
14
tF – FALL TIME (ns)
10
tR – RISE TIME (ns)
20
8
tR
6
Frequency = 7.5MHz
Duty Cycle = 50%
VDD1 = VDD2 = 3.3V
12
tF
10
8
4
6
2
15
20
25
30
35
40
45
50
4
15
55
20
25
30
35
40
45
50
55
CL – OUTPUT LOAD CAPACITANCE (pF)
CL – OUTPUT LOAD CAPACITANCE (pF)
Fig. 9 Typical Rise Time vs. Output Load Capacitance
(Channel A & B)
Fig. 10 Typical Fall Time vs. Output Load Capacitance
(Channel A & B)
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
6
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Typical Performance Curves (Continued)
7.5
VDD1 = VDD2 = 5.5V, TA = 25°C
VINA and VINB Switching
Pin 2 and 6 Floating
7.0
IDD1 / IDD2 – INPUT SUPPLY CURRENT (mA)
IDD1 / IDD2 – INPUT SUPPLY CURRENT (mA)
7.5
TA = -40°C
6.5
TA = 25°C
6.0
5.5
5.0
TA = 110°C
4.5
VDD1 = VDD2 = 5.5V, TA = 25°C
VINB = 0V @ IDD1, VINA Switching
VINA = 0V @ IDD2, VINB Switching
Pin 2 and 6 Floating
7.0
TA = 25°C
6.5
6.0
TA = 110°C
5.5
TA = -40°C
5.0
4.5
4.0
4.0
0
2,000
4,000
6,000
8,000
10,000
12,000
14,000
0
2,000
4,000
6,000
8,000
10,000
12,000
14,000
F – FREQUENCY (kHz)
F – FREQUENCY (kHz)
Fig. 11a Typical IDD1/IDD2 Supply Current vs. Frequency
Fig. 11b Typical IDD1/IDD2 Supply Current vs. Frequency
IDD1 / IDD2 – INPUT SUPPLY CURRENT (mA)
7.5
VDD1 = VDD2 = 5.5V, TA = 25°C
VINA = 0V @ IDD1, VINB Switching
VINB = 0V @ IDD2, VINA Switching
Pin 2 and 6 Floating
7.0
6.5
6.0
TA = 25°C
TA = -40°C
5.5
5.0
TA = 110°C
4.5
4.0
0
2,000
4,000
6,000
8,000
10,000
12,000
14,000
F – FREQUENCY (kHz)
Fig. 11c Typical IDD1/IDD2 Supply Current vs. Frequency
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
7
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Typical Performance Curves (Continued)
1
8
2
7
VOA
VDD2
0.1μF
0.1μF
CL
0V~3.3V
VOB
3
6
4
5
VDD1
tPLH
tPHL
3.3V
Input
50%
VIN
VOH
90%
Output
50%
VOUT 10%
VOL
tR
tF
Figure 12. Test Circuit for Propagation Delay Time and Rise Time, Fall Time
1
8
2
7
VOA
A
0.1μF
0.1μF
CL
3
6
4
5
VDD2
B
VDD1
–
+
Vcm
Pulse Gen
VCM
GND
VOH
Switching Pos. (A), VIN = 3.3V
CMH
0.8 x VDD
0.8V
VOL
Switching Pos. (B), VIN = 0V
CML
Figure 13. Test Circuit for Instantaneous Common Mode Rejection Voltage
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
8
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Test Circuits
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Small Outline Package Dimensions
Figure 14. 8-Lead, SOIC, Small Outline 8-pin
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
9
8.0 ± 0.10
3.50 ± 0.20
2.0 ± 0.05
0.30 MAX
Ø1.5 MIN
4.0 ± 0.10
1.75 ± 0.10
5.5 ± 0.05
12.0 ± 0.3
8.3 ± 0.10
5.20 ± 0.20
Ø1.5 ± 0.1/-0
6.40 ± 0.20
0.1 MAX
User Direction of Feed
Note:
All dimensions are in millimeters.
Ordering Information
Option
Order Entry Identifier
Description
No Suffix
FOD8012A
Small outline 8-pin, shipped in tubes (50 units per tube)
R2
FOD8012AR2
Small outline 8-pin, tape and reel (2,500 units per reel)
All packages are lead free per JEDEC: J-STD-020B standard.
Marking Information
1
8012A
X YY S1
3
2
5
4
Definitions
1
Fairchild logo
2
Device number
3
One digit year code, e.g., ‘8’
4
Two digit work week ranging from ‘01’ to ‘53’
5
Assembly package code
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
www.fairchildsemi.com
10
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Carrier Tape Specification
FOD8012A — High CMR, Bi-Directional, Logic Gate Optocoupler
Reflow Profile
260 T
P
245
240
220 TL
Temperature (°C)
200
Max. Ramp-up Rate = 3°C/S
Max. Ramp-down Rate = 6°C/S
tP
Tsmax
tL
180
160
Tsmin
140
ts
120
100
80
60
40
20
0
240
120
360
Time 25°C to Peak
Time (seconds)
Profile Freature
Pb-Free Assembly Profile
Temperature Min. (Tsmin)
150°C
Temperature Max. (Tsmax)
200°C
Time (tS) from (Tsmin to Tsmax)
60–120 seconds
Ramp-up Rate (tL to tP)
3°C/second max.
Liquidous Temperature (TL)
217°C
Time (tL) Maintained Above (TL)
60–150 seconds
Peak Body Package Temperature
245°C +0°C / –5°C
Time (tP) within 5°C of 245°C
30 seconds
Ramp-down Rate (TP to TL)
6°C/second max.
Time 25°C to Peak Temperature
©2015 Fairchild Semiconductor Corporation
FOD8012A Rev. 1.0
8 minutes max.
www.fairchildsemi.com
11
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PRODUCT STATUS DEFINITIONS
Definition of Terms
Datasheet Identification
Product Status
Advance Information
Formative / In Design
Preliminary
First Production
No Identification Needed
Full Production
Obsolete
Not In Production
Definition
Datasheet contains the design specifications for product development. Specifications may change
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Datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild
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