www.fairchildsemi.com AN-9080 Motion SPM® 5 Series Version 2 User’s Guide Table of Contents 1. Introduction ............................................................. 2 5. New Key Parameter Design Guidance...................13 1.1 About this Application Note ......................... 2 5.1 Thermal Sensing Unit (TSU) ......................13 1.2 Design Concept ............................................. 2 5.2 Bootstrap Circuit Design .............................14 1.3 Features ......................................................... 2 5.3 Minimum Pulse Width ................................17 2. Product Selections ................................................... 3 5.4 Short Circuit SOA .......................................17 2.1 Ordering Information .................................... 3 6. Application Example .............................................18 2.2 Product Line-up ............................................ 3 6.1 General Application Circuit Examples........18 2.3 SPM5 Version Comparison .......................... 3 6.2 Recommended Wiring of Shunt Resistor ....19 3. Package .................................................................... 4 6.3 Snubber Capacitor .......................................19 3.1 Internal Circuit Diagram ............................... 4 6.4 PCB Layout Guidance .................................19 3.2 Pin Description ............................................. 4 6.5 Heatsink Mounting ......................................20 3.3 Package Structure ......................................... 5 6.6 System Performance....................................21 3.4 Package Outline ............................................ 6 7. Handling Guide and Packing Information .............22 3.5 Marking Specification................................... 7 7.1 Handling Precaution ....................................22 4. Integrated Functions and Protection Circuit .......... 11 7.2 Packing Specification ..................................23 4.1 Internal Structure of HVIC ......................... 11 8. Related Resources ..................................................28 4.2 Circuit of Input Signal (VIN(H), VIN(L)) ......... 11 4.3 Functions vs. Control Supply Voltage ........ 11 4.4 Under-Voltage Protection ........................... 12 © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com AN-9080 1. APPLICATION NOTE Introduction 1.1. About this Application Note 1.3. Features This application note is about Motion SPM® 5 Series Version 2 products. It should be used in conjunction with the datasheet, reference designs, and related application notes listed in Related Resources. This note focuses on the difference between Version 2 and the previous versions of SPM parts, with emphasis on new IC functions The detailed features and integrated functions are: Variety of products with different voltage and power ratings: 250/500/600 V 3-phase FRFET inverter ,including HVICs Three divided negative DC-link terminals for leg current sensing 1.2. Design Concept HVIC for gate driving of FRFET, under-voltage protection, and thermal sensing functions The key design objective of the SPM 5 series is to provide a compact and reliable inverter solution for small power motor drive applications. Ongoing efforts have improved the performance, quality, and power rating of SPM 5 series products and the Version 2 products are the latest results of these enhancements. The new features include temperaturesensing capability, built-in bootstrap diodes, and upgraded ruggedness. Two higher power rating devices based on super-junction MOSFET technology are added to cover higher power rating applications without significantly increasing cost. 3.3/5 V Schmitt trigger input with active HIGH logic Built-in bootstrap diodes Single-grounded power supply and optocoupler-less interface due to built-in HVIC Minimized standby current of HVIC for energy regulation Packages; DIP, SMD, Double-DIP, Zigzag-DIP Isolation voltage rating of 1500 VRMS for 1 minute The MOSFETs in SPM 5 series are specially processed to reduce the amount of body-diode reverse recovery charge to minimize the switching loss and enable fast switching operations. Softness of the reverse-recovery characteristics is managed through advanced MOSFET design with optimized gate resistor selections to contain Electromagnetic Interference (EMI) noise within a reasonable range. Moisture Sensitive Level 3 (MSL3) for SMD package SPM 5 series has six fast-recovery MOSFETs (FRFET®) and three high-voltage half-bridge gate drive ICs. These MOSFETs and HVICs are not available as discrete parts. An FRFET-based power module has much better ruggedness and a larger safe operation area (SOA) than IGBT-based module or Silicon-On-Insulator modules. The FRFET-based power module has a big advantage in light-load efficiency over IGBT-based because the voltage drop across the transistor decreases linearly as current decrease, whereas IGBT Vce saturation voltage stays at the threshold level. Some applications require continuous operation at light load except short transients and improving the efficiency in the light-load condition is the key to saving energy. Refrigerators, water circulation pumps, and some fans are good examples. The temperature-sensing function of version 2 products is implemented in the HVIC to enhance system reliability. An analog voltage proportional to the temperature of the HVIC is provided for monitoring the module temperature and necessary protections against over-temperature situations. Three internal bootstrap diodes with resistive characteristics reduce the number of external components and make the PCB design more compact, beneficial when designing an inverter built inside the motor. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 2 AN-9080 2. APPLICATION NOTE Product Selections 2.1. Ordering Information Fairchild’s online loss and temperature simulation tool, Motion Control Design Tool, available at: (http://www.fairchildsemi.com/support/design-tools/motioncontrol-design-tool/), is recommended to select the best SPM product by power rating for the desired application. FSB50250XX(D) BSD in Ver.1 & 1.5 Package blank : W/O BSD D : With BSD blank : DIP S : SMD T : Double DIP B : Zigzag DIP 2.3. SPM 5 Version Comparison blank : Ver.1 Version U : Ver.1.5 A : Ver.2 SF : Ver.2 with SuperFET2 As can be seen from Table 2, version s “V2” products have at least the same or lower RDS_max compared with the predecessors; lower RDS_max values than older version are in red. Old version products were not released at the same time, and, therefore, there are differences even within the same version products. V2 products are being released at the same time with consistent features. V2 products are more rugged than previous versions in many respects. Voltage Rating ( x 10 ) Comparative Current Rating ( Not in Amps ) Motion SPM® 5 Series Figure 1. Ordering Information 2.2. Product Line-up Table 1 shows the basic line up without package variations. VCC-COM and VB-VS surge noise immunity level increased about 50%. In other words, when a singlesurge pulse comes in between these pins, V2 products endure 50% higher surge voltage without malfunction. Destruction level against surge pulses consecutively coming in between Vb and VS improved significantly. Problems associated with intermittent latch-on/off due to manufacturing issue have been resolved. Previous version products have been updated accordingly. VCC quiescent current increased due to the TSU function. It does not have much effect on selecting the bootstrap capacitor value, but stand-by power is increased by about 2.1 mW. There is no change in quiescent current of VBS. Table 1. Product Offerings Current Rating Part Number BVDSS FSB50325A 250 0.90 1.70 1.10 1.70 10.2 FSB50825A 250 1.90 3.60 0.33 0.45 8.8 FSB50250A 500 0.60 1.20 2.50 3.80 9.3 FSB50450A 500 0.80 1.50 1.90 2.40 8.9 FSB50550A 500 1.10 2.00 1.00 1.40 8.6 FSB50660SF 600 1.60 3.10 0.60 0.70 8.8 FSB50760SF 600 1.90 3.60 0.46 0.53 8.6 IDRMS ID25 RƟJC RDS(on) RDS(on) (Max.) (Typ.) (Max.) Table 2. SPM 5 Version Comparison Silicon Technology 60 V 250 V Line-Up & RDS(on)max 500 V V1 V1.5 V2 CFET UniFET™ UniFET™ / SuperFET® 2 FSB52006: 80 mΩ Max. FSB50325: 1.8 Ω Max. FSB50325A: 1.7 Ω Max. FSB50825U: 0.45 Ω Max. FSB50825A: 0.45 Ω Max. FSB50250: 4.0 Ω Max. FSB50250U: 4.2 Ω Max. FSB50250A: 3.8 Ω Max. FSB50450: 2.4 Ω Max. FSB50450U: 2.4 Ω Max. FSB50450A: 2.4 Ω Max. FSB50550: 1.7 Ω Max. FSB50550U: 1.4 Ω Max. FSB50550A: 1.4 Ω Max. FSB50660SF: 0.7 Ω Max. 600 V FSB50760SF: 0.53 Ω Max. Package Transfer molded package without substrate VS-Output Out-Bonding, except 50325TD Out-Bonding except TD-Version Inner Bonding Bootstrap Diode Not included except 50325TD Not included except D-Version Included UV Protection Available Available Available Thermal Sensing Not available Not available Available © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 3 AN-9080 3. APPLICATION NOTE Package 3.1. Internal Circuit Diagram Table 3. Pin Descriptions Major differences between Version 2 and previous versions are red in the internal circuit diagram in Figure 2. Though some old versions also have these features, Version 2 widely adopts these features. Main differences are Vts, internal connections between VS and sources of high-side FRFETs, and internal bootstrap diodes. The Vts pin is from V-phase HVIC only and sends out the temperature sensing signal. Pin # Name 1 2 3 (1) COM (2) VB(U) (17) P (3) VCC(U) VCC VB (4) IN (UH) HIN HO (5) IN (UL) LIN VS COM LO (8) VCC(V) VCC VB (9) IN (VH) HIN HO LIN VS COM LO (10) IN (VL) (11) Vts VCC VB HIN HO LIN VS COM LO (15) IN (WL) IN(UH) Input for U-phase high-side gate signal 5 IN(UL) Input for U-phase low-side gate signal 6 NC No connection Bias voltage for V-phase high-side MOSFET driving Bias voltage for V-phase IC and low-side VCC(V) MOSFET driving 8 (20) N V 9 IN(VH) Input for V-phase high-side gate signal 10 IN(VL) Input for V-phase low-side gate signal 11 VTS 12 VB(W) 13 VCC(W) 14 IN(WH) Input for W-phase high-side gate signal 15 IN(WL) Input for W-phase low-side gate signal 16 NC 17 P 18 U, VS(U) 19 NU Source of U-phase low-side MOSFET 20 NV Source of V-phase low-side MOSFET 21 V, VS(V) Output for V-phase and bias voltage ground for high-side MOSFET driving 22 NW Source of W-phase low-side MOSFET 23 W, VS(W) Output for W-phase and bias voltage ground for high-side MOSFET driving (21) V, VS(V) (22) N W (23) W, V S(W) (16) N.C Figure 2. Internal Circuit Diagram of Motion SPM 5 Series Version 2 Products 3.2. 4 (19) N U (12) V B(W) (13) V CC(W) Bias voltage for U-phase high-side MOSFET driving Bias voltage for U-phase IC and low-side VCC(U) MOSFET driving VB(U) 7 Vts (14) IN (WH) IC common supply ground (18) U, VS(U) (6) N.C (7) VB(V) COM Pin Description Pin Description Figure 3 shows the locations of pins and the names of double-DIP package. Note that Vb pins have longer leads to accommodate further creepage distance on the PCB. Figure 4 in the later section illustrates the internal layout of the module in more detail. VB(V) Analog voltage output proportional to IC temperature Bias voltage for W-phase high-side MOSFET driving Bias voltage for W-phase IC and low-side MOSFET driving No connection Positive DC-link input Output for U-phase and bias voltage ground for high-side FET driving High-Side Bias Voltage Pins for Driving the HighSide MOSFET / High-Side Bias Voltage Ground Pins for Driving the High-Side MOSFET Pins: VB(U) – U,VS(U), VB(V) – V, VS(V), VB(W) – W, VS(W) Figure 3. Pin Numbers and Names © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 These are drive power supply pins for providing gate drive power to the high-side MOSFETs. The advantage of the bootstrap scheme is that no separate external power supplies are required to drive the high-side MOSFETs. Each bootstrap capacitor is generally charged from the VCC supply during the on-state of the corresponding low-side MOSFET. www.fairchildsemi.com 4 AN-9080 APPLICATION NOTE To prevent malfunctions caused by noise and ripple in supply voltage, a good quality filter capacitor with low Equivalent Series Resistance (ESR) and Equivalent Series Inductance (ESL) should be mounted very close to these pins. Positive DC-Link Pin Pin: P Low-Side Bias Voltage Pin / High-Side Bias Voltage Pin Pin: VCC(U), VCC(V), VCC(W) These are control supply pins for the built-in ICs. These three pins should be connected externally. To prevent malfunctions caused by noise and ripple in the supply voltage, a good quality filter capacitor with low ESR and ESL should be mounted very close between these pins and the COM pins. Negative DC-Link Pins Pins: NU, NV, NW Low-Side Common Supply Ground Pin Pin: COM The common (COM) pin connects to the control ground for the internal ICs. Important! To prevent switching noises caused by parasitic inductance from interfering with operations of the module, the main power current should not flow through this pin. These are DC-link negative power supply pins (power ground) of the inverter. These pins are connected to the source of low-side MOSFET in each phase. Inverter Power Output Pin Pins: U, V, W Signal Input Pins Pins: IN(UL), IN(VL), IN(WL), IN(UH), IN(VH), IN(WH) This is a DC-link positive power supply pin of the inverter. This pin is internally connected to the drains of the high-side MOSFETs. To suppress the surge voltage caused by the DC-link wiring or PCB pattern inductance, connect a smoothing filter capacitor close to this pin and the negative DClink. Figure 35 shows more details. Typically metal film capacitors are recommended. Inverter output pins to be connected to the inverter load, such as an electrical motor. 3.3. Package Structure Figure 4 shows the internal package structure, including the lead frame and bonding wires. This design has been revised several times to further improve the manufacturability and the reliability for customers. These pins control the operation of the MOSFETs. These pins are activated by voltage input signals. The terminals are internally connected to the Schmitt trigger circuit. The signal logic of these pins is active HIGH; the MOSFET turns ON when sufficient logic voltage is applied to the associated input pin. The wiring of each input needs to be short to protect the module against noise influences. An RC filter can be used to mitigate signal oscillations or any noise that traces of input signals may pick up. Analog Temperature Sensing Output Pin Pin: Vts This indicates the temperature of the V-phase HVIC with analog voltage. HVIC itself creates some power loss, but mainly heat generated from the MOSFETs increases the temperature of the HVIC. Vts versus temperature characteristics is illustrated in Figure 16. Figure 4. Package Structure © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 5 AN-9080 APPLICATION NOTE 3.4. Packages Figure 7. Double DIP 1 Package Figure 5. DIP Package Figure 6. SMD Package Figure 8. Zigzag DIP Package Notes: 1. For more detail regarding the package dimension and land pattern recommendation, please refer to each datasheet. 2. Zigzag DIP package is only available for custom products. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 6 AN-9080 APPLICATION NOTE 3.5. Marking Specifications Figure 9. Marking of DIP Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 7 AN-9080 APPLICATION NOTE Figure 10. Marking of SMD Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 8 AN-9080 APPLICATION NOTE Figure 11. Marking of Double-DIP Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 9 AN-9080 APPLICATION NOTE Figure 12. Marking of Zigzag DIP Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 10 AN-9080 4. APPLICATION NOTE Integrated Functions and Protection Circuit control supply and the input signal during power supply startup or shutdown. In addition, pull-down resistors are built into each input circuit. Therefore, external pull-down resistors are not typically needed and the number of external components is smaller as a result. The input noise filter inside the HVIC suppresses short pulse noise and prevents the MOSFET from malfunction and excessive switching loss. Furthermore, by lowering the turn-on and turn-off threshold voltages of the input signal, as shown in Table 5, a direct connection to 3.3 V-class MCU or DSP is possible. 4.1. Internal Structure of HVIC HVIC of Motion SPM® 5 Series Version 2 Products Input Noise Filter HIN Level-Shift Circuit Common Mode Noise Canceller Gate Driver w/ Gate Resistors HO Gate Driver w/ Gate Resistors LO 500k(typ) Input Noise Filter LIN 500k(typ) Matching Delay 90ns(typ) Table 5. Input Threshold Voltage Ratings (at VCC=15 V, TJ=25°C) Figure 13. Internal Block Diagram of HVIC Figure 13 shows the block diagram of the internal structure of the HVIC inside Motion SPM 5 Series V2 products. Gate signal input pins have internal 500 kΩ (typical) pull-down resistors. The weak pull-down reduces standby power consumption. If there is any concern for malfunction due to noise associated with layout, additional pull-down resistors of 4.7 kΩ, for example, are recommended close to the module input pins. RC filters can be used instead of pulldowns to reduce noise and narrow pulses as well. Keep in mind that this filter introduces some distortion of PWM volt-second because the ON/OFF threshold levels are not symmetrical within the supplied voltage. Figure 14 shows an example of PWM input interface circuit from the microcontroller (MCU) to Motion SPM 5 Series products. The input logic is active HIGH and, because there are built-in pull-down resistors of 500 kΩ, external pulldown resistors are not typically needed. IN(UL), IN(VL), IN(WL) SPM CF COM The maximum rating voltages of the input pins are shown in Table 4. The RC coupling at each input shown dotted in Figure 14 may change depending on the PWM control scheme used in the application and the wiring impedance of the application PCB layout. Table 4. Maximum Ratings of Input Pins Condition Rating (V) Control Supply Voltage VCC Applied between VCC – COM 20 Input Signal Voltage VIN Applied between IN(xH) – COM, -0.3 ~ VCC + 0.3 IN(xL) – COM VIH 2.9 V Off Threshold Voltage VIL IN(UH), IN(VH), IN(WH) – COM IN(UL), IN(VL), IN(WL) - COM 0.8 V It is very important that all control circuits and power supplies should be referred to COM terminal of the module and not to the N power terminal. In general, it is best practice to make the common reference (COM) a ground plane in the PCB layout. The main control power supply is also connected to the bootstrap circuits that are used to establish the floating supplies for the high-side gate drives. When control supply voltage (VCC and VBS) falls below Under-Voltage Lockout (UVLO) level, HVIC turns off the MOSFETs while disregarding gate control input signals. Motion SPM 5 Series products employ active-HIGH input logic. This removes the sequence restriction between the © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 On Threshold Voltage High-frequency noise on the supply might cause the internal control IC to malfunction and generate erroneous signals. To avoid these problems, the maximum ripple on the supply should be less than ±1 V/µs. In addition, it may be necessary to connect a 20 V/1 W Zener diode (for example, 1N4747A) across the control supply to prevent surge destruction under severe conditions. Figure 14. Recommended MCU I/O Interface Circuit Symbol Min. Max. Control and gate drive power for SPM 5 Series V2 products is normally provided by a single 15 V DC supply connected to the module VCC and COM terminals. For proper operation, this voltage should be regulated to 15 V 10% and its current supply should be larger than 260 µA for SPM product, excluding other circuitry. Table 6 describes the behavior of the SPM parts for various control supply voltages. The control supply should be well filtered with a low impedance electrolytic capacitor and a high-frequency decoupling capacitor connected right at the pins. RF Item Condition 4.3. Functions vs. Control Supply Voltage IN(UH), IN(VH), IN(WH) RPD Symbol As shown in Figure 13, the input signal integrates a 500 kΩ (typical) pull-down resistor. Therefore, when using an external filtering resistor between the MCU output and the Motion SPM® input, attention should be paid to the signal voltage drop at the input terminals to satisfy the turn-on threshold voltage requirement. For instance, R=100 Ω and C=1 nF can be used for the parts shown dotted in Figure 14. 4.2. Circuit of Input Signal (VIN(H), VIN(L)) MCU Item www.fairchildsemi.com 11 AN-9080 APPLICATION NOTE Table 6. Control Voltage Range vs. Operations Control Voltage Range [V] Function Operations 0~4 Control IC does not operate. UVLO and fault output do not operate. dv/dt noise on the main P-N supply might trigger the MOSFETs. 4 ~ 10 Control IC starts to operate. As the UVLO is set, gates of MOSFETs are pulled down regardless of control input signals. 10 ~ 13.5 4.4. Under-Voltage Lockout (UVLO) The half-bridge HVIC has under-voltage lockout function to protect MOSFETs from operation with insufficient gate driving voltage. A timing chart for this protection is shown in Figure 15. Input Signal UV Protection Status Over 20 SET RESET a6 a5 a1 High-side Supply, Vbs UVBSD a2 UVLO is cleared. MOSFETs operate in accordance with the control gate input. Because driving voltage is below the recommended range, RDS(on) and the switching loss is higher than under normal conditions. a3 a4 MOSFET Current [High Side] Input Signal 13.5 ~ 16.5 for VCC Normal operation. This is the 13.5 ~ 16.5 for VBS recommended operating condition. 16.5 ~ 20 for VCC 16.5 ~ 20 for VBS RESET UVBSR UV Protection Status RESET SET RESET b6 UVCCR MOSFETs still operate. Because driving voltage is above the recommended range, MOSFETs switch faster and system noise may increase. The peak of short-circuit current may increase as well. Low-side Supply, Vcc b5 b1 UVCCD b2 b3 b4 MOSFET Current [Low Side] Figure 15. Timing Chart of Under-Voltage Protection Control circuit in the module might be damaged. a1: Control supply voltage rises: After the voltage reaches UVBSR, the circuit starts to operate when next input comes in. a2: Normal operation: MOSFET turns on and carries current. a3: Under-voltage detection (UVBSD). a4: MOSFET turns off regardless of control input condition, but there is no fault output signal because the SPM 5 series does not have an FO pin. a5: Under-voltage lockout cleared (UVBSR). a6: Normal operation: MOSFET turns on and carries current. b1: Control supply voltage rises: After the voltage rises UVCCR, the circuit starts to operate immediately. b2: Normal operation: MOSFET turns on and carries current. b3: Under-voltage detection (UVCCD). b4: MOSFET turns off regardless of control input condition, but there is no fault output signal because SPM 5 series does not have FO pin. b5: Under-voltage lockout cleared (UVCCR). b6: Normal operation: MOSFET turns on and carries current. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 12 AN-9080 5. APPLICATION NOTE New Parameter Design Guidance As temperature decreases further below 0ºC, Vts decreases linearly until it reaches zero volts. If the temperature of HVIC increases above 150ºC, which is above the maximum operating temperature, Vts increases (theoretically) up to 5.2 V until it gets clamped by the internal Zener diode. 5.1. Thermal Sensing Unit (TSU) The junction temperature of power devices should not exceed the maximum junction temperature. Even though there is some margin between the Tjmax specified on the datasheet and the Tjmax at which power devices are destroyed, attention should be paid to ensure the junction temperature stays well below the Tjmax. One of the inconveniences in using previous versions of SPM 5 Series products was lack of temperature monitoring or protection feature inside the module. An NTC had to be mounted on the heat sink or very close to the module if over-temperature protection was required in the application. Figure 17 shows the equivalent circuit diagram of TSU inside the IC and a typical application diagram. This output voltage is clamped to 5.2 V by an internal Zener diode, but if the maximum input range of analog-to-digital converter of MCU is below 5.2 V, an external Zener diode should be inserted between an A/D input pin and the analog ground pin of MCU. An amplifier can be used to change the range of voltage input to the analog-to-digital converter to have better resolution of the temperature. It is recommended to add a ceramic capacitor of 1000 pF between VTS and COM (ground) to make the Vts more stable. If VCC is not supplied for any reason, Vts is longer available. Thermal Sensing Unit (TSU) uses the technology based on the temperature dependency of transistor Vbe; Vbe decreases 2 mV as temperature increases 1ºC. The TSU analog voltage output reflects the temperature of the HVIC in Motion SPM 5 Series products. The relationship between Vts output and HVIC temperature is shown in Figure 16. It does not have any self-protection function and, therefore, it should be used appropriately based on application requirement. Note that there is a time lag from MOSFET temperature to HVIC temperature. It is very difficult to respond quickly when temperature rises sharply in a transient condition, such as load step changes. Even though TSU has limitations, it is definitely useful in enhancing the system reliability. VCC SPM 5 Series Vdd VCC MCU Temperature Sensing Voltage 2.5Kohm 2.5Kohm VTS A/D 100Kohm 5.2V COM COM Figure 17. Internal Block Diagram, TSU Interface Circuit Figure 18 shows the sourcing capability of VTS pin at 25 ºC and the test method. VTS voltage decreases as the sourcing current increases. Therefore, the load connected to VTS pin should be minimized to maintain the accurate voltage output level without degradation. Test Methods Figure 16. Temperature vs. Vts The relationship between Vts and V-phase HVIC temperature can be expressed as the following equation: VTS [V] = 0.0192*THVIC [ºC] + 0.31 ±0.19 (1) The maximum variation of Vts due to process variation is ±0.19 V, which is equivalent ±10ºC. This amount is constant, regardless of the temperature because the slopes of three lines in Figure 16 are identical. If the ambient temperature information is available, for example, through NTC in the system, Vts can be measured to adjust the offset before the motor starts to operate. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 Test Result Figure 18. Load Variation of Vts www.fairchildsemi.com 13 AN-9080 APPLICATION NOTE Figure 19 shows that the V-phase HVIC temperature inferred from VTS follows closely the case temperature, TC, with some lag. The amount of loss in a single MOSFET in a given operating condition can be calculated by Fairchild’s online loss and temperature simulation tool, available at: http://www.fairchildsemi.com/support/design-tools/motioncontrol-design-tool/. By using the loss from this simulation and the thermal resistance value on the datasheet, together with TSU, the junction temperature can be estimated and controlled to stay below the target junction temperature. Conditions: VDC=300V, VCC=15V, FSW=16.6kHz, Fan Motor Load 150 TC 140 VTS Set Thermal Shutdown 3.2 5V 3.0 Reset Thermal Shutdown VO 2.8 130 VTS 2.6 o Hysteresis : 38.6 C 2.4 120 2.2 110 TC : 138.1 C 100 VTS : 2.728 V (136 C) o o 2.0 o TC : 99.5 C 90 1.8 o VTS : 2.044 V (101 C) 80 1.6 70 1.4 60 1.2 50 1.0 40 0.8 30 0.6 20 0.4 VOLTAGE, VTS [V] o CASE TEMPERATURE, TC [ C] 160 There are four variables with two equations and, therefore, set both variables as desired. Ru, the pull-up resistor for VO, can be chosen to be 10 kΩ. R2 can be 1 kΩ, considering VREF is below one half of the supply voltage, which is 5 V in this example, and R1 needs to be bigger than R2. A Microsoft® Excel® Solver can be used to get the answer of R1=1364 Ω and Rf= 3952 Ω. Close standard resistor values would be 1.37 kΩ and 3.92 kΩ. These two resistor values result in VTS_off of 2.225 V, which is 99.7°C and VTS_on of 1.839 V, which is 79.6°C. 2.230V (=100℃) 0V Figure 21. Comparator Output with Hysteresis Using TSU 0.2 10 0 0 10 20 30 40 50 60 70 80 90 0.0 100 5.2. Bootstrap Circuit Design TIME [min] Operation of Bootstrap Circuit The VBS voltage, which is the voltage difference between VB (U, V, W) and VS (U, V, W), provides the supply to the HVIC within Motion SPM 5 Series V2 products. This supply must be in the range of 13.5 V~16.5 V to ensure that the HVIC can fully drive the high-side MOSFET. The SPM5 V2 products include under-voltage lockout protection for VBS to ensure that the HVIC does not drive the high-side MOSFET if the VBS voltage drops below the specific voltage shown on the datasheet. This function prevents the MOSFET from operating in a high-dissipation mode. Figure 19. OTP Test in Real Application Figure 20 is an example of over-temperature protection circuit using the Vts signal. A comparator with hysteresis is used to create a low active OT signal that can be read by a microprocessor. Based on this signal, the microprocessor can disable or enable PWM output. Calculate the resistor values to make the upper threshold level 100ºC and the lower threshold level 80ºC so that the comparator output voltage VO matches the waveform in Figure 21. 5V MCU Rf R1 Vref I/O Port Comparator VTS Vo C14 104 The VBS floating supply can be generated in a number of ways, including the bootstrap method shown in Figure 22. This method is simple and inexpensive; however, the duty cycle and on-time are limited by the need to refresh the charge in the bootstrap capacitor. The bootstrap supply is formed by a combination of bootstrap diode, resistor, and capacitor, as shown in Figure 22. SPM 5 Series V2 Product Ru R2 C16 104 Hysteresis voltage: ΔVTS=0.384V (THVIC=20℃) 1.846V (=80℃) C17 102 Figure 20. Example of OTP Using TSU VBS When the temperature is below 80ºC; VO, the open-collector output of the comparator, should stay HIGH. To make VO transition to LOW at 100ºC, VREF needs to go below 2.230 V, which is VTS voltage at 100ºC. CBS VCC VCC(H) IN(H) (2) CVCC When the temperature is above 100ºC, VO should stay LOW. To make VO transition to HIGH at 80ºC, VREF needs to be higher than 1.846 V, which is VTS voltage at 80ºC. IN(L) COM (3) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 VB DBS (Integrated RBS) Motion SPM® VB VCC HO IN(H) HVIC VS VDC IN(L) LO COM Figure 22. Bootstrap Circuit for the Supply Voltage (VBS) of HVIC www.fairchildsemi.com 14 AN-9080 APPLICATION NOTE The current flow path of the bootstrap circuit is show in Figure 23. When VS is pulled down to ground (either through the low-side power device or the load), the bootstrap capacitor, CBS, is charged through the bootstrap diode (DBS) and the resistor from the VCC supply. The bootstrap resistor is not included in Figure 23 because the bootstrap diode in SPM 5 Series version 2 products has resistive characteristics. The characteristics of the built-in bootstrap diode in the SPM5 V2 products are: Fast recovery diode: 600 V / 0.5 A Typical trr: 80 ns Resistive characteristic: equivalent resistor: ~15 Ω Table 7 shows the forward-voltage drop and reverserecovery characteristics of the bootstrap diode. VBS Table 7. Bootstrap Diode Specifications CBS VCC VB DBS (Include RBS) ichg VCC(H) OFF IN(H) ON IN(L) COM Symbol Motion SPM® VB VCC HO IN(H) HVIC VS Parameter Condition Typ. VF Forward-Drop Voltage trr Reverse-Recovery Time IF=0.1 A, TC=25°C 80 ns IF=0.1 A, TC=25°C 2.5 V Table 8. Bootstrap Diode Absolute Max. Ratings VDC Symbol IN(L) VRRMB LO COM IFB (3) IFPB(3) Parameter Condition Maximum Repetitive Reverse Voltage Forward Current TC=25°C Forward Current TC=25°C, Under (Peak) 1 ms Pulse Width Rating 600 V 0.5 A 1.5 A Note: 3. Calculated values or design parameters. Figure 23. Bootstrap Circuit Charging Path Built-in Bootstrap Diode When the high-side MOSFET or body diode conducts, the bootstrap diode (DBS) supports the entire bus voltage, so a diode with withstand voltage of more than 500 V is required. It is important that this diode has a recovery time of less than 100 ns characteristic to minimize the amount of charge fed back from the bootstrap capacitor into the VCC supply. The bootstrap resistor is necessary to slow down the dVBS/dt and limit initial charging current (Icharge) of the bootstrap capacitor. Initial Charging of Bootstrap Capacitor Adequate on-time of the low-side MOSFET to fully charge the bootstrap capacitor is required before normal operation of PWM starts. Figure 25 shows an example of initial bootstrap charging sequence. Once VCC establishes, VBS must be charged by turning on low-side MOSFETs. PWM signals are typically generated by an interrupt triggered by a timer with a fixed interval based on the switching carrier frequency. Therefore, it is desired to maintain this structure without creating complementary high-side PWM signals. Figure 24 shows the built-in bootstrap diodes of SPM5 V2 products’ special VF characteristics to be used without additional bootstrap resistors. Therefore, only external bootstrap capacitors are needed to make a bootstrap circuit. The capacitance of VCC should be sufficient to supply necessary charge to VBS capacitance of all three phases. If normal PWM operations start before VBS reaches the undervoltage lockout reset level, high-side MOSFETs do not switch accordingly without creating any fault signal. This may lead to a failure of motor start in some applications. VPN 0V VCC 0V VBS 0V ON VIN(L) 0V Figure 24. V-I Characteristics of Bootstrap Diode in SPM5 V2 Products Section of charge pumping for VBS : Switching or Full Turn on Start PWM VIN(H) OFF 0V Figure 25. Timing Chart of Initial Bootstrap Charging © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 15 AN-9080 APPLICATION NOTE Selection of Bootstrap Capacitor The bootstrap capacitance can be calculated by: If three phases are charged synchronously, initial charging current through a single shunt resistor may exceed the overcurrent protection level. In that case, a sequential charging among three phases is more appropriate. CBS The initial charging time (tcharge) can be calculated from the following equation: t charge CBS (RBS RDS _ ON ) VCC 1 ln( ) VCC VBS (min) VF VLS ILeak t VBS (5) where: Δt: maximum on pulse width of high-side MOSFET; ΔVBS: allowable discharge voltage (voltage ripple) of the CBS; and ILeak: maximum discharge current of the CBS, including: Gate charge for turning the HS MOSFET on Quiescent current to the HS circuit in the HVIC Level-shift charge required by level-shifters in HVIC Leakage current in the bootstrap diode CBS capacitor leakage current (can be ignored for non-electrolytic capacitors) Bootstrap diode reverse-recovery charge. Practically, 1 mA of ILeak is recommended for Motion SPM®5 Series V2 products. By considering dispersion and reliability, the capacitance is generally selected to be twice the calculated one. The CBS is only charged when the highside MOSFET is off and the VS voltage is pulled down to ground. Therefore, the on-time of the low-side MOSFET must be sufficient to ensure that the charge drawn from the CBS capacitor can be fully replenished. Hence, there is an inherent minimum on-time for the low-side MOSFET (or off-time of the high-side MOSFET). (4) where: VF: forward-voltage drop across the bootstrap diode; VBS(min): minimum value of the bootstrap capacitor; VLS: voltage drop across the low-side MOSFET or load; and δ: duty ratio of PWM (0 – 1). VF is actually not a constant and varies depending on the amount of bootstrap charging current. VLS changes by the magnitude and direction of the phase output current in normal operation. RDS_ON drop by bootstrap charging current must be considered because phase output current can be assumed to zero at initial charging. VLS can be regarded as zero and RDS_ON needs to be part of RC time constant. In that case, VF needs to set as approximately 1 V, which is the value of a non-resistive diode, and RBS needs to be 15 Ω. Figure 26 and Figure 27 show real waveforms of the initial bootstrap capacitor charging. Figure 26 is with 1 µF capacitor and Figure 27 is with 47 µF capacitor to demonstrate two extreme cases. In Figure 26, bootstrap voltage charges to 13 V in 25 µs, but in Figure 27 it takes several ms at 50% duty. The initial peak current values are about 1 A, which can be expected from Figure 24. Bootstrap Capacitance Calculation Examples Examples of bootstrap capacitance calculation: ILeak = 1.0 mA (recommended value) ΔVBS = 0.1 V (recommended value) Δt = Maximum on pulse width of high-side MOSFET = 0.2 ms. (depends on user system) CBS _ min ILeak t 1mA 0.2ms 2.0 10 6 VBS 0.1V (6) → More than two times → 4.7 µF. Note: 4. This capacitance value can be changed according to the switching frequency, the type of capacitor used, and recommended VBS voltage of 13.5~16.5 V (from datasheet). The above result is a calculation example and should be changed according to the actual control method and lifetime of component. Figure 26. Waveform of Initial Bootstrap Charging (Conditions: VDC=300 V, VCC=15 V, CBS=1 μF, LS MOSFET Turn-on Time=25 μs) Figure 28 shows bootstrap capacitance value versus switching frequency with maximum discharge current of 2 mA. Figure 27. Waveform of Initial Bootstrap Charging (Conditions: VDC=300 V, VCC=15 V, CBS=47 μF, LS MOSFET Turn-on Time=100 μs) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 16 AN-9080 APPLICATION NOTE Figure 31. ton_pw and toff_pw vs. ID and TJ of FSB50450A It is not included in this graph; but as VCC increases, ton_pw decreases and toff_pw increases. 5.4. Short-Circuit SOA SPM 5 Series products have MOSFETs and endure longer than IGBT-based modules when short-circuit situations occur. Figure 32 is the test circuit used to measure shortcircuit withstanding time and the definitions of the terms used in the measurement. The low-side MOSFET is shorted with a wire and the high-side device is turned on. Figure 28. Capacitance of Bootstrap Capacitor on Variation of Switching Frequency 5.3. Minimum Pulse Width As shown in Figure 29, there are input noise filters of 90 ns time constant inside the HVIC. It screens out pulses narrower than the filter time constant. Additional propagation delay in level-shifters and other circuits, together with gate charging time, prevent SPM 5 products from responding to an input pulse narrower than ~120 ns. HVIC of Motion SPM® 5 Series Version 2 Products Input Noise Filter HIN Level-Shift Circuit Common Mode Noise Canceller Gate Driver w/ Gate Resistors HO Gate Driver w/ Gate Resistors LO 500k(typ) Input Noise Filter LIN 500k(typ) Matching Delay Figure 32. Short Circuit Withstanding Time Test 90ns(typ) Figure 33 is a waveform of FSB50550A at a short-circuit condition of VDC=400 V, VCC=VBS=20 V, TJ=150°C. Even in this type of extreme condition, FSB50550A demonstrates its ability to endure short-circuit conditions several times longer than IGBT modules. Figure 29. Internal Structure of Signal Input Pins Figure 30 shows definitions of ton_pw and toff_pw illustrated in Figure 31. ton_pw is the minimum pulse width of PWM ON signal required to make VDS decrease to zero, as shown on the left side of Figure 30. toff_pw is the minimum pulse width of PWM OFF signal required to make ID decrease to zero. Figure 30. Definition of ton_pw and toff_pw Figure 31 shows variations of ton_pw and toff_pw as the ID and TJ of FSB50450A changes. As ID increases, ton_pw increases, but toff_pw does not change much. As TJ increases, ton_pw decreases, but toff_pw does not vary much. Figure 33. SCWT of FSB50550A at Worst Condition © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 17 AN-9080 6. APPLICATION NOTE Application Example C1 (1 ) COM (2 ) VB(U) (3 ) VCC(U) (4 ) IN(UH) R5 Note1 C5 C2 Note2 (5 ) IN(UL) (6 ) N.C Microprocessor VCC VB HIN HO LIN VS COM LO (18) U , VS(U) C3 Note4 (9 ) IN(VH) (10) IN(VL) C2 Note3 (11) VTS (12) VB(W) (13) VCC(W) (14) IN(WH) (15) IN(WL) C2 VDC (19) NU (7 ) VB(V) (8 ) VCC(V) Note5 (17) P VCC VB HIN HO LIN VS COM LO (20) NV (21) V , VS(V) Motor VTS Note5 VCC VB HIN HO LIN VS COM LO (22) NW (23) W , VS(W) (16) N.C For temperature sensing For current sensing and protection R4 Note6 R3 Note3 Note8 C4 15V Supply Note5 Note7 Figure 34. Example of Application Circuit Notes: 1. Gate signal inputs are active-HIGH with 500 kΩ internal pull-down resistors. However, an additional 4.7 kΩ pulldown resistor is recommended for each gate signal input to prevent malfunction induced by switching noise. 2. Shorter traces are desirable between the microprocessor and the power module. If necessary, RC filters can be employed on gate signals to suppress noise coupled from power traces and remove very narrow pulses. RC values should be selected for input signals to be compatible with the turn-on and turn-off threshold voltages. Keep in mind that this RC filter may alter the timing of PWM and the resulting volt-second. 3. Each HVIC needs to have a 1 µF cermaic capacitor close to VCC pin and possibly to the COM pin to supply instantaneous power. An electrolytic capacitor of 10 µF is required to supply stable VCC voltage to the module. A Zener diode can be used in parallel to ensure VCC does not increase beyond a certain voltage at surge events. 4. A high-frequency non-inductive capacitor, C3, of around 0.1~0.22 µF/600 V should be placed very close to the module and between P and the ground side of the shunt resistor, R3. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 5. PCB traces for the main power paths between DC bus capacitors and the module should be as short as possible to minimize the noise associated with the parasitic inductance. These traces are colored in blue. 6. The current feedback trace should be connected directly from the shunt resistor (Kelvin connection) to get a clean and undistorted signal. 7. The power ground and the signal ground need to be connected at a single point to prevent switching noise on the power side from interfering with control signals. 8. Relays are commonly used in all home appliances electrical equipment and should be kept a sufficient distance from the microprocessor to avoid electromagnetic interference. www.fairchildsemi.com 18 AN-9080 APPLICATION NOTE If the snubber capacitor is installed in location A in Figure 35, it cannot suppress the surge voltage effectively due to parasitic impedance of the traces between the capacitor and the module. If the capacitor is installed in location B, surge suppression is more effective because the snubber capacitor is connected right at the module power pins. However, in case a single shunt resistor is used for phase current reconstruction or over-current protection, the voltage across the shunt resistor cannot correctly reflect the DC bus current information consumed by the module and, therefore, the current feedback signal is distorted. The C position is a reasonable compromise with better suppression than location A, without impacting the current sensing signal accuracy. For this reason, location C is generally used. 6.1. Recommended Wiring of Shunt Resistor External current-sensing resistors are applied to detect phase current. A longer pattern between the shunt resistor and SPM pins cause large surge voltages that might damage built-in ICs and distort the sensing signals. To decrease the pattern inductance, the wiring between the shunt resistor and SPM pins should be as short as possible. Parasitic impedance between the shunt resistor and the power module pins should be less than 10 nH, which results from a trace in 3 mm width, 20 mm length, and 1 oz thickness. 6.2. Snubber Capacitor As shown in Figure 35, snubber capacitors should be carefully located to suppress surge voltages effectively. A 0.1~0.22 µF snubber capacitor is generally a recommended. Incorrect position of Snubber Capacitor 6.3. PCB Layout Guidance Figure 36 shows an example of PCB layout for a fan application. This “donut” shape of the board facilitates the inclusion of the board within the motor frame. The compact size of Motion SPM 5 Series is the key to overcome the mechanical challenge in this type of design. More detailed guidelines can be found in Fairchild reference designs RD-FSB50450A and RD-FSB50760SF. Correct position of Snubber Capacitor P A Capacitor Bank B SPM C Wiring Leakage Inductance Nu,Nv,Nw Please make the connection point as close as possible to the terminal of shunt resistor COM Shunt Resistor Wiring inductance should be less than 10nH. width > 3mm, length < 20mm Figure 35. Recommended Wiring of Shunt Resistor and Snubber Capacitor Figure 36. PCB Layout Example © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 19 AN-9080 APPLICATION NOTE Because Motion SPM 5 Series does not have screw holes, flatness of the top surface is not specified on the datasheet. But because of its compact size, warpage is below several tens of µm. Special methods are required to install a heat sink, as shown in Figure 39. 6.4. Heat Sink Mounting Recommended Cooling Method Motion SPM 5 Series does not have screw holes for mounting a heat sink on top of the module because it is a very compact device aiming for small power applications. However, if it is desired to extend the power capability of the module by attaching a heat sink, this section introduces several methods. Temperature rise of power semiconductors is coming from the non-ideal aspects of switching devices; such as IGBT, MOSFET, and diode. When the switching device turns on, the forward-voltage drop results in conduction loss and the finite rise and fall time of current and voltage during the switching period create switching loss. These power losses make the junction temperature, as well as the case temperature, rise and the thermal resistance of each package plays an important role, as shown in the formula: TJ-TC = (Power loss) x (Thermal Resistance between Junction-to-Case) Adhesive material with high thermal conductivity, such as Loctite® 384, can be used to fix the heat sink on the top surface, as shown in Figure 39(a). Another way to mount a heat sink is to use screws throughout the PCB and the heat sink as shown in Figure 39(b). SPM 5 products should be soldered first. Excessive torque may bend the PCB. Fairchild has developed a special metal strip that fits in the slit on the bottom side of SPM5 package, as shown in Figure 39(c). The heat sink can be mounted on the module first before the soldering process. A heat sink with leads can be used, as shown in Figure 39(d). Keep good contact between the top surface of the module and the heat sink during the soldering process. (7) Using the chassis for heat-sink, as shown in Figure 39(e), can be an effective solution for built-in applications. But it is difficult to maintain mechanical accuracy in assembly and flexible thermal interface material is often used to fill the gap between module and the chassis. Therefore, to decrease the case temperature and increase the SOA area, total thermal resistance and power losses must be minimized. Heat-sink, one of the most popular cooling methods of power devices, decreases the thermal resistance between the package case and the ambient. A heat-sink can improve the thermal performance by spreading the heat to the ambient more effectively. Anything with comparably high thermal conductivity can be used as a heat-sink. For example, even a PCB pattern can be a heat-sink if it has enough cooling areas. DIP without stand-offs and SMD products can benefit from this cooling area contacting the bottom-side of the module on the PCB. Thicker and wider patterns of power pins are useful in a similar fashion. Figure 37 shows a typical test board for Motion SPM 5 Series without cooling area. Figure 38 shows a test board with cooling area on the PCB surfacing the bottom side of the module and with wider traces for power pins. Figure 37. Test Board without Cooling Area Figure 38. Test Board with Cooling Area of Copper Plane Under the Module and Thick Power Pins Figure 39. Heat Sink Installation Methods © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 20 AN-9080 APPLICATION NOTE Silicon Thermal Compound Silicone thermal compound, also called thermal grease, should be applied between the heat sink and the flat surface of the SPM 5 Series to fill microscopic air gaps due to imperfect flatness that ultimately reduce the contact thermal resistance. Thermal conductivity of thermal compound is about 0.5 – 10 W/(mK) and far greater than that of air (0.024), but far smaller than that of metal (Aluminum 220, Copper 390). It should not be used too much; a uniform layer of 100 ~ 200 µm thickness is desired. Figure 41 shows the test bench setup and the case temperature comparison result. FSB50450A shows outstanding thermal performance compared to its competition in the same operating conditions. 6.5. System Performance A fan motor for an air-conditioner indoor unit has been tested to provide comparison data between Motion SPM 5 Series V2 and competitive products. Figure 40 illustrates the power loss of single power device, such as MOSFET or IGBT. FSB50450A (Motion SPM 5 Series V2 – 500 V / 1.5 A) shows the lowest conduction loss and switching loss compared to competitive products in the same operating conditions. This lowest power loss with Motion SPM 5 Series V2 means better energy efficiency in the system. Figure 41. Case Temperature Comparison of SPM 5 Series V2 and Competition (Test Conditions: VDC=300 V, VCC=15 V, fSW=16.6 kHz, ID=0.3 Arms, TA=25°C, SVPWM, Dead Time=2.6 μs, 124 W Fan Motor with Blade for Air Conditioner) Figure 40. Power Loss Comparison © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 21 AN-9080 8. APPLICATION NOTE Handling Guide and Packing Information 8.1. Handling Precautions When using semiconductors, the incidence of thermal and/or mechanical stress to the devices due to improper handling may result in significant deterioration of their electrical characteristics and/or reliability. Transportation Handle the device and packaging material with care. To avoid damage to the device, do not toss or drop. During transport, ensure that the device is not subjected to mechanical vibration or shock. Avoid getting devices wet. Moisture can adversely affect the packaging (by nullifying the effect of the antistatic agent). Place the devices in special conductive trays. When handling devices, hold the package and avoid touching the leads, especially the gate terminal. Put package boxes in the correct direction. Putting them upside down, leaning them, or giving them uneven stress can cause the electrode terminals to be deformed or the resin case to be damaged. Throwing or dropping the packaging boxes can cause the devices to be damaged. Wetting the packaging boxes might cause the breakdown of devices when operating. Pay attention not to wet them when transporting on a rainy or snowy day. Storage 1. Avoid locations where devices might be exposed to moisture or direct sunlight. (Be especially careful during periods of rain or snow.) 2. Do not place the device cartons upside down. Stack the cartons on top of one another in an uprighrt position only. Do not place cartons on their sides. 3. The storage area temperature should be maintained within a range of 5°C to 35°C, with humidity kept within the range from 40% to 75%. 4. Do not store devices in the presence of harmful (especially corrosive) gases or in dusty conditions. 5. Use storage areas with minimal temperature fluctuation. Rapid temperature changes can cause moisture condensation, resulting in lead oxidation or corrosion, which degrades lead solderability. 6. When repacking devices, use antistatic containers. Unused devices should be stored less than one month. 7. Do not allow external forces or loads to be applied to the devices while they are in storage. 4. Place a conductive mat over the floor of the work area or take other appropriate measures, so that the floor surface is grounded to earth and is protected against electrostatic electricity. 5. Cover the workbench surface with a conductive mat, grounded to earth, to disperse electrostatic electricity on the surface through resistive components. Workbench surfaces must not be constructed of low-resistance metallic material that allows rapid static discharge when a charged device touches it directly. 6. Ensure that work chairs are protected with an antistatic textile cover and are grounded to the floor surface with a grounding chain. 7. Install antistatic mats on storage shelf surfaces. 8. For transport and temporary storage of devices, use containers that are made of antistatic materials or materials that dissipate static electricity. 9. Make sure cart surfaces that come into contact with device packaging are made of materials that conduct static electricity and are grounded to the floor surface with a grounding chain. 11. Operators must wear a wrist strap grounded to earth through a resistor of about 1 MΩ. 12. If tweezers are likely to touch the device terminals, use an antistatic type and avoid metallic tweezers. If a charged device touches such a low-resistance tool, a rapid discharge can occur. When using vacuum tweezers, attach a conductive chucking pad at the tip and connect it to a dedicated ground used expressly for antistatic purposes. 13. When storing device-mounted circuit boards, use a board container or bag protected against static charge. Keep them separated from each other and do not stack them directly on top of one another to prevent static charge / discharge due to friction. 14. Ensure that articles (such as clip boards) that are brought into static electricity control areas are constructed of antistatic materials as much as possible. 15. In cases where the human body comes into direct contact with a device, be sure finger cots or gloves protected against static electricity are worn at all times. Electrical Shock A device undergoing electrical measurement poses the danger of electrical shock. Do not touch the device unless sure that the power to the measuring instrument is off. Be aware of the risk of moisture absorption by the products after unpacking moisture-proof packaging. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 Be sure that all equipment, jigs, and tools in the working area are grounded to earth. 10. Operators must wear antistatic clothing and conductive shoes (or a leg or heel strap). Environment 1. When humidity in the working environment decreases, the human body and other insulators can easily become charged with electrostatic electricity due to friction. Maintain the recommended humidity of 40% to 60% in the work environment. 2. 3. www.fairchildsemi.com 22 AN-9080 APPLICATION NOTE Circuit Board Coating When using devices in equipment requiring high reliability or in extreme environments (where moisture, corrosive gas, or dust is present), circuit boards can be coated for protection. However, before doing so, carefully examine the possible effects of stress and contamination that may result. There are many and varied types of coating resins whose selection is, in most cases, based on experience. However, because device-mounted circuit boards are used in various ways, factors such as board size, board thickness, and the effects that components have on one another; makes it practically impossible to predict the thermal and mechanical stresses to which the semiconductor devices are subjected. 8.2. Packing Specifications Motion SPM 5 Series products are normally shipped in tube. The SMD package is shipped in tape. More detailed information can be found in Figure 42 for DIP package, in Figure 43 and Figure 44 for SMD package, in Figure 45 for Double-DIP package, and in Figure 46 for Zigzag-DIP package. Please ignore internal package names shown in these figures. Figure 42. Packing Information for DIP Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 23 AN-9080 APPLICATION NOTE Figure 43. Packing Information for SMD Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 24 AN-9080 APPLICATION NOTE Figure 44. Packing Information for SMD Package (Continued) © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 25 AN-9080 APPLICATION NOTE Figure 45. Packing Information for Double-DIP Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 26 AN-9080 APPLICATION NOTE Figure 46. Packing Information for Zigzag-DIP Package © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 www.fairchildsemi.com 27 AN-9080 9. APPLICATION NOTE Related Resources AN-9760: PCB Design Guidance for SPM® AN-9082: Motion SPM® 5 Series Thermal Performance Information by Contact Pressure AN-9042: Motion SPM® 5 Series V1 User’s Guide RD-FSB50450A (Reference Design) RD-402 FSB50760SF (Reference Design) FSB50660SF(T) — Motion SPM® 5 SuperFET® Series FSB50760SF(T) — Motion SPM® 5 SuperFET® Series FSB50450AS — Motion SPM® 5 Series FSB50825AS — Motion SPM® 5 Series FSB50250A(T) — Motion SPM® 5 Series FSB50250AS — Motion SPM® 5 Series FSB50325A(T) — Motion SPM® 5 Series FSB50450A — Motion SPM® 5 Series FSB50550A(T) — Motion SPM® 5 Series FSB50550AS — Motion SPM® 5 Series SPM® Module Design Guide Motion Control Design Tool FCM8531 — MCU Embedded and Configurable 3-Phase PMSM / BLDC Motor Controller FCM8201 — 3-Phase Sinusoidal Brushless DC Motor Controller FCM8202 — 3-Phase Sinusoidal Brushless DC Motor Controller Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2013 Fairchild Semiconductor Corporation Rev. 1.0.1 • 4/16/14 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 28