www.fairchildsemi.com AN-9075 Smart Power Module, Motion 1200 V SPM 2 Series User’s Guide 1. 1.1 1.2 1.3 Introduction ................................................................................................................................... 2 Design Concept ............................................................................................................................... 2 Ordering Information ....................................................................................................................... 3 Features and Integrated Functions ................................................................................................. 3 2. 2.1 2.2 2.3 Product Synopsis .......................................................................................................................... 4 Detailed Pin Definition & Notification .............................................................................................. 5 Absolute Maximum Ratings ............................................................................................................ 6 Electrical Characteristics ................................................................................................................. 9 3. 3.1 3.2 Package ........................................................................................................................................ 11 Detailed Package Outline Drawings ............................................................................................. 12 Marking Information ...................................................................................................................... 13 4. 4.1 4.2 Operating Sequence for Protections ........................................................................................ 14 Short-Circuit Current Protection (SCP) ......................................................................................... 14 Under-Voltage Lockout Protection ................................................................................................ 15 5. 5.1 5.2 5.3 5.6 5.7.1. 5.7.2. 5.7.3. 5.8 5.9 Key Parameter Design Guidance .............................................................................................. 16 Selection of RSC Resistor for Protection ...................................................................................... 16 Shunt Resistor Selection at N-Terminal for Current Sensing & Protection ................................... 18 Time Constant of Internal Delay ................................................................................................... 19 Circuit of Input Signal (IN(xH), IN(xL)) .......................................................................................... 21 Operation of Bootstrap Circuit ....................................................................................................... 22 Selection of Bootstrap Capacitor Considering Initial Charging ..................................................... 22 Selection of Bootstrap Capacitor Considering Operating ............................................................. 24 Built-in Bootstrap Diode ................................................................................................................ 25 Circuit of NTC Thermistor (Temperature Monitoring of Module) .................................................. 26 6. 6.1 6.2 Print Circuit Board (PCB) Design .............................................................................................. 29 General Application Circuit Example .......................................................................................... 29 PCB Layout Guidance ................................................................................................................... 30 7. Packing Information .................................................................................................................... 31 © 2013 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 1 AN-9075 1. APPLICATION NOTE are inverterized motor drives for industrial use, such as air conditioners, general-purpose inverters, and serve motors. Introduction This application note supports the 1200-V rated Motion SPM® family. It should be used in conjunction with Motion SPM 2 datasheets, Fairchild’s Motion SPM evaluation board user guides (FEB212_001), and application notes AN-9079 — Thermal Performance Information and AN-9076 — Mounting Guidance. A design advantage integrates an NTC thermistor for temperature measuring of power chips (e.g. IGBTs, FastRecovery Diode (FRDs) on the same substrate. Most customers want to know the exact temperature of power chips because temperature affects the quality, reliability, and longevity of products. This desire is thwarted because integrated power chips (e.g. IGBTs, FRD) inside modules operate in high-voltage conditions. Therefore, instead of directly sensing the temperature of power chips, customers have been using an external NTC thermistor for sensing the temperature of the module or heat-sink. This method doesn’t accurately reflect the temperature of power components due to cost, but is simple. The NTC thermistor of the Motion SPM 2 is integrated with the power chips on the same ceramic substrate and therefore more accurately reflects the temperature of power chips. 1.1 Design Concept Minimized package and a low power consumption module with improved reliability. This is achieved by applying a new 1200 V gate-driving high-voltage integrated circuit (HVIC), a new insulated-gate bipolar transistor (IGBT) of advanced silicon technology, and improved direct bonded copper (DBC) substrate base transfer mold package. Motion SPM 2 achieves reduced board size and improved reliability compared to existing discrete solutions. Target applications Figure 1. External View and Internal Structure of Motion SPM 2 Series Table 1. Product Line-up and Target Application (1) Target Application Fairchild Device IGBT Rating Motor Rating Motor drives for industrial use, System air conditioners, General-purpose inverters, Servo motors FNA21012A 10 A / 1200 V 1.5 kW / 440 VAC FNA22512A 25 A / 1200 V 3.7 kW / 440 VAC FNA23512A 35 A / 1200 V 5.5 kW / 440 VAC Isolation Voltage VISO = 2500 VRMS (Sine 60 Hz, 1-min. All Shorted Pins Heat Sink) Note: 1. These motor ratings are simulation results under following conditions: VAC=440 V, VDD=15 V, TC=100°C, Tj= 150°C, fPWM=5kHz, PF=0.8, MI=0.9, Motor efficiency=0.75, overload 150% for 1min. These motor ratings are general ratings, so may be changed by conditions. © 2013 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 2 AN-9075 APPLICATION NOTE (33) VB(W) 1.2 Ordering Information P (1) VB (32) VBD(W) (31) VCC(WH) FNA21012A VCC OUT COM (30) IN(WH) IN VS (34) VS(W) Voltage Rating (X10) 120X10=1200V (28) VB(V) W (2) VB (27) VBD(V) Voltage Rating (X10) 12: 120V 4 : SPM2 Package (26) VCC(VH) Current Rating 10 : 10A rating 25 : 25A rating 35 : 35A rating VCC OUT COM (25) IN(VH) IN VS (29) VS(V) V (3) Package Option (23) VB(U) (21) VCC(UH) (20) COM(H) F : Fairchild Semiconductor (19) IN(UH) (17) CSC 1.3 Features and Integrated Functions DBC Substrate - VS C(SC) U (4) OUT(UL) C(FOD) VFO IN(WL) OUT(VL) NV (6) (12) IN(UL) One-Channel HVIC (three HVIC) for High-Side IGBTs Control (11) COM(L) IN(VL) IN(UL) COM OUT(WL) NU (7) (10) VCC(L) Three-Channel LVIC (one LVIC) for Low-Side IGBTs Control VCC VTH (9) RTH (8) (18) RSC Six IGBTs / Diodes; Sense IGBTs for Low-Side Figure 3. Internal Equivalent Circuit, Input / Output Pins NTC Thermistor for Temperature Sensing Bootstrap Diodes Single DC Supply Compatible Using Integrated Bootstrap Diode High-Side Gate Driver (One-Channel) IN Control Drive Supply: (14) IN(WL) Integrated Components: - (15) VFO Excellent Thermal Conductivity, Keeping 2500 Vrms Isolation Voltage from Pin to Heat Sink (13) IN(VL) - OUT COM NW (5) (16) CFOD - VCC (24) VS(U) Figure 2. Ordering Information VB (22) VBD(U) Product Category N : Inverter module P : Converter module with PFC part M : CI module (Converter + Inverter) High-Voltage Level-Shift Circuit Input interface: Active HIGH Compatible with 3.3 V Controller Outputs Under-Voltage Lockout without Fault Signal Low-Side Gate Driver (Three-Channel) - Input Interface: Active HIGH Compatible with 3.3 V Controller Outputs Under-Voltage Lockout with Fault Signal Figure 4. Package Top-View and Pin Assignment Short-Circuit & Over-Current Protection Detecting Sense Current from External Resistor (RSC) with RSC Pin Soft Turn-off for Preventing Excessive Surge Voltage Controllable Fault-Out Duration by External Capacitor (CFOD) with CFOD Pin © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 3 AN-9075 APPLICATION NOTE 2. Product Synopsis This section discusses pin descriptions, electrical specifications, characteristics, and packaging. Table 2. Pin Description Pin Number Name 1 P Positive DC Link Input 2 W Output for W Phase 3 V Output for V Phase 4 U Output for U Phase 5 NW Negative DC Link Input for W Phase 6 NV Negative DC Link Input for V Phase 7 NU Negative DC Link Input for U Phase 8 RTH Series Resistor for Thermistor (Temperature Detection) 9 VTH Thermistor Bias Voltage 10 VCC(L) Low-Side Bias Voltage for IC and IGBT Driving 11 COM(L) Low-Side Common Supply Ground 12 IN(UL) Signal Input for Low-Side U Phase 13 IN(VL) Signal Input for Low-Side V Phase 14 IN(WL) Signal Input for Low-Side W Phase 15 VFO 16 CFOD 17 CSC Capacitor (Low-Pass Filter) for Short-Circuit Current Detection Input 18 RSC Resistor for Short-Circuit Current Detection 19 IN(UH) 20 COM(H) No Connection 21 VCC(UH) High-Side Bias Voltage for U Phase IGBT Driving 22 VBD(U) Anode of Bootstrap Diode for High-Side U Phase 23 VB(U) High-Side Bias Voltage for U Phase IGBT Driving 24 VS(U) High-Side Bias Voltage Ground for U Phase IGBT Driving 25 IN(VH) Signal Input for High-Side V Phase 26 VCC(VH) 27 VBD(V) Anode of Bootstrap Diode for High-Side V Phase 28 VB(V) High-Side Bias Voltage for V Phase IGBT Driving 29 VS(V) High-Side Bias Voltage Ground for V Phase IGBT Driving 30 IN(WH) 31 VCC(WH) 32 VBD(W) Anode of Bootstrap Diode for High-Side W Phase 33 VB(W) High-Side Bias Voltage for W Phase IGBT Driving 34 VS(W) High-Side Bias Voltage Ground for W Phase IGBT Driving © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 Description Fault Output Capacitor for Fault Output Duration Selection High-Side Common Supply Ground High-Side Bias Voltage for V Phase IC Signal Input for High-Side W Phase High-Side Bias Voltage for W Phase IC www.fairchildsemi.com 4 AN-9075 APPLICATION NOTE 2.1 Detailed Pin Definition & Notification High-side bias voltage pins for driving the IGBT / highside bias voltage ground pins for driving the IGBTs: ► Pins: VB(U)-VS(U), VB(V)-VS(V), VB(W)-VS(W) - The signal logic of these pins is active HIGH. The IGBT associated with each of these pins is turned ON when a sufficient logic voltage is applied to these pins. These are drive power supply pins for providing gate drive power to the high-side IGBTs. - By virtue of the ability of bootstrap, the circuit scheme is that no external power supplies are required for the high-side IGBTs. - The wiring of each input should be as short as possible to protect the Motion SPM 2 against noise influences. - Each bootstrap capacitor is charged from the VCC supply during ON state of the corresponding lowside IGBT. - To prevent signal oscillations, a RC coupling as illustrated in Figure 46 is recommended. - To prevent malfunctions caused by noise and ripple in the supply voltage, a low-ESR, low-ESL filter capacitor should be mounted very close to these pins. Low-Side Bias Voltage Pin / High-Side Bas Voltage Pins: ► Pins: VCC(L), VCC(WH), VCC(VH), VCC(UH) These are control supply pins for the built-in ICs. Resistor Connection Pin for Short-Circuit Current Detection ► Pin: RSC - Low-side sense IGBT current flows through this pin. Short-circuit and over-current can be detected at this pin through an external resistor. (refer to Figure 46) - If using three shunt resistors at N terminals for OCP and SCP without sense detecting from RSC, RSC should be connected to COM. These four pins should be connected externally. To prevent malfunctions caused by noise and ripple in the supply voltage, a low-ESR, low-ESL filter capacitor should be mounted very close to these pins. Short-Circuit and Over-Current Detection Input Pin ► Pin: CSC - The current sense current detecting resistor (R SC) should be connected between CSC and COM pins to detect over-current and short-circuit current. (refer to Figure 46). The shunt resistor should be selected to meet the detection levels matched for the specific application. The RC filter should be connected to the CSC pin to eliminate noise. - The connection length between the shunt resistor and CSC pin should be minimized. Low-Side Common Supply Ground Pins: ► Pins: COM(L), COM(H) - They are activated by voltage input signals. The terminals are internally connected to a Schmitttrigger circuit composed of 5 V-class CMOS. - - - These are supply ground pins for the built-in ICs. These two pins should be connected externally. Important! To avoid noise influences, the main power circuit current should not be allowed to flow through this pin. Anode Pins of Bootstrap Diode: ► Pins: VBD(UH), VBD(VH), VBD(WH), - These are pins to connect internal bootstrap diode for each high-side bootstrapping. - External resistor should be connected between these pins and each VCC(xH). Signal Input Pins: ► Pins: IN(UL), IN(VL), IN(WL), IN(UH), IN(VH), IN(WH) - These pins control the operation of the built-in IGBTs. © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 Fault Output Pin ► Pin: VFO - This is the fault output alarm pin. An active LOW output is given on this pin for a fault state condition in the SPM. - The alarm conditions are: Short-Circuit Current Protection (SCP), and low-side bias Under-Voltage Lockout (UVLO). - The VFO output is open drain configured. The VFO signal line should be pulled to the 5 V logic power supply with approximately 4.7 kΩ resistance. www.fairchildsemi.com 5 AN-9075 - Negative DC-link Pins ► Pins: NU, NV, NW - This is the bias voltage pin of internal thermistor. This pin should be connected to the 5 V logic power supply. These are the DC-link negative power supply pins (power ground) of the inverter. - These pins are connected to the low-side IGBT emitters of the each phase. Inverter Power Output Pins ► Pins: U, V, W Series Resistor for Thermistor (Temperature Detection) ► Pin: RTH - Thermistor Bias Voltage ► Pin: VTH APPLICATION NOTE For case temperature (TC) detection, this pin should be connected to an external series resistor. - The external series resistor should be selected to meet the detection range matched for the specification of each application (for details, refer to Figure 46). Inverter output pins for connecting to the inverter load (e.g. motor). Positive DC-Link Pin ► Pin: P - This is the DC-link positive power supply pin of the inverter. - It is internally connected to the collectors of the high-side IGBTs. - To suppress surge voltage caused by the DC-link wiring or PCB pattern inductance, connect a smoothing filter capacitor close to this pin (Tip: metal film capacitor is typically used). 2.2 Absolute Maximum Ratings TJ = 25°C, unless otherwise specified. Table 3. Inverter Symbol VPN Parameter Conditions Supply Voltage VPN(Surge) Supply Voltage (Surge) VCES ±IC ±ICP Rating Unit Applied between P – NU, NV, NW 900 V Applied between P – NU, NV, NW 1000 V 1200 V Collector – Emitter Voltage TC=25°C, TJ≤150°C Each IGBT Collector Current TC=25°C, TJ≤150°C, Under 1 ms Pulse Width Each IGBT Collector Current (Peak) PC Collector Dissipation TJ Operating Junction Temperature TC=25°C per One Chip FNA21012A 10 FNA22512A 25 FNA23512A 35 FNA21012A 20 FNA22512A 50 FNA23512A 70 FNA21012A 93 FNA22512A 154 FNA23512A (2) A A W 171 -40~150 °C Note: 2. The maximum junction temperature rating of the power chips integrated within the Motion SPM 2 product is 150°C. © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 6 AN-9075 APPLICATION NOTE Table 4. Control Part Symbol Parameter Conditions Rating Unit VCC Control Supply Voltage Applied between VCC(H), VCC(H) - COM 20 V VBS High-Side Control Bias Voltage Applied between VB(x), VS(x) 20 V VIN Input Signal Voltage Applied between IN(xH), IN(xL) - COM -0.3~VCC+0.3 V VFO Fault Output Supply Voltage Applied between VFO - COM -0.3~VCC+0.3 V IFO Fault Output Current Sink Current at VFO Pin 2 mA VSC Current Sensing Input Voltage Applied between CSC - COM -0.3~VCC+0.3 V Rating Unit Table 5. Bootstrap Part Symbol Parameter Conditions VRRM Maximum Repetitive Reverse Voltage 1200 V IF Forward Current TC=25°C, TJ≤150°C 1.0 A IFP Forward Current (Peak) TC=25°C, TJ≤150°C, Under 1 ms Pulse Width 2.0 A TJ Operating Junction Temperature -40~150 °C Rating Unit 800 V Module Case Operation Temperature See Figure 46 -40~125 °C TSTG Storage Temperature -40~125 °C VISO Isolation Voltage 2500 Vrms Table 6. Total System Symbol VPN(PROT) TC Parameter Self Protection Supply Voltage Limit (Short-Circuit Protection Capability) Conditions VCC, VBS=13.5~16.5 V, TJ=50°C, NonRepetitive, < 2 µs 60 Hz, Sinusoidal, 1-Minute, Connect Pins to Heat Sink Table 7. Thermal Resistance Symbol Parameter Rth(j-c)Q Conditions Inverter IGBT Part (per 1/6 Module) Junction-to-Case Thermal Resistance Rth(j-c)F © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 Inverter FWD Part (per 1/6 Module) Rating FNA21012A 1.33 FNA22512A 0.81 FNA23512A 0.73 FNA21012A 2.30 FNA22512A 1.58 FNA23512A 1.26 Unit °C/W www.fairchildsemi.com 7 AN-9075 APPLICATION NOTE Figure 5. Case Temperature (TC) Detecting Point Table 8. Recommended Operating Conditions Symbol Parameter Conditions Min. Typ. Max. Unit VPN Supply Voltage Applied between P - NU, NV, NW 400 600 800 V VCC Control Supply Voltage Applied between VCC(xH) - COM(H), VCC(L) COM(L) 13.5 15.0 16.5 V VBS High-Side Bias Voltage Applied between VB(x) - VS(x) 13.0 15.0 18.5 V dVCC/dt, dVBS/dt Control Supply Variation +1 V/µs tdead fPWM VSEN PWIN(ON) PWIN(OFF) TJ -1 Blanking Time for Preventing Arm-Short For Each Input Signal FNA21012A 2.0 FNA22512A 2.0 FNA23512A 2.0 PWM Input Signal -40°C ≤ TC ≤ 125°C, - 40°C ≤ TJ ≤ 150°C Voltage for Current Sensing Applied between NU, NV, NW - COM(H, L) (Including Surge Voltage) Minimum Input Pulse Width -5 µs 20 kHz 5 V 1.5 (3) µs 1.5 Junction Temperature -40 150 °C Note: 3. This product might not make response if the input pulse width is less than the recommended value. © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 8 AN-9075 APPLICATION NOTE 2.3 Electrical Characteristics TJ = 25°C, unless otherwise specified. Table 9. Inverter Part (Based on FNA21012A) Symbol Parameter Typ. Max. Unit VCE(SAT) Collector–Emitter Saturation Voltage VCC, VBS=15 V, VIN=5 V IC=10 A, TJ=25°C 2.2 2.8 V FWD Forward Voltage VIN=0 V 2.2 2.8 V 0.85 1.35 tC(ON) 0.25 0.55 tOFF 0.95 1.45 tC(OFF) 0.10 0.40 VF Conditions Min. IF=10 A, TJ=25°C tON HS trr tON LS 0.45 VPN=600 V, VCC=15 V, VBS=15 V, IC=10 A (4) TJ=25, VIN=0 V ↔5 V, Inductive Load Switching Times 0.25 0.75 1.25 tC(ON) 0.20 0.50 tOFF 0.95 1.45 tC(OFF) 0.10 0.40 trr 0.20 Collector – Emitter Leakage Current ICES µs VCE=VCES 5 mA Note: 4. tON and tOFF include the propagation delay of the internal drive IC. TC(ON) and tC(OFF) are the switching times of the IGBT itself under the given gate driving condition internally. For the detailed information, see Figure 6 and Figure 7. 15V Only for low side switching Line stray Inductance < 100nH HINx LINx One-Leg Diagram of Motion SPM VB P VCC IN Switching Pulse Inducotor HO trr VS toff 600V COM ton 100% ICx 15V OUT ICx 90% ICx VCC Inducotor LO IN Switching Pulse 10% VCEx vCEx COM N RSC 10% ICx tc(off) 10% VCEx 10% ICx tc(on) Line stray Inductance < 100nH Figure 6. Switching Evaluation Circuit © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 Figure 7. Switching Time Definition www.fairchildsemi.com 9 AN-9075 APPLICATION NOTE Table 10. Control Part Symbol IQCCH IQCCL IPCCH Parameter Conditions VCC(xH)=15 V, IN(xH)=0 V Quiescent VCC Supply Current Operating High-Side VCC Supply Current Min. Typ. VCC(xH) - COM(H) Max. Unit 0.15 VCC(L)=15 V, IN(xL)=0 V VCC(L) - COM(L) 5.0 VCC(xH)=15 V, FNA21012A fPWM=20 kHz, Duty=50%, FNA22512A Applied to One PWM Signal Input for High Side FNA23512A 0.3 0.3 13.0 IQBS Quiescent VBS Supply Current VBS=15 V, IN(xH)=0 V 0.3 IPBS Operating VBS Supply Current VCC=VBS=15 V, FNA21012A fPWM=20 kHz, Duty=50%, FNA22512A Applied to One PWM Signal Input for High Side FNA23512A VFOH VFOL ISEN VSC(ref) ISC UVBSD Short-Circuit Trip Level (5) VCC=15 V Supply Circuit, Under-Voltage Protection (6) tFOD Fault-Out Pulse Width VIN(ON) ON Threshold Voltage VIN(OFF) OFF Threshold Voltage Resistance of (7) Thermistor mA 4.5 9.0 mA 12.0 4.5 0.5 FNA21012A IC=10 A 7 FNA22512A IC=25 A 23 FNA23512A IC=35 A 36 CSC - COM(L) No Connection of Shunt Resistor at NU, V, W (5) Terminal Short-Circuit Current Level for Trip UVBSR RTH VB(x) - VS(x) VCC=15 V, VIN=5 V, Sensing Current of Each RSC=0, No Connection of Sense IGBT Shunt Resistor at NU,NV,NW Terminal mA 15.5 VCC=15 V, VSC=1 V, VFO Circuit: 4.7 kW to 5 V Pull-up UVCCD UVCCR 8.5 VCC=15 V, VSC=0 V, VFO Circuit: 4.7 kW to 5 V Pull-up Fault Output Voltage mA 0.3 VCC(L)=15 V, FNA21012A Operating Low-Side VCC fPWM=20 kHz, Duty=50%, FNA22512A Supply Current Applied to One PWM Signal Input for Low Side FNA23512A IPCCL mA 0.43 0.50 FNA21012A RSC=68 (±1%) 20 FNA22512A RSC=27 (±1%) 50 FNA23512A RSC=16 (±1%) 70 V mA 0.57 V A Detection Level 10.3 12.8 Reset Level 10.8 13.3 Detection Level 9.5 12.0 Reset Level 10.0 12.5 CFOD=Open 50.0 µs CFOD=2.2 nF 1.7 ms Applied between IN(xH)-COM(H), IN(xL)-COM(L) 2.6 0.8 TTH=25°C 47.0 TTH=100°C 2.9 V V k Notes: 5. Short-circuit current protection functions only at the low-sides because the sense current is divided from main current at the low-side IGBT. If inserting the shunt resistor for monitoring the phase current at NU, NV, NW terminal, the trip level of the short circuit current changes. 6. The fault-out pulse width tFOD depends on the capacitance value of CFOD. 7. TTH is the thermistor temperature. To determine case temperature (TC), experiment with the specific application. © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 10 AN-9075 APPLICATION NOTE 3. Package Since heat dissipation is an important factor limiting the power module’s current capability, the heat dissipation characteristics of a package are important in determining the performance. A trade-off exists among heat dissipation characteristics, package size, and isolation characteristics. The key to good package technology lies in the optimization package size while maintaining outstanding heat dissipation characteristics without compromising the isolation rating. In 1200 V Motion SPM 2, technology was developed with DBC substrate that resulted in good heat dissipation characteristics. Power chips are attached directly to the DBC substrate. This technology is applied 1200 V Motion SPM 2 achieving improved reliability and heat dissipation. Figure 8. Vertical Structure for Heat Dissipation Figure 9. Distance for Isolation Figure 8 and Figure 9 show the package outline and the cross-sections of the Motion SPM 2 package. Table 11. Mechanical Characteristics and Ratings Parameter Device Flatness Mounting Torque Terminal Pulling Strength Terminal Bending Strength Conditions See Figure 10 Mounting Screw: M4 Value Min. Typ. 0 Max. Unit +200 µm Recommended 0.9 N∙m 0.9 1.0 1.5 N∙m Recommended 9.1 kg∙cm 9.1 10.1 15.1 kg∙cm Load 19.6 N 10 Load 9.8 N, 90° Bend 2 Weight s Times 50 g Figure 10. Flatness Measurement Position © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 11 AN-9075 APPLICATION NOTE 3.1 Detailed Package Outline Drawings 0.80 25X 0.60 2.30 33X 1.70 1.30 0.70 (0.70) 2X 33.30 32.70 (7.00) 33.30 32.70 (7.00) 80.50 79.50 34 Æ ~6¡ 2¡ Æ 3.90 3.70 10 (R1.00) 39.76 38.76 37.60 13.00 12.40 33.50 32.50 4.40 2X 4.20 24.30 23.70 8.10 7.90 9 70.30 69.70 0.80 0.65 1 16.50 15.50 TOP VIEW 33.30 32.70 31.30 30.70 33 x 2.0 = (66.00) B 34 26.30 25.70 1.00 19.40 33.00 38.80 31.00 (7.00) 26.00 21.00 24.00 (0.70) 2.10 7X 1.90 1 B 9 4.00 0.80 2X 0.60 1.40 2.50 NOTES: UNLESS OTHERWISE SPECIFIED A) THIS PACKAGE DOES NOT COMPLY TO ANY CURRENT PACKAGING STANDARD B) ALL DIMENSIONS ARE IN MILLIMETERS. C) DIMENSIONS ARE EXCLUSIVE OF BURRS, MOLD FLASH, AND TIE BAR EXTRUSIONS. D) ( ) IS REFERENCE E) [ ] IS ASS'Y QUALITY F) DRAWING FILENAME: MOD34BAREV1.0 3.90 (1.50) 7X © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 6.00 2.00 Max. 1.10 (1.15) 16.00 14.00 DETAIL A DETAIL B (SCALE N/A) (SCALE N/A) 2.40 21.30 20.70 16.30 15.70 6.30 5.70 19.40 (16.00) 24.30 23.70 14.30 13.70 4.30 3.70 10 LAND PATTERN RECOMMENDATIONS www.fairchildsemi.com 12 AN-9075 APPLICATION NOTE 3.2 Marking Information Figure 11. Marking Information © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 13 AN-9075 APPLICATION NOTE 4. Operating Sequence for Protections 4.1 Short-Circuit Current Protection (SCP) Motion SPM 2 uses a sense current detecting resistor (RSC) for the short circuit current detection, as shown in Figure 12. LVIC has a built-in short-circuit current protection function. This protection function senses the voltage to the CSC pin. If this voltage exceeds the VSC(ref) (the threshold voltage trip level of the short-circuit) specified in the device datasheets(typ. VSC(ref) is 0.5 V), a fault signal is asserted and the all low side IGBTs are turned off. Typically, the maximum short-circuit current magnitude is gate-voltage dependent: higher gate voltage (VCC & VBS) results in larger short-circuit current. To avoid potential problems, the maximum short-circuit trip level is set below 1.7 times the nominal rated collector current. The LVIC short-circuit current protection-timing chart is shown in Figure 13. Motion SPM 2 P ISC (Short-Circuit Current) HVIC UH VH WH C Motor W V U ShortCircuit ! LVIC UL CSC LPF Circuit of SCP RF CSC RSC WL VL NV NU NW Operates protection function. (All LS IGBTs are shutdown) RSC SC Trip Level : VSC(REF) p ISC (Short-Circuit Current) Figure 12. Operation of Short-Circuit Current Protection Lower arms control input A6 Protection circuit state A7 SET Lower arms gate input RESET Soft turn-off for small voltage spike (to prevent of L*di/dt effect). A4 A2 A3 SC External filter delay + internal IC delay + IGBT off delay < SCWT (typical 2~3 μs). External filter is recommended with 1~2 μs time constant A1 Output Current A8 IC filtering < 500 ns Sensing Voltage ( of RSC ) Fault Output Signal SC Reference Voltage tFOD A5 Fault-out duration (tFOD): controllable by CFOD. Figure 13. Timing Chart of Short-Circuit Current Protection Function Notes: 8. A1-normal operation: IGBT on and carrying current. 9. A2-short-circuit current detection (SC trigger). 10. A3-hard IGBT gate interrupt. 11. A4-IGBT turns OFF by soft-off function. 12. A5-fault output timer operation start with internal delay (typ. 2.0 μs), tFOD=controlled by CFOD. 13. A6-input “L”: IGBT OFF state. 14. A7-input “H”: IGBT ON state, but during the active period of fault output the IGBT doesn’t turn ON. 15. A8-IGBT keeps OFF state. © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 14 AN-9075 APPLICATION NOTE 4.2 Under-Voltage Lockout Protection The LVIC has an under-voltage lockout protection (UVLO) function to protect the low-side IGBTs from operation with insufficient gate driving voltage. A timing chart for this protection is shown in Figure 14. Input Signal Protection Circuit State RESET SET RESET UVCCR Control Supply Voltage Needed LOW-to-HIGH input transition to turn on IGBT again. (Edge Trigger) Built-in typ.10 μs filter to prevent malfunction by noise. Filtering? B1 B6 B6 UVCCD Fault-out duration (tFOD): keep fault signal (0 V) until recover VCC and CFOD. B3 B2 B7 B4 Restart Output Current High-level (no fault output) All low-side IGBT gate are locked with VFO output. B5 Fault Output Signal Figure 14. Timing Chart of Low-Side Under-Voltage Protection Function Notes: 16. B1-control supply voltage rise: after the voltage rises UVCCR, the circuits starts to operate when the next input is applied. 17. B2-normal operation: IGBT ON and carrying current. 18. B3-under-voltage detection (UVCCD). 19. B4-IGBT OFF in spite of control input is alive. 20. B5-fault output signal starts. 21. B6-under-voltage reset (UVCCR). 22. B7-normal operation: IGBT ON and carrying current. If fault-out duration (tFOD) by external capacitor at CFOD pin is longer than UVCCR timing, fault output and IGBT state are cleared after tFOD. The HVIC has an under-voltage lockout function to protect the high-side IGBT from insufficient gate driving voltage. A timing chart for this protection is shown in Figure 15. A fault-out (FO) alarm is not given for low HVIC bias conditions. Input Signal Protection Circuit State RESET SET UVBSR Control Supply Voltage Needed LOW-to-HIGH input transition to turn on IGBT again. (Edge Trigger) Built-in 11 μs filter to prevent malfunction by noise. RESET Filtering? C1 UVBSD C5 C3 C2 C4 Restart C6 Output Current High-level (no fault output) Fault Output Signal High-side IGBT gate is locked without VFO output. Figure 15. Timing Chart of High-Side Under-Voltage Protection Function Notes: 23. C1-control supply voltage rises: after the voltage reaches UVBSR, the circuit starts when the next input is applied. 24. C2-normal operation: IGBT ON and carrying current. 25. C3-under-voltage detection (UVBSD). 26. C4-IGBT OFF in spite of control input is alive, but there is no fault output signal. 27. C5-under-voltage reset (UVBSR). 28. C6-normal operation: IGBT ON and carrying current. © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 15 AN-9075 APPLICATION NOTE 5. Key Parameter Design Guidance For stable operation, there are recommended parameters for passive components and bias conditions, considering operating characteristics of Motion SPM 2 series. 5.1 Selection of RSC Resistor for Protection Figure 46 shows “RSC resistance vs. trip current” curve of FNA21012A under the shunt resistor=0Ω condition. Figure 16 is an example circuit of the short-circuit protection using the RSC resistor. Sense IGBT is employed for the low side. The designer can use the RSC pin for OverCurrent Protection (OCP) and Short-Circuit Protection (SCP) without an external shunt resistor at the N-terminal. The line current on RSC is detected and the protective operation signal is passed through the RC filter. If the current exceeds the VSC(ref), all the gates of the N-side three IGBTs are turned off and the fault signal is transmitted from Motion SPM 2 to MCU. Since repetitive short circuit is not allowable, IGBT operation should be immediately halted when the fault signal is given. For current sensing, apply an external shunt resistor at each N terminal. Sensing voltage from RSC pin is influenced by an external shunt resistor, as shown in Figure 18. Figure 17 through Figure 22 show RSC value of Motion SPM2 under one-shunt resistor condition. For adequate RSC value in a three-shunt structure, the RSC value needs to be considered by the N-terminal shunt resistor value and target protection current level. HVIC . Level Shift . Gate Drive . UVLO VS VDC 3Ø Motor LVIC VCC . Gate Drive . UVLO . SCP VFO RSC CSC COM VCSC Short Circuit Current (ISC) RF CSC RSC Figure 16. Current Path in Short-Circuit Condition by Leg Short Circuit Trip Current Level@VSC(ref)=0.5V at shunt resistor=0Ω at N terminals 40 TJ = -40℃ TJ = 25℃ TJ = 150℃ 38 36 34 32 30 28 26 IC [A] 24 22 20 18 16 14 12 10 8 6 4 0 10 20 30 40 50 60 70 80 90 100 110 120 130 RSC resistance [Ω ] Figure 17. RSC Resistance vs. Trip Current Level for Protection at Variable Junction Temperature of FNA21012A © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 16 AN-9075 APPLICATION NOTE 38 TJ = -40℃ TJ = 25℃ TJ = 150℃ 36 34 32 30 28 26 IC [A] IC [A] 24 22 20 18 16 14 12 10 8 6 4 0 5 10 15 20 25 30 35 40 45 Trip Current Level@Vsc=0.5V, RSC=68Ω 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 50 TJ = -40℃ TJ = 25℃ TJ = 150℃ IC [A] Trip Current Level@Vsc=0.5V, RSC=30Ω 40 0 5 Shunt Resistor at N terminal [mΩ ] (a) 10 15 20 25 30 35 40 45 Trip Current Level@Vsc=0.5V, RSC=100Ω 40 38 36 34 32 30 28 26 24 22 20 18 16 14 12 10 8 6 4 2 0 50 TJ = -40℃ TJ = 25℃ TJ = 150℃ 0 5 Shunt Resistor at N terminal [mΩ ] 10 15 20 25 30 35 40 45 50 Shunt Resistor at N terminal [mΩ ] (b) Figure 18. Trip Current Level vs. Shunt Resistor of FNA21012A (c) (a): RSC=30 Ω, (b): RSC=68 Ω, (c): RSC=100 Ω IC [A] Trip Current Level@VSC(ref)=0.5V at shunt resistor=0Ω at N terminals 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 Tj=-40C Tj=25C Tj=150C 0 5 10 15 20 25 30 35 40 45 50 55 60 RSC resistance [Ω ] TJ = -40℃ TJ = 25℃ TJ = 150℃ 0 2 4 6 8 10 12 14 16 18 Shunt Resistor at N terminal [mΩ ] (a) 20 Trip Current Level@Vsc=0.5V, RSC=27Ω 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 TJ = -40℃ TJ = 25℃ TJ = 150℃ IC [A] Trip Current Level@Vsc=0.5V, RSC=13Ω 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 IC [A] IC [A] Figure 19. RSC Resistance vs. Trip Current Level for Protection at Variable Junction Temperature of FNA22512A 0 2 4 6 8 10 12 14 16 Shunt Resistor at N terminal [mΩ ] 18 20 Trip Current Level@Vsc=0.5V, RSC=47Ω 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 15 10 TJ = -40℃ TJ = 25℃ TJ = 150℃ 0 2 4 (b) Figure 20. Trip Current Level vs. Shunt Resistor of FNA22512A (a): RSC=13 Ω, (b): RSC=27 Ω, (c): RSC=47 Ω © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 6 8 10 12 14 16 18 20 Shunt Resistor at N terminal [mΩ ] (c) www.fairchildsemi.com 17 AN-9075 APPLICATION NOTE IC [A] Trip Current Level@VSC(ref)=0.5V at shunt resistor=0Ω at N terminals 120 115 110 105 100 95 90 85 80 75 70 65 60 55 50 45 40 35 30 25 20 Tj=-40C Tj=25C Tj=150C 0 5 10 15 20 25 30 35 40 RSC resistance [Ω ] Figure 21. RSC Resistance vs. Trip Current Level for Protection at Variable Junction Temperature of FNA23512A Trip Current Level@Vsc=0.5V, RSC=8.2Ω 120 100 IC [A] IC [A] 80 60 60 40 40 40 20 20 20 0 0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 (a) 0 0 Shunt Resistor at N terminal [mΩ ] TJ = -40℃ TJ = 25℃ TJ = 150℃ 100 80 60 Trip Current Level@Vsc=0.5V, RSC=30Ω 120 TJ = -40℃ TJ = 25℃ TJ = 150℃ 100 80 IC [A] Trip Current Level@Vsc=0.5V, RSC=16Ω 120 TJ = -40℃ TJ = 25℃ TJ = 150℃ 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Shunt Resistor at N terminal [mΩ ] 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Shunt Resistor at N terminal [mΩ ] (b) Figure 22. Trip Current Level vs. Shunt Resistor of FNA23512A (c) (a): RSC=8.2 Ω, (b): RSC=16 Ω, (c): RSC=30 Ω 5.2 Shunt Resistor Selection at N-Terminal for Current Sensing & Protection If using three shunt resistors at N terminals for OCP and SCP without sense detecting from RSC, RSC should be connected to COM. The external RC time constant from the N-terminal shunt resistor to CSC must be lower than 2 µs in short circuit for stable shutdown. P HVIC . Level Shift . Gate Drive . UVLO VS VDC 3Ø Motor The proper shunt resistance can be calculated by simple equations as below. LVIC VCC . Gate Drive . UVLO . SCP VFO 5V Line NW NV Vref. VSC(ref)=min.0.43 V / typ. 0.5 V / max. 0.57 V (see Table 12.) NU RSC CSC COM VCSC CSC Vref. RF RSC RSC should be connected to COM when it is not used for current detection Shunt Resistance: Vref. ISC(max)=VSC(max) / RSHUNT(min) RSHUNT(min)=VSC(max) / ISC(max) Figure 23. Recommended Circuitry for Over-Current & Short-Circuit Protection without RSC Pin Usage © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 If the deviation of shunt resistor is limited below ±5%: RSHUNT(typ) = RSHUNT(min) / 0.95 RSHUNT(max) = RSHUNT(typ) x 1.05 www.fairchildsemi.com 18 AN-9075 APPLICATION NOTE The Actual SC Trip Current Level becomes: ISC(typ)=VSC(typ) / RSHUNT(typ) ISC(min) = VSC(min) / RSHUNT(max) Shunt Resistor Value at TC = 25°C (RSHUNT): 40 mΩ De-rating Ratio of Shunt Resistor at TSHUNT = 100°C: 70% (refer to Figure 46). Inverter Output Power: Safety Margin: 20% VO_LL = Calculation Results: where: ISC(max): 1.5 IC(max) = 1.5 x 10 A = 15 A VO_LL :Inverter Output Lin to Line RSHUNT(min): VSC(max) / ISC(max)=0.57 V / 15 A=38 mΩ MI = Modulation Index RSHUNT(typ): RSHUNT(min) / 0.95 = 38 mΩ / 0.95 = 40 mΩ VDC_Link = DC link voltage RSHUNT(max) : RSHUNT(typ) x 1.05 = 40.0 mΩ x 1.05 = 42 mΩ ISC(min) : VSC(min) / RSHUNT(max) = 0.43 V / 42 mΩ = 10.2 A ISC(typ) : VSC(typ) / RSHUNT(typ) = 0.5 V / 40 mΩ = 12.5 A IDC_AVG = VDC_Link / (Pout Eff) VO_LL = = where: Eff = Inverter efficiency POUT = = The power rating of shunt resistor is calculated by: IDC_AVG = (POUT/Eff) / VDC_Link = 4.64 A PSHUNT = (I POUT = IRMS= Maximum load current of inverter PF = Power Factor Average DC Current: 2 PSHUNT = (I DC_AVG x RSHUNT x Margin) /De-rating Ratio where: IDC_AVG : Average load current of inverter RSHUNT : Shunt resistor typical value at TC=25[°C] De-rating ratio: Shunt resistor at TSHUNT=100[°C] from datasheet of shunt resistor Margin: Safety margin determined by customer’s system. 2 DC_AVG 0.9 0.5600=330.7 330.7 5 0.8 = 2291 W RSHUNT Margin) / Derating Ratio 2 = (4.64 0.040 1.2) / 0.7 = 1.48 W (Therefore, the proper power rating of shunt resistor is over 2 W) Table 13. Operation Short-Circuit Current Range of FNA21012A \ at TJ=25°C (RSHUNT=38 mΩ (Min.), 40 mΩ (Typ.), 42 mΩ (Max.) Example value of shunt resistor calculation: FNA21012A shunt resistor deviation is ±5%. Conditions Min. Typ. Max. Unit Operation SC Level 10 12 15 A Table 12. OCP & SCP Level(VSC(ref)) Specification Conditions Min. Typ. Max. Unit Specification at TJ=25°C, VCC=15 V 0.43 0.50 0.57 V Shunt Resistor Calculation Examples Calculation Conditions: DUT: FNA21012A Tolerance of shunt resistor: ±5% SC Trip Reference Voltage: Figure 24. De-rating Curve Example of Shunt Resistor (from RARA Elec.) VSC(min)=0.43 V, VSC(typ)=0.50 V, VSC(max)=0.57 V Maximum Load Current of Inverter (IRMS): 5 Arms Maximum Peak Load Current of Inverter (IC(max)): 10 A Modulation Index(MI) : 0.9 DC Link Voltage(VDC_Link): 600 V Power Factor(PF): 0.8 Inverter Efficiency(Eff): 0.95 © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 5.3 Time Constant of Internal Delay An RC filter is prevents noise-related Short-Circuit Current Protection (SCP) circuit malfunction. The RC time constant is determined by the applied noise time and the ShortCircuit Current Withstanding Time (SCWT) of Motion SPM 2. When the RSC voltage exceeds the SCP level, this is applied to the CSC pin via the RC filter. The RC filter delay (T1) is the time required for the CSC pin voltage to rise to the referenced SCP level. The LVIC has an internal filter www.fairchildsemi.com 19 AN-9075 APPLICATION NOTE 5.4 Soft Turn-Off time (logic filter time for noise elimination: T2). Consider this filter time when designing the RC filter of VCSC. T1 T2 T3 T4 An LVIC soft turn-off function protects the low side IGBTs from over voltage of VPN (supply voltage) by “short-circuit hard off,” which is when IGBTs are turned off by short input signal before the SCP function under short-circuit condition. In this case, VPN rapidly rises by fast and big di/dt of ISC (short-circuit current). This kind of rapid rise of VPN can cause destruction of IGBT by over-voltage. Therefore, soft-off function prevents IGBT rapid turning off by slow discharging of VGE (gate-to-emitter voltage of IGBT). T5 VIN LOUT VCSC An internal block diagram of LVIC and operation sequence of soft turn-off function is shown in Figure 28 and Figure 28. This function operates by two internal protection functions (UVLO and SCP). When the IGBT is turned off in normal conditions, LVIC turns off the IGBT immediately by turn-off gate signal (IN(xL)) via gate driver block. Pre- ISC VFO Figure 25. Timing Diagram Notes: 29. VIN: Voltage of input signal. 30. LOUT: VGE of low-side IGBT. 31. VCSC: Voltage of CSC pin. 32. ISC: Short-circuit current. 33. VFO: Voltage of VFO pin. 34. T1: filtering time of RC filter of VCSC. 35. T2: filtering time of CSC. If VCSC width is less than T2, SCP does not operate. 36. T3: delay from CSC triggering to gate-voltage down. 37. T4: delay from CSC triggering to short-circuit current. 38. T5: delay from CSC triggering to fault-out signal. driver turns on output buffer of gate driver block(path①) When the IGBT is turned off by a protection function, the gate driver is disabled by the protection function signal via output of protection circuit (disable output buffer, high-Z) and output of the protection circuit turn-on switch of the soft-off function. VGE (IGBT gate-emitter voltage) is discharged slowly via circuit of soft-off (path ②). (Under-Voltage Lock Out) VCC SCP CSC Table 14. Time Table on Short-Circuit Conditions: VCSC to LOUT, ISC, VFO LVIC UVLO VCC Output Buffer (Short-circuit Current Protection) Restart Device Under Test FNA21012A Typ. at TJ=25°C Typ. at TJ=150°C T2=0.25 μs T2=0.09 μs T3=0.62 μs T3=0.57 μs T4=3 μs T4=3.3 μs T5=4.1 μs T5=4.25 μs Max. at TJ=25°C IN(xL) LO Pre Driver Delay 5.0K Gate Driver Considering ±20% deviation, T4=3.6 μs COM Protection Circuit Soft-off Timer VFO TSU CFOD TSU Figure 26. Internal Block Diagram of LVIC Notes: 39. To guarantee safe short-circuit protection under all operating conditions, CSC should be triggered within 1.0 μs after short-circuit occurs. (Recommendation: SCWT < 5.0 μs, Conditions: VDC=800 V, VCC=16.5 V, TJ=150°C). 40. It is recommended that delay from short-circuit to CSC triggering should be minimized. LVIC VCC IGBT Gate Driver Pre Driver Restart Output Buffer On Off Low-Side IGBT Off On VGE ① Soft-off Off On ② VFO Figure 27. Operating Sequence of Soft Turn-Off © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 20 AN-9075 APPLICATION NOTE Figure 28 and Figure 29 show normal turn-off switching operations performed satisfactorily at a VDC=800 V with the surge voltage between the P and N pins (VPN(Surge)) limited to under 1000 V. The difference between the hard and soft turn-off switching operation is also shown in Figure 28 and Figure 29. The hard turn-off of the IGBT creates a large overshoot (155 V). The DC-link capacitor supply voltage should be limited to 800 V to safely protect the 1200 V Motion SPM 2. A hard turn-off, with a duration of less than ~2 μs, may occur in the case of a short-circuit fault. For a normal short-circuit fault, the protection circuit becomes active and the IGBT is turned off softly to prevent excessive overshoot voltage. An overshoot voltage of <100 V occurs in this condition. Because VFO terminal is an open-drain type; it should be pulled up via a pull-up resistor. The resistor must satisfy the above specifications. 0.40 o TJ=150[ C] 0.35 0.30 VFO [V] 0.25 0.20 0.15 0.10 0.05 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 IFO [mA] Figure 30. Voltage-Current Characteristics of VFO Terminal LIN [5V/div.] 5.6 Circuit of Input Signal (IN(xH), IN(xL)) VCE(SURGE)=155V IC [5A/div.] Figure 28 shows the I/O interface circuit between the MCU and Motion SPM 2. Because the Motion SPM 2 input logic is an active HIGH and there are built-in pull-down resistors, external pull-down resistors are not needed. Turn-off by LIN 5V-Line MCU VPN [200V/div.] Motion SPM 2 RPF=4.7kΩ Time [200ns/div] IN(UH), IN(VH), IN(WH) Input Noise Filter Level-Shift Circuit Gate Driver Typ. 5 k Figure 28. Turn-Off by Input (FNA21012A, Ref. Condition: VDC=600 V, TJ=25°C) IN(UL), IN(VL), IN(WL) Typ. 5 k Input Noise Filter Gate Driver tIN(FLT) = Typ. 450 ns for turn on Typ. 250 ns for turn off VFO CPF=1nF COM VCE(SURGE)=90V Figure 31. Recommended CPU I/O Interface Circuit The input and fault output maximum rated voltages are shown in Figure 46. Since the fault output is open drain, its rating is VCC+0.3 V, 15 V supply interface is possible. However, it is recommended that the fault output be configured with the 5 V logic supplies, which is the same as the input signals. It is also recommended that the decoupling capacitors be placed at both the MCU and Motion SPM 2 ends of the VFO signal line, as close as possible to each device. The RC coupling at each input (parts shown dotted in Figure 46) can be changed depending on the PWM control scheme used in the application and the wiring impedance of the PCB layout. Turn-off by Protection Figure 29. Turn-Off by Soft Off Function (FNA21012A, Ref. Condition: VDC=600 V, TJ=25°C) 5.5 Fault Output Circuit Table 15. Fault-Output Maximum Ratings Symbol Item Condition Rating Unit VFO Fault Output Supply Voltage Applied between VFO-COM -0.3 ~ VCC+0.3 V IFO Fault Output Current Sink Current at VFO Pin 2 mA The input signal section of the Motion SPM 2 series integrates a 5 kΩ (typical) pull-down resistor. Therefore, when using an external filtering resistor between the MCU output and the Motion SPM 2 input, attention should be given to the signal voltage drop at the Motion SPM 2 input terminals to satisfy the turn-on threshold voltage requirement. Table 16. Electric Characteristics Symbol Item Conditions Min. VFOH Fault Output Supply Voltage VCC=15 V, VSC=0, VFO Circuit: 4.7 kΩ to 5 V Pull-Up 4.5 VFOL © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 Max. Unit V 0.5 V www.fairchildsemi.com 21 AN-9075 APPLICATION NOTE Table 17. Maximum Ratings of Input and VFO Pins Symbol Item Condition VIN Input Signal Voltage Applied between -0.3 ~ IN(xH), IN(xL)VCC +0.3 COM(x) V VFO Fault Output Supply Voltage Applied between -0.3 ~ VFO-COM(L) VCC +0.3 V 5.7.2. Selection of Bootstrap Capacitor Considering Initial Charging Rating Unit Adequate on-time of the low-side IGBT to fully charge the bootstrap capacitor is required for initial bootstrap charging. The initial charging time (tcharge) can be calculated by: tcharge = CB Item Condition Min. Max. Unit VIN(ON) Turn-On Threshold Voltage IN(UH), IN(VH), IN(WH)-COM(H) 2.6 VIN(OFF) Turn-Off Threshold Voltage IN(UL), IN(VL), IN(WL)-COM(L) 0.8 V V 5.7.1. Operation of Bootstrap Circuit The VBS voltage, which is the voltage difference between VB (U, V, W) and VS (U, V, W), provides the supply to the HVIC within the Motion SPM 2 series. This supply must be in the range of 13.0 V~18.5 V to ensure that the HVIC can fully drive the high-side IGBT. The under-voltage lockout protection for VBS ensures that the HVIC does not drive the high-side IGBT if the VBS voltage drops below a specific voltage (refer to the datasheet). This function prevents the IGBT from operating in a high-dissipation mode. Motion SPM 2 CBS VCC VB min) VF VL Figure 34 shows an example of initial bootstrap charging sequence. Once VCC establishes, VBS needs to be charged by turning on the low-side IGBTs. PWM signals are typically generated by an interrupt triggered by a timer with a fixed interval, based on the switching carrier frequency. Therefore, it is desired to maintain this structure without creating complementary high-side PWM signals. The capacitance of VCC should be sufficient to supply necessary charge to VBS capacitance in all three phases. If a normal PWM operation starts before VBS reaches VUVLO reset level, the high-side IGBTs cannot switch without creating a fault signal. It may lead to a failure of motor start in some applications. If three phases are charged synchronously, initial charging current through a single shunt resistor may exceed the over-current protection level. Therefore, initial charging time for bootstrap capacitors should be separated, as shown in Figure 34. The effect of the bootstrap capacitance factor and charging method (low-side IGBT driving method) is shown in Figure 35. There are a number of ways in which the VBS floating supply can be generated. One of them is the bootstrap method described here (refer to Figure 32). This method has the advantage of being simple and inexpensive. However, the duty cycle and on-time are limited by the requirement to refresh the charge in the bootstrap capacitor. The bootstrap supply is formed by a combination of a bootstrap diode, resistor, and capacitor. The current flow path of the bootstrap circuit is shown in Figure 32. When VS is pulled down to ground (low-side IGBT turn-on or low-side FRD freewheeling), the bootstrap capacitor (CBS) is charged through the bootstrap diode (DBS) and the resistor (RBS) from the VCC supply. VBD VCC VCC VB When the bootstrap capacitor is charged initially; VCC drop voltage is generated based on initial charging method, V CC line SMPS output current, VCC source capacitance, and bootstrap capacitance. If VCC drop voltage reaches UVCCD level, the low side is shutdown and a fault signal is activated. To avoid this malfunction, related parameter and initial charging method should be considered. To reduce VCC voltage drop at initial charging, a large VCC source capacitor and selection of optimized low-side turn-on method are recommended. Adequate on-time duration of the low-side IGBT to fully charge the bootstrap capacitor is initially required before normal operation of PWM starts. 5.7 Bootstrap Circuit Design RBS ln where: VF = Forward voltage drop across the bootstrap diode; VBS(min) =The minimum value of the bootstrap capacitor; VLS = Voltage drop across the low-side IGBT or load; and = Duty ratio of PWM. Table 18. Input Threshold Voltage Ratings (VCC=15 V, TJ=25°C) Symbol 1 B DBS(Integrated) P VB VCC(H) VCC HVIC COM(H) COM HO VDC VS VS VCC(L) CVCC VCC LVIC COM(L) LO COM N RSC Figure 32. Current Path of Bootstrap Circuit for the Supply Voltage (VBS) of a HVIC when Low-Side IGBT Turns On © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 22 AN-9075 APPLICATION NOTE VPN VDC 0V VCC VCC 0V Bootstrap capacitor charging(W phase) … IN(WL) VBS 0V Section of charge pumping for VBS : Switching or Full Turn on … Bootstrap capacitor charging(V phase) ON VIN(L) … … IN(VL) 0V Start PWM Bootstrap capacitor charging(U phase) VIN(H) Bootstrap capacitor charging period Figure 33. Timing Chart of Initial Bootstrap Charging … … IN(UL) OFF 0V System operating periode Figure 34. Recommended Initial Bootstrap Capacitors Charging Sequence IN(WL, VL, UL) [5V/div.] VFO is activated by UVCCD VFO [5V/div.] CBS=33µF VCC [5V/div.] CBS=100µF VB-VS [5V/div.] All low side turns on at a same time All low side turns on at a same time Time [2ms/div.] VFO is activated by UVCCD CBS=100µF CBS=100µF All low side turns on at a same time Only one low side turns on VFO is activated by UVCCD CBS=100µF CBS=100µF All low side turns on with fSW=5kHz, Duty=50% All low side turns on with fSW=5kHz, Duty=25% Figure 35. Initial Charging According to Bootstrap Capacitance and Charging Method (Ref. Condition: VCC=15 V/300 mA, VCC Capacitor=220 µF, Bootstrap Capacitor=100 µF, RBS=20 Ω) © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 23 AN-9075 APPLICATION NOTE Based on switching frequency and recommended ΔVBS 5.7.3. Selection of Bootstrap Capacitor Considering Operating The bootstrap capacitance can be calculated by: where: t: maximum on pulse width of high-side IGBT; VBS: the allowable discharge voltage of the CBS (voltage ripple) ILeak: maximum discharge current of the CBS. VBS: discharged voltage = 0.1 V (recommended value) t: maximum on pulse width of high-side IGBT = 0.2 ms (depends on application) More than 2 times 18 μF(22μF STD value) Mainly via the following mechanisms: ILeak: circuit current = 4.5 mA (For FNA21012A, refer to the Figure 28) Table 19. Operating VBS Supply Current Gate charge for turning the high-side IGBT on Symbol Quiescent current to the high-side circuit in HVIC Level-shift charge required by level-shifters in HVIC IPBS Leakage current in the bootstrap diode CBS capacitor leakage current (ignored for non-electrolytic capacitors) Practically, 4.5 mA of ILeak is recommended for the Motion SPM 2 family. By considering dispersion and reliability, the capacitance is generally selected to be 2~3 times the calculated one. The CBS is only charged when the high-side IGBT is off and the VS(x) voltage is pulled down to ground. Minimum Value Recommend Value Commercial Capacitance 90 Bootstrap Capacitance, CBS [F] 4.5 FNA22512A 9.0 FNA23512A 12.0 To avoid unexpected under-voltage protection and to keep VBS within recommended value, bootstrap capacitance should be selected based on the operating conditions. Bootstrap voltage ripple is influenced by bootstrap resistor, load condition, output frequency, and switching frequency. Check the bootstrap voltage under the maximum load condition in the system. Figure 37 shows example of VB(x)VS(x) ripple voltage during operation. Conditions : VBS=0.1 [V], ILeak=4.5 [mA] 80 FNA21012A Unit Based on operating conditions, UVBS function, and allowable recommended VB(x)-VS(x). Calculation Examples of Bootstrap Capacitance A 100[F] Max. Calculation Examples of Bootstrap Capacitance B The on-time of the low-side IGBT must be sufficient to for the charge drawn from the CBS capacitor to be fully replenished. This creates an inherent minimum on-time of the low-side IGBT (or off-time of the high-side IGBT). 100 VCC = VBS = 15 V, fPWM = 20 kHz, Duty = 50%, Applied to one PWM Signal Input for High-Side Device Note: 41. The capacitance value can be changed according to the switching frequency, the capacitor selected, and the recommended VBS voltage of 13.0~18.5 V (from datasheet). The above result is just a calculation example. This value can be changed according to the actual control method and lifetime of the component. Bootstrap diode reverse recovery charge 110 Conditions CBS_min=(ILeak*t)/VBS 70 Continuous Sinusoidal Current Control 60 47[F] 50 40 33[F] 30 22[F] 20 10[F] 10 6.8[F] 0 0 2 4 6 8 10 12 14 16 18 20 Switching Frequency, FSW [kHz] Figure 36. Capacitance of Bootstrap Capacitor on Variation of Switching Frequency Figure 37. Recommendation of Bootstrap Ripple Voltage during Operation © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 24 mA AN-9075 APPLICATION NOTE I-V characteristics of integrated bootstrap diode without series resistor 5.8 Built-in Bootstrap Diode 3.0 When the high-side IGBT or FRD conducts, the bootstrap diode (DBS) supports the entire bus voltage. A withstand voltage of more than 1200 V is recommended for the bootstrap diode. It is important that this diode should be fast recovery (recovery time<100 ns) to minimize the amount of charge fed back from the bootstrap capacitor into the V CC supply. Normally, bootstrap circuit consists of bootstrap diode (DBS), bootstrap resistor (RBS), and bootstrap capacitor (CBS). I-V characteristics of Motion SPM 2 bootstrap diode are shown in Figure 38 and Figure 39. The bootstrap resistor (RBS) slows down the dVBS/dt and limits initial charging current (Icharge) of bootstrap capacitor. To prevent large inrush current at initial bootstrap capacitor charging, an additional series resistor should be used for current limitation. Large inrush current can result in over-current protection and stress of bootstrap diode. Guaranteed pulse current of bootstrap diode is limited by 2 A; therefore, minimum 10 Ω series resistor should be used for the current limitation. Generally, tens of Ω is recommended as RBS. For the selection of RBS, pulse power rating should be considered for initial charging of bootstrap capacitor. To use a large bootstrap capacitor, high pulse power rating is required for the bootstrap resistor. An example of resistor pulse power rating is shown in Figure 40. TJ=-40℃ TJ=25℃ 2.5 TJ=100℃ TJ=125℃ 2.0 IF [A] TJ=150℃ 1.5 1.0 0.5 0.0 0.0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 2.4 2.7 3.0 VF [V] Figure 38. I-V Characteristics of Integrated Bootstrap Diode Series without Series Resistor I-V characteristics of integrated bootstrap diode with series resistor 1.0 RBS=20ohm, TJ=25℃ 0.9 0.8 0.7 0.07 0.6 If [A] 0.06 0.5 Main Operating Area of Bootstrap Circuit 0.05 0.4 IF [A] 0.04 0.3 0.03 0.02 The characteristics of Motion SPM 2 bootstrap diode are: Fast recovery diode: 1200 V/1 A 0.2 0.0 Zoom in 0.1 trr: 80 ns (typical) 0.01 0.00 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 VF [V] 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Vf [V] Table 20. Specification for Bootstrap Diode Symbol Parameter Conditions VF Forward-Drop Voltage IF=1 A, TC=25°C 2.2 V trr ReverseRecovery Time IF=1 A, TC=25°C, dIF/dt=50 A/µs 80 ns Figure 39. I-V Characteristics of Integrated Bootstrap Diode Series with Series Resistor Typ. Unit Figure 40. Example of Pulse Power Curve of Resistor (from KAMAYA OHM) © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 25 AN-9075 APPLICATION NOTE 5.9 Circuit of NTC Thermistor (Temperature Monitoring of Module) 600 MIN TYP MAX 550 Motion SPM 2 series include a Negative Temperature Coefficient (NTC) thermistor for temperature sensing inside the module. This thermistor is located in the DBC substrate with the power chip (IGBT/FRD) and accurately reports the temperature of the power chip (see Figure 42.). Normally, circuit designers use twp kinds of circuit for temperature protection (monitoring) by NTC thermistor. One is circuit by Analog-Digital Converter (ADC). The other is circuit by comparator. Figure 44 and Figure 45 show examples of both circuits for NTC thermistor. 500 Resistance[kΩ ] 450 400 350 300 250 200 150 100 50 0 -20 -10 0 10 20 30 40 50 60 70 80 90 100 110 120 Temperature TTH[℃] Figure 43. R-T Curve of NTC Thermistor VDD NTC VTH RTH ADC Port MCU Motion SPM 2 RTH Figure 44. OT Protection Circuit by MCU VDD VDD NTC VTH R1 R3 RTH I/O Port MCU Motion SPM 2 C2 R2 RTH C1 Figure 45. OT Protection Circuit by Comparator Figure 41. 1200-V Motion SPM 2 5 Output Voltage of RTH [V] RTH VTH NV NU CFOD VFO IN(WL) IN(VL) IN(UL) COM(L) VCC(L) CSC RSC NTC Thermistor VBD(U) VCC(UH) COM(H) IN(UH) VB(U) VS(U) IN(VH) VBD(V) VCC(VH) VB(V) VS(U) IN(WH) VBD(W) VCC(WH) VS(W) VB(W) FNA210xxA DXX XXXX NW U V P W VOUT(min) VOUT(typ) 4 VOUT(max) VDD=5.0V 3 VDD=3.3V 2 1 V-T Curve at VDD=5.0, 3.3V, RTH=6.8kohm 0 20 Figure 42. Location of NTC Thermistor in 1200-V Motion SPM 2 30 40 50 60 70 80 90 100 110 120 o Temperature TThermistor[ C] Figure 46. V-T Curve of Figure 44 © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 26 AN-9075 APPLICATION NOTE Table 21. R-T Table of NTC Thermistor TNTC (°C) Rmin (kΩ) Rcent (kΩ) Rmax (kΩ) TNTC (°C) Rmin (kΩ) Rcent (kΩ) Rmax (kΩ) 0 153.8063 158.2144 162.7327 61 10.4594 10.8007 11.1520 1 146.0956 150.1651 154.3326 62 10.0746 10.4091 10.7536 2 138.8168 142.5725 146.4152 63 9.7058 10.0336 10.3714 3 131.9431 135.4081 138.9502 64 9.3522 9.6734 10.0046 4 125.4497 128.6453 131.9091 65 9.0133 9.3279 9.6525 5 119.3135 122.2594 125.2655 66 8.6882 8.9963 9.3145 6 113.5129 116.2273 118.9947 67 8.3764 8.6782 8.9899 7 108.0276 110.5275 113.0739 68 8.0773 8.3727 8.6782 8 102.8388 105.1398 107.4814 69 7.7902 8.0795 8.3787 9 97.9288 100.0454 102.1974 70 7.5147 7.7979 8.0910 10 93.2812 95.2267 97.2031 71 7.2496 7.5268 7.8138 11 88.8803 90.6673 92.4810 72 6.9950 7.2663 7.5474 12 84.7119 86.3519 88.0148 73 6.7505 7.0160 7.2913 13 80.7624 82.2661 83.7894 74 6.5157 6.7755 7.0450 14 77.0190 78.3963 79.7903 75 6.2901 6.5443 6.8082 15 73.4700 74.7302 76.0043 76 6.0739 6.3227 6.5810 16 70.1042 71.2558 72.4189 77 5.8662 6.1096 6.3624 17 66.9112 67.9620 69.0224 78 5.6665 5.9046 6.1521 18 63.8812 64.8386 65.8039 79 5.4745 5.7075 5.9498 19 61.0050 61.8759 62.7530 80 5.2899 5.5178 5.7549 20 58.2739 59.0647 59.8601 81 5.1129 5.3358 5.5680 21 55.6798 56.3961 57.1160 82 4.9426 5.1607 5.3879 22 53.2152 53.8628 54.5127 83 4.7788 4.9921 5.2145 23 50.8732 51.4569 52.0422 84 4.6211 4.8299 5.0475 24 48.6469 49.1715 49.6969 85 4.4694 4.6736 4.8866 25 46.5300 47.0000 47.4700 86 4.3228 4.5226 4.7310 26 44.4567 44.9360 45.4159 87 4.1817 4.3771 4.5811 27 42.4868 42.9737 43.4618 88 4.0459 4.2369 4.4366 28 40.6147 41.1075 41.6021 89 3.9150 4.1019 4.2973 29 38.8351 39.3323 39.8319 90 3.7890 3.9717 4.1629 30 37.1428 37.6431 38.1463 91 3.6675 3.8463 4.0334 31 35.5329 36.0351 36.5408 92 3.5505 3.7253 3.9084 32 34.0011 34.5041 35.0111 93 3.4377 3.6087 3.7879 33 32.5433 33.0462 33.5534 94 3.3290 3.4963 3.6716 34 31.1555 31.6573 32.1640 95 3.2242 3.3878 3.5593 35 29.8340 30.3339 30.8392 96 3.1235 3.2836 3.4515 36 28.5760 29.0734 29.5764 97 3.0264 3.1830 3.3473 37 27.3776 27.8717 28.3720 98 2.9328 3.0860 3.2468 38 26.2356 26.7260 27.2228 99 2.8425 2.9923 3.1497 39 25.1472 25.6332 26.1261 100 2.7553 2.9019 3.0559 40 24.1094 24.5907 25.0792 101 2.6712 2.8146 2.9654 41 23.1198 23.5960 24.0796 102 2.5901 2.7303 2.8779 42 22.1759 22.6466 23.1249 103 2.5117 2.6489 2.7933 © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 27 AN-9075 APPLICATION NOTE TNTC (°C) Rmin (kΩ) Rcent (kΩ) Rmax (kΩ) TNTC (°C) Rmin (kΩ) Rcent (kΩ) Rmax (kΩ) 43 21.2753 21.7401 22.2129 104 2.4360 2.5703 2.7117 44 20.4158 20.8746 21.3416 105 2.3630 2.4943 2.6327 45 19.5953 20.0478 20.5088 106 2.2921 2.4206 2.5560 46 18.8120 19.2580 19.7126 107 2.2236 2.3493 2.4819 47 18.0638 18.5032 18.9514 108 2.1575 2.2805 2.4102 48 17.3492 17.7818 18.2234 109 2.0936 2.2139 2.3409 49 16.6663 17.0921 17.5269 110 2.0319 2.1496 2.2739 50 16.0137 16.4325 16.8605 111 1.9725 2.0877 2.2094 51 15.3899 15.8016 16.2227 112 1.9151 2.0278 2.1470 52 14.7934 15.1981 15.6122 113 1.8596 1.9699 2.0866 53 14.2230 14.6205 15.0277 114 1.8060 1.9139 2.0282 54 13.6773 14.0677 14.4678 115 1.7541 1.8598 1.9716 55 13.1552 13.5385 13.9316 116 1.7042 1.8076 1.9171 56 12.6556 13.0318 13.4178 117 1.6559 1.7572 1.8644 57 12.1774 12.5465 12.9255 118 1.6092 1.7083 1.8134 58 11.7195 12.0815 12.4536 119 1.564 1.6611 1.7639 59 11.2810 11.6361 12.0011 120 1.5203 1.6153 1.7161 60 10.8610 11.2091 11.5673 © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 28 AN-9075 APPLICATION NOTE 6. Print Circuit Board (PCB) Design 6.1 General Application Circuit Example Figure 47 shows a general application circuitry of interface schematic with control signals connected directly to a MCU. Figure 48 shows guidance of PCB layout for Motion SPM 2. 15V line (33) VB(W) P (1) VB R1 20R, 1/4W (32) VBD(W) (31) VCC(WH) C22 104 R2 100R, 1/8W Gating WH C1 47uF 35V VCC C2 104 D1 1N 4749A (30) IN(WH) (34) VS(W) C3 102 (28) VB(V) R3 20R, 1/4W R4 100R, 1/8W Gating WH IN VS W (2) VB (27) VBD(V) (26) VCC(VH) C23 104 OUT COM C4 47uF 35V C5 104 D2 1N 4749A (25) IN(VH) (29) VS(V) C6 102 VCC OUT COM IN VS V (3) Motor C21 104 VDC (23) VB(U) VB R5 20R, 1/4W (22) VBD(U) (21) VCC(UH) C24 104 R6 100R, 1/8W Gating WH C8 104 D3 1N 4749A C19 100uF 16V (20) COM(H) (19) IN(UH) (24) VS(U) C9 102 5V line C20 104 C7 47uF 35V R12 1.0K 1/8W VCC OUT COM IN VS (17) CSC OUT(UL) C(SC) R10 5.1K 1/8W C16 222 C15 202 NW (5) (16) CFOD C(FOD) R11 100R, 1/8W (15) VFO Fault C13 102 U (4) VFO C14 102 R7 (14) IN(WL) IN(WL) Gating WL R8 OUT(VL) NV (6) (13) IN(VL) IN(VL) Gating VL R9 (12) IN(UL) IN(UL) Gating UL R7~9: 100R, 1/8W C10~12: 102 C10 ~ C12 (11) COM(L) OUT(WL) COM NU (7) (10) VCC(L) C17 220uF 35V C18 104 5V line VTH (9) VCC D4 1N4749A (18) RSC R13 100R RTH (8) Temp Monitoring RTH C26 102 RSC Figure 47. General Application Circuitry for Motion SPM 2 © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 29 30 Isolation distance between high voltage. (Recommend insert PCB cutting) In the short-circuit protection circuit, please select the RC time constant in the range 1.5~ 2usec. To MCU and Power Source 472 100 100 100 100 100 24V 1.0W 47uF 35V 20R 47uF 35V 20R 47uF 35V 20R 82R 202 VS(W) VB(W) VCC(WH) VBD(W) IN(WH) VS(U) VB(V) VCC(VH) VBD(V) IN(VH) VS(U) VB(U) IN(UH) COM(H) VCC(UH) VBD(U) RSC CSC VCC(L) COM(L) IN(UL) IN(VL) IN(WL) VFO CFOD Th VTH P W V U NW NV NU RTH 682 Main Electrolytic Capacitor The main electrolytic capacitor should be placed to snubber capacitor as close as possible Power Source Copper Snubber Capacitor Connect to Moter Place sunbber capacitor between P and N and closely to terminals Power GND Copper Large DIP SPM (SPM2 PKG) Design for PCB Layout (Direct coupling) Capacitor and Zener diode should be placed closely to terminals GND 15V 5V NTC Fault WL VL UL WH VH 100 24V 1.0W a © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 24V 1.0W a UH 24V 1.0W a The VIN RC filter should be placed to SPM as close as possible. The capacitor and Zener between It is Recommend to connect control GND And Power GND at only Wiring pattern inductance should a point. (Don’t used copper pattern and don’t make a close loop in be minimized (Recommend less Vcc and COM should be placed to SPM as close as possible. than 10nH) GND pattern) And this wiring should be as short as possible AN-9075 APPLICATION NOTE 6.2 PCB Layout Guidance Figure 48. Print Circuit Board (PCB) Layout Guidance for Motion SPM 2 www.fairchildsemi.com AN-9075 APPLICATION NOTE 7. Packing Information Figure 49. Packing Information © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 www.fairchildsemi.com 31 AN-9075 APPLICATION NOTE Related Resources AN-9076 — 1200-V Motion SPM 2 Series Mounting Guidance AN-9079 —1200-V Motion SPM 2 Series Thermal Performance by Mounting Torque FNA21012A Product Information FNA22512A Product Information FNA23512A Product Information DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. LIFE SUPPORT POLICY FAI CHILD’ P ODUCT A E NOT AUTHO IZED FO U E A C ITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. © 2014 Fairchild Semiconductor Corporation Rev. 1.2 • 4/6/15 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com 32