HUF76639S3ST_F085
July 2012
50A, 100V, 0.026 Ohm, N-Channel, Logic
Level UltraFET® Power MOSFET
Packaging
JEDEC TO-263AB
DRAIN
(FLANGE)
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.026Ω, VGS = 10V
• Simulation Models
- Temperature Compensated PSPICE® and SABER™
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.fairchildsemi.com
GATE
SOURCE
HUF76639S3S
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
• Switching Time vs RGS Curves
Symbol
D
Ordering Information
PART NUMBER
G
HUF76639S3ST_F085
S
Absolute Maximum Ratings
PACKAGE
BRAND
TO-263AB
76639S
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUF76639S3ST.
TC = 25oC, Unless Otherwise Specified
HUF76639S3ST_F085
UNITS
Drain to Source Voltage (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
100
V
Drain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
100
V
Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
±16
V
Drain Current
Continuous (TC = 25oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 25oC, VGS = 10V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 5V) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TC = 100oC, VGS = 4.5V) (Figure 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . IDM
50
51
35
34
Figure 4
A
A
A
A
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . UIS
Figures 6, 17, 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
180
1.2
W
W/oC
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
-55 to 175
oC
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TL
Package Body for 10s, See Techbrief TB334. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
300
260
oC
oC
NOTES:
1. TJ = 25oC to 150oC.
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
Product reliability information can be found at http://www.fairchildsemi.com/products/discrete/reliability/index.html
For severe environments, see our Automotive HUFA series.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Electrical Specifications
TC = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
ID = 250µA, VGS = 0V (Figure 12)
100
-
-
V
ID = 250µA, VGS = 0V , T C = -40oC (Figure 12)
90
-
-
V
VDS = 95V, VGS = 0V
-
-
1
µA
VDS = 90V, VGS = 0V, TC = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
Drain to Source On Resistance
rDS(ON)
ID = 51A, VGS = 10V (Figures 9, 10)
-
0.023
0.026
Ω
TO-263
-
-
0.83
oC/W
-
-
62
oC/W
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Case
RθJC
Thermal Resistance Junction to
Ambient
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
tON
td(ON)
-
336
ns
17
-
ns
tr
-
207
-
ns
-
83
-
ns
tf
-
136
-
ns
tOFF
-
-
328
ns
-
-
96
ns
Fall Time
Turn-Off Time
-
td(OFF)
Rise Time
Turn-Off Delay Time
VDD = 50V, ID = 34A
VGS = 4.5V, RGS = 12Ω
(Figures 15, 21, 22)
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
tON
VDD = 50V, ID = 51A
VGS = 10V, RGS = 12Ω
(Figures 16, 21, 22)
-
10
-
ns
tr
-
55
-
ns
td(OFF)
-
151
-
ns
tf
-
110
-
ns
tOFF
-
-
392
ns
td(ON)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 50V,
ID = 35A,
Ig(REF) = 1.0mA
-
71
86
nC
-
39
47
nC
-
2.0
2.4
nC
Gate to Source Gate Charge
Qgs
-
6
-
nC
Gate to Drain “Miller” Charge
Qgd
-
19
-
nC
-
2400
-
pF
-
520
-
pF
-
140
-
pF
MIN
TYP
MAX
UNITS
(Figures 14, 19, 20)
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2012 Fairchild Semiconductor Corporation
SYMBOL
TEST CONDITIONS
ISD = 35A
-
-
1.25
V
ISD = 15A
-
-
1.0
V
trr
ISD = 35A, dISD/dt = 100A/µs
-
-
137
ns
QRR
ISD = 35A, dISD/dt = 100A/µs
-
-
503
nC
VSD
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
1.2
60
1.0
50
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
VGS = 10V
40
VGS = 4.5V
30
20
10
0
0
0
25
50
75
100
125
150
25
175
50
TC , CASE TEMPERATURE (oC)
75
100
125
150
175
TC, CASE TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs CASE
TEMPERATURE
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
CASE TEMPERATURE
2
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
ZθJC, NORMALIZED
THERMAL IMPEDANCE
1
PDM
0.1
t1
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJC x RθJC + TC
SINGLE PULSE
0.01
10-5
10-4
10-3
10-2
10-1
100
101
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
IDM, PEAK CURRENT (A)
1000
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
175 - TC
I = I25
150
VGS = 10V
100
50
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
10-5
10-4
VGS = 5V
10-3
10-2
10-1
100
101
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Typical Performance Curves
(Continued)
500
IAS, AVALANCHE CURRENT (A)
ID, DRAIN CURRENT (A)
300
100
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
10
1ms
1
10ms
SINGLE PULSE
TJ = MAX RATED
TC = 25oC
1
If R = 0
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
100
STARTING TJ = 25oC
10
STARTING TJ = 150oC
1
10
100
300
0.01
0.1
1
10
100
tAV, TIME IN AVALANCHE (ms)
VDS, DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
100
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
VGS = 10V
VGS = 5V
ID, DRAIN CURRENT (A)
ID, DRAIN CURRENT (A)
100
75
50
TJ = 175oC
25
TJ = 25oC
50
VGS = 3V
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
TJ = -55oC
0
0
1.5
2.0
2.5
3.0
3.5
0
4.0
1
VGS, GATE TO SOURCE VOLTAGE (V)
2
3
4
5
VDS, DRAIN TO SOURCE VOLTAGE (V)
FIGURE 7. TRANSFER CHARACTERISTICS
FIGURE 8. SATURATION CHARACTERISTICS
40
3.0
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TC = 25oC
ID = 51A
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
VGS = 3.5V
VGS = 4V
75
35
30
ID = 35A
ID = 15A
25
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 51A
2.5
2.0
1.5
1.0
0.5
20
2
4
6
8
10
VGS, GATE TO SOURCE VOLTAGE (V)
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2012 Fairchild Semiconductor Corporation
-80
-40
0
40
80
120
160
200
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Typical Performance Curves
(Continued)
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
ID = 250µA
1.1
1.0
0.9
0.4
-80
-40
0
40
80
120
160
-80
200
-40
TJ, JUNCTION TEMPERATURE (oC)
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
COSS ≅ CDS + CGD
CRSS = CGD
100
VGS = 0V, f = 1MHz
40
0.1
1
80
120
160
200
10
CISS = CGS + CGD
1000
40
10
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
C, CAPACITANCE (pF)
5000
0
TJ , JUNCTION TEMPERATURE (oC)
VDD = 50V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 51A
ID = 35A
ID = 15A
2
0
100
0
15
30
45
60
75
Qg, GATE CHARGE (nC)
VDS , DRAIN TO SOURCE VOLTAGE (V)
NOTE: Refer to Fairchild Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
400
600
VGS = 4.5V, VDD = 50V, ID = 34A
VGS = 10V, VDD = 50V, ID = 51A
SWITCHING TIME (ns)
SWITCHING TIME (ns)
500
300
tr
200
tf
td(OFF)
100
td(OFF)
400
300
tf
200
tr
100
td(ON)
td(ON)
0
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
©2012 Fairchild Semiconductor Corporation
50
0
10
20
30
40
50
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tf
tr
RL
VDS
90%
90%
+
VGS
VDD
-
10%
10%
0
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2012 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
PSPICE Electrical Model
.SUBCKT HUF76639 2 1 3 ;
rev 26 July 1999
CA 12 8 4.2e-9
CB 15 14 4.2e-9
CIN 6 8 2.27e-9
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
EBREAK 11 7 17 18 118.2
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
10
DBREAK
+
RSLC2
5
51
ESLC
11
-
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
MMED 16 6 8 8 MMEDMOD
GATE
MSTRO 16 6 8 8 MSTROMOD
1
MWEAK 16 21 8 8 MWEAKMOD
+
50
-
LDRAIN 2 5 1.0e-9
LGATE 1 9 5.1e-9
LSOURCE 3 7 3.1e-9
EVTEMP
RGATE +
18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
S1A 6 12 13 8 S1AMOD
S1B 13 12 13 8 S1BMOD
S2A 6 15 14 13 S2AMOD
S2B 13 15 14 13 S2BMOD
RLDRAIN
RSLC1
51
IT 8 17 1
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 15.8e-3
RGATE 9 20 1.94
RLDRAIN 2 5 10
RLGATE 1 9 51
RLSOURCE 3 7 31
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 3.6e-3
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
DRAIN
2
5
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RLSOURCE
S1A
12
S2A
13
8
14
13
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
VBAT 22 19 DC 1
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
ESLC 51 50 VALUE = {(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*99),3.5))}
.MODEL DBODYMOD D (IS = 2.6e-12 RS = 2.65e-3 IKF = 6 TRS1 = 1.5e-3 TRS2 = 3.5e-6 CJO = 2.1e-9 TT = 5.6e-8 M = 0.52)
.MODEL DBREAKMOD D (RS = 2.5e-1 TRS1 = 1e-4 TRS2 = -1e-6)
.MODEL DPLCAPMOD D (CJO = 2.6e-9 IS = 1e-30 M = 0.89 N = 10)
.MODEL MMEDMOD NMOS (VTO = 1.77 KP = 7 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U RG = 1.94)
.MODEL MSTROMOD NMOS (VTO = 2.06 KP = 95 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U)
.MODEL MWEAKMOD NMOS (VTO = 1.48 KP = 0.12 IS = 1e-30 N = 10 TOX = 1 L = 1U W = 1U RG = 19.4 RS = .1)
.MODEL RBREAKMOD RES (TC1 = 1.05e-3 TC2 = -5e-7)
.MODEL RDRAINMOD RES (TC1 = 8.5e-3 TC2 = 2.3e-5)
.MODEL RSLCMOD RES (TC1 = 3.4e-3 TC2 = 2.5e-6)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -1.9e-3 TC2 = -4.5e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.7e-3 TC2 = 1.5e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -4.5 VOFF = -2.0)
.MODEL S1BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -2.0 VOFF = -4.5)
.MODEL S2AMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = -0.5 VOFF = 0.3)
.MODEL S2BMOD VSWITCH (RON = 1e-5 ROFF = 0.1 VON = 0.3 VOFF = -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
SABER Electrical Model
REV 26 July 1999
template huf76639 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
d..model dbodymod = (is = 2.6e-12, cjo = 2.1e-9, tt = 5.6e-8, m = 0.52, n=10)
d..model dbreakmod = ()
d..model dplcapmod = (cjo = 2.6e-9, is = 1e-30, m = 0.89)
m..model mmedmod = (type=_n, vto = 1.77, kp = 7, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.06,kp = 95, is = 1e-30, tox = 1)
m..model mweakmod = (type=_n, vto = 1.48, kp = 0.12,is = 1e-30, tox = 1)
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4.5, voff = -2.0)
sw_vcsp..model s1bmod = (ron = 1e-5, roff = 0.1, von = -2.0, voff = -4.5)
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.3)
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.3, voff = -0.5)
LDRAIN
DPLCAP
10
RSLC1
51
c.ca n12 n8 = 4.2e-9
c.cb n15 n14 = 4.2e-9
c.cin n6 n8 = 2.27e-9
RLDRAIN
RDBREAK
RSLC2
72
ISCL
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
i.it n8 n17 = 1
LGATE
GATE
1
EVTEMP
RGATE + 18 22
9
20
MWEAK
MSTRO
CIN
DBODY
EBREAK
+
17
18
MMED
m.mmed n16 n6 n8 n8 = model = mmedmod, l = 1u, w = 1u
m.mstrong n16 n6 n8 n8 = model = mstrongmod, l = 1u, w = 1u
m.mweak n16 n21 n8 n8 = model = mweakmod, l = 1u, w = 1u
71
11
16
6
RLGATE
res.rbreak n17 n18 = 1, tc1 = 1.05e-3, tc2 = -5e-7
res.rdbody n71 n5 = 2.65e-3, tc1 = 1.5e-3, tc2 = 3.5e-6
res.rdbreak n72 n5 = 2.5e-1, tc1 = 1e-4, tc2 = -1e-6
res.rdrain n50 n16 = 15.8e-3, tc1 = 8.5e-3, tc2 = 2.3e-5
res.rgate n9 n20 = 1.94
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 51
res.rlsource n3 n7 = 31
res.rslc1 n5 n51 = 1e-6, tc1 = 3.4e-3, tc2 = 2.5e-6
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 3.6e-3, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.7e-3, tc2 = 1.5e-6
res.rvthres n22 n8 = 1, tc1 = -1.9e-3, tc2 = -4.5e-6
21
RDBODY
DBREAK
50
-
d.dbody n7 n71 = model = dbodymod
d.dbreak n72 n11 = model = dbreakmod
d.dplcap n10 n5 = model = dplcapmod
l.ldrain n2 n5 = 1.0e-9
l.lgate n1 n9 = 5.1e-9
l.lsource n3 n7 = 3.1e-9
DRAIN
2
5
-
8
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
+
6
8
EGS
19
CB
+
-
-
IT
14
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 118.2
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model = s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model = s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model = s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model = s2bmod
v.vbat n22 n19 = dc = 1
equations {
i (n51->n50) + = iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/99))** 3.5))
}
}
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1
HUF76639S3ST_F085
SPICE Thermal Model
th
JUNCTION
REV 26 July 1999
HUF76639T
CTHERM1 th 6 3.2e-3
CTHERM2 6 5 8.5e-3
CTHERM3 5 4 1.2e-2
CTHERM4 4 3 1.6e-2
CTHERM5 3 2 5.5e-2
CTHERM6 2 tl 1.5
RTHERM1
RTHERM1 th 6 8.0e-3
RTHERM2 6 5 6.8e-2
RTHERM3 5 4 9.2e-2
RTHERM4 4 3 2.0e-1
RTHERM5 3 2 2.4e-1
RTHERM6 2 tl 5.2e-2
RTHERM2
CTHERM1
6
CTHERM2
5
RTHERM3
CTHERM3
SABER Thermal Model
SABER thermal model HUF76639T
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 6 = 3.2e-3
ctherm.ctherm2 6 5 = 8.5e-3
ctherm.ctherm3 5 4 = 1.2e-2
ctherm.ctherm4 4 3 = 1.6e-2
ctherm.ctherm5 3 2 = 5.5e-2
ctherm.ctherm6 2 tl = 1.5
rtherm.rtherm1 th 6 = 8.0e-3
rtherm.rtherm2 6 5 = 6.8e-2
rtherm.rtherm3 5 4 = 9.2e-2
rtherm.rtherm4 4 3 = 2.0e-1
rtherm.rtherm5 3 2 = 2.4e-1
rtherm.rtherm6 2 tl = 5.2e-2
}
4
RTHERM4
CTHERM4
3
RTHERM5
CTHERM5
2
RTHERM6
CTHERM6
tl
©2012 Fairchild Semiconductor Corporation
CASE
HUF76639S3ST_F085 Rev. C1
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Rev. I61
©2012 Fairchild Semiconductor Corporation
HUF76639S3ST_F085 Rev. C1