REI Datasheet SN54ALS161B, ‘ALS162B, ‘ALS163B, ‘AS161, ‘AS163 SN74ALS161B, ‘ALS163B, ‘AS161, ‘AS163 Synchronous 4-Bit Decade and Binary Counters These synchronous, presettable, 4-bit decade and binary counters feature an internal carry lookahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The ‘ALS161B, ‘ALS163B, ‘AS161, and ‘AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. Rochester Electronics Manufactured Components Rochester branded components are manufactured using either die/wafers purchased from the original suppliers or Rochester wafers recreated from the original IP. All recreations are done with the approval of the OCM. Parts are tested using original factory test programs or Rochester developed test solutions to guarantee product meets or exceeds the OCM data sheet. Quality Overview • • • • ISO-9001 AS9120 certification Qualified Manufacturers List (QML) MIL-PRF-38535 • Class Q Military • Class V Space Level Qualified Suppliers List of Distributors (QSLD) • Rochester is a critical supplier to DLA and meets all industry and DLA standards. Rochester Electronics, LLC is committed to supplying products that satisfy customer expectations for quality and are equal to those originally supplied by industry manufacturers. The original manufacturer’s datasheet accompanying this document reflects the performance and specifications of the Rochester manufactured version of this device. Rochester Electronics guarantees the performance of its semiconductor products to the original OEM specifications. ‘Typical’ values are for reference purposes only. Certain minimum or maximum ratings may be based on product characterization, design, simulation, or sample testing. © 2013 Rochester Electronics, LLC. All Rights Reserved 10252013 To learn more, please visit www.rocelec.com SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 D D D D D Internal Look-Ahead Circuitry for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Package Options Include Plastic Small-Outline (D) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Standard Plastic (N) and Ceramic (J) DIPs SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 . . . J PACKAGE SN74ALS161B, SN74AS161, SN74AS163 . . . D OR N PACKAGE SN74ALS163B . . . D, DB, OR N PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND description These counters are fully programmable; they can be preset to any number between 0 and 9 or 15. Because presetting is synchronous, setting up a low level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK CLR NC VCC RCO SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 . . . FK PACKAGE (TOP VIEW) A B NC C D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QA QB NC QC QD ENP GND NC LOAD ENT These synchronous, presettable, 4-bit decade and binary counters feature an internal carry look-ahead circuitry for application in high-speed counting designs. The SN54ALS162B is a 4-bit decade counter. The ’ALS161B, ’ALS163B, ’AS161, and ’AS163 devices are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock input waveform. 1 NC – No internal connection The clear function for the ’ALS161B and ’AS161 devices is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, LOAD, or enable inputs. The clear function for the SN54ALS162B, ’ALS163B, and ’AS163 devices is synchronous, and a low level at CLR sets all four of the flip-flop outputs low after the next clock pulse, regardless of the levels of the enable inputs. This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear the counter to 0000 ( LLLL ). The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. ENP and ENT inputs and a ripple-carry (RCO) output are instrumental in accomplishing this function. Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. RCO, thus enabled, Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 2000, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. On products compliant to MIL-PRF-38535, all parameters are tested unless otherwise noted. On all other products, production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 description (continued) produces a high-level pulse while the count is maximum (9 or 15, with QA high). The high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, and SN54AS163 are characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS161B, SN74ALS163B, SN74AS161, and SN74AS163 are characterized for operation from 0°C to 70°C. logic symbols† ’ALS161B AND ’AS161 BINARY COUNTERS WITH DIRECT CLEAR 1 CLR 9 LOAD ENT ENP CLK A B C D 10 7 2 3 4 5 6 ’ALS163B AND ’AS163 BINARY COUNTERS WITH SYNCHRONOUS CLEAR CTRDIV16 CT=0 M1 M2 15 3CT=15 RCO ENT G4 ENP C5/2,3,4+ CLK 14 [1] 13 [2] 12 [4] 11 [8] 9 M1 M2 LOAD G3 1, 5D CTRDIV16 5CT=0 1 CLR QA A QB B QC C QD D 10 7 9 LOAD ENT ENP CLK A B C D 10 7 2 3 4 5 6 M1 M2 C5/2,3,4+ 3 1, 5D [1] 4 [2] 5 [4] 6 3CT=9 [8] 15 G4 C5/2,3,4+ [1] [2] [4] [8] 14 13 12 11 † These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, DB, J, and N packages. 2 RCO G3 1, 5D POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 RCO G4 2 CTRDIV10 5CT=0 1 15 G3 SN54ALS162B DECADE COUNTER WITH SYNCHRONOUS CLEAR CLR 3CT=15 QA QB QC QD 14 13 12 11 QA QB QC QD SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 logic diagram (positive logic) LOAD ENT ENP CLR CLK 9 SN54ALS162B 10 15 7 RCO 1 2 C1 14 QA 1D A 3 C1 13 QB 1D B 4 C1 12 QC 1D C 5 C1 11 QD 1D D 6 Pin numbers shown are for the J package. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 logic diagram (positive logic) CLR LOAD ENT ENP CLK 1 ’ALS163B and ’AS163 9 10 15 7 RCO 2 C1 14 QA 1D A 3 C1 13 QB 1D B 4 C1 12 QC 1D C 5 C1 1D D 6 Pin numbers shown are for the D, DB, J, and N packages. ’ALS161B and ’AS161 synchronous binary counters are similar; however, CLR is asynchronous. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 QD SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 typical clear, preset, count, and inhibit sequences SN54ALS162B The following sequence is illustrated below: 1. Clear outputs to zero (SN54ALS162B is synchronous) 2. Preset to BCD 7 3. Count to 8, 9, 0, 1, 2, and 3 4. Inhibit CLR LOAD A Data Inputs B C D CLK ENP ENT QA Data Outputs QB QC QD RCO 7 8 9 0 1 2 3 Count Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 typical clear, preset, count, and inhibit sequences ’ALS161B, ’AS161, ’ALS163B, and ’AS163 The following sequence is illustrated below: 1. Clear outputs to zero (’ALS161B and ’AS161 are asynchronous; ’ALS163B and ’AS163 are synchronous.) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A Data Inputs B C D CLK ENP ENT QA Data Outputs QB QC QD RCO 12 13 14 15 0 1 2 Count Sync Preset Clear Async Clear 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 Inhibit SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input voltage range, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Package thermal impedance, θJA (see Note 1): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73°C/W DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTE 1: The package thermal impedance is calculated in accordance with JESD 51. recommended operating conditions SN54ALS161B SN54ALS162B SN54ALS163B VCC VIH Supply voltage VIL IOH Low-level input voltage IOL TA High-level input voltage SN74ALS161B SN74ALS163B UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 2 V V 0.7 0.8 High-level output current – 0.4 – 0.4 mA Low-level output current 4 8 mA 70 °C Operating free-air temperature – 55 125 0 V electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VOL VCC = 4 4.5 5V IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V IIL IO§ VCC = 5.5 V, VCC = 5.5 V, VI = 0.4 V VO = 2.25 V SN54ALS161B SN54ALS162B SN54ALS163B MIN TYP‡ MAX SN74ALS161B SN74ALS163B MIN TYP‡ – 1.5 VCC – 2 MAX – 1.5 VCC – 2 0.25 – 20 UNIT 0.4 V V 0.25 0.4 0.35 0.5 V 0.1 0.1 20 20 µA – 0.2 – 0.2 mA – 112 mA – 112 – 30 mA ICC VCC = 5.5 V 12 21 12 21 mA ‡ All typical values are at VCC = 5 V, TA = 25°C. § The output conditions have been chosen to produce a current that closely approximates one-half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 timing requirements over recommended operating conditions (unless otherwise noted) (see Figure 1) SN54ALS161B SN54ALS162B SN54ALS163B MIN fclock tw tsu Clock frequency Pulse duration Setup time, before CLK↑ ↑ MIN 22 CLR high or low 12.5 20 15 A, B, C, D 50 15 LOAD 20 15 ’ALS161B 25 15 ’ALS161B CLR low SN54ALS162B, ’ALS163B SN54ALS162B ’ALS163B SN54ALS162B, ENP ENT ENP, 20 15 CLR inactive 10 10 CLR low 20 15 CLR high 20 10 0 0 Hold time, all synchronous inputs after CLK↑ UNIT MAX 40 20 ’ALS161B th MAX SN74ALS161B SN74ALS163B MHz ns ns ns switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL tPHL FROM (INPUT) TO (OUTPUT) SN54ALS161B MIN MAX 22 MIN MAX 40 34 5 20 5 27 5 20 4 19 4 15 6 25 6 20 3 18 3 13 3 17 3 13 Any Q 8 27 8 24 RCO 11 32 11 23 RCO CLK Any Q ENT RCO UNIT MHz 5 CLK CLR SN74ALS161B ns ns ns ns switching characteristics over recommended operating conditions (unless otherwise noted) (see Figure 1) PARAMETER fmax tPLH tPHL tPLH tPHL tPLH tPHL 8 FROM (INPUT) TO (OUTPUT) SN54ALS162B SN54ALS163B MIN MAX 22 CLK RCO CLK Any Q ENT RCO POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN74ALS163B MIN UNIT MAX 40 MHz 5 25 5 20 5 25 5 20 4 18 4 15 6 25 6 20 3 16 3 13 3 16 3 13 ns ns ns SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 recommended operating conditions SN54AS161 SN54AS163 SN74AS161 SN74AS163 UNIT MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 VCC VIH Supply voltage VIL IOH Low-level input voltage 0.8 0.8 V High-level output current –2 –2 mA IOL TA Low-level output current 20 20 mA 70 °C High-level input voltage 2 Operating free-air temperature 2 – 55 125 V V 0 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54AS161 SN54AS163 TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 2 mA VOL VCC = 4.5 V, IOL = 20 mA VCC = 5.5 V, VI = 7 V TYP† ENT VCC = 5.5 V, VI = 2.7 V All others LOAD IIL ENT VCC = 5.5 V, TYP† VI = 0.4 V All others UNIT MAX – 1.2 VCC – 2 0.25 LOAD ENT MIN – 1.2 All others IIH MAX VCC – 2 LOAD II SN74AS161 SN74AS163 0.5 V V 0.25 0.5 0.3 0.3 0.2 0.2 0.1 0.1 60 60 40 40 20 20 –1.5 –1.5 –1 –1 – 0.5 – 0.5 V mA µA mA IO‡ VCC = 5.5 V, VO = 2.25 V – 30 – 112 – 30 – 112 mA ICC VCC = 5.5 V 35 53 35 53 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 timing requirements over recommended operating conditions (see Figure 1) SN54AS161 SN54AS163 MIN fclock Clock frequency tw Pulse duration tsu Setup time, time before CLK↑ ↑ MIN 65 CLR high or low 6.7 10 8 A, B, C, D 10 8 LOAD 10 8 ENP, ENT 10 8 CLR inactive 10 8 CLR low 14 12 CLR high (inactive) 10 9 2 0 CLR low ’AS161 Hold time, all synchronous inputs after CLK↑ UNIT MAX 75 7.7 ’AS161 ’AS163 th MAX SN74AS161 SN74AS163 MHz ns ns ns switching characteristics over recommended operating conditions (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax SN74AS161 MIN MAX 75 1 8.5 1 8 3 17.5 3 16.5 CLK RCO 2 14 2 12.5 CLK Any Q 1 7.5 1 7 2 14 2 13 RCO 1.5 10 1.5 9 ENT 1 9.5 1 8.5 Any Q 2 14 2 13 RCO 2 14 2 12.5 CLR UNIT MHz RCO (with LOAD low) tPHL tPLH tPHL MAX RCO (with LOAD high) CLK tPHL MIN 65* tPLH tPHL tPLH SN54AS161 ns ns ns ns ns * On products compliant to MIL-PRF-38535, this parameter is not production tested. switching characteristics over recommended operating conditions (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax MAX CLK tPHL tPLH CLK SN74AS163 MIN MAX 75 1 8.5 1 8 RCO (with LOAD low) 3 17.5 3 16.5 RCO 2 14 2 12.5 1 7.5 1 7 2 14 2 13 1.5 10 1.5 9 1 9.5 1 8.5 CLK Any Q POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT MHz RCO (with LOAD high) RCO ENT tPHL * On products compliant to MIL-PRF-38535, this parameter is not production tested. 10 MIN 65* tPLH tPHL tPLH SN54AS163 ns ns ns ns SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V VCC From Output Under Test From Output Under Test Test Point 500 Ω CL = 50 pF (see Note A) 500 Ω Test Point 500 Ω 3V 500 Ω LOAD CIRCUIT FOR 3-STATE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3V High-Level Pulse 1.5 V Test Point From Output Under Test CL = 50 pF (see Note A) CL = 50 pF (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS Timing Input S1 1.5 V 1.5 V 0V 0V tw th tsu 3V Data Input 1.5 V 3V Low-Level Pulse 1.5 V 0V 1.5 V 0V VOLTAGE WAVEFORMS PULSE DURATIONS VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Control (low-level enabling) 3V 1.5 V 1.5 V 0V tPZL 1.5 V tPHZ VOL 0.3 V tPZH VOH 1.5 V 3V Input tPLZ ≈3 V Waveform 1 S1 Closed (see Note B) Waveform 2 S1 Open (see Note B) 1.5 V 0.3 V ≈0 V VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS 1.5 V 1.5 V 0V tPLH In-Phase Output tPHL VOH 1.5 V VOL tPHL Out-of-Phase Output (see Note C) 1.5 V tPLH VOH 1.5 V 1.5 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one input transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN54ALS161B, SN54ALS162B, SN54ALS163B, SN54AS161, SN54AS163 SN74ALS161B, SN74ALS163B, SN74AS161, SN74AS163 SYNCHRONOUS 4-BIT DECADE AND BINARY COUNTERS SDAS276A – DECEMBER 1994 – REVISED JULY 2000 APPLICATION INFORMATION n-bit synchronous counters This application demonstrates how the ripple-mode carry circuit (see Figure 2) and the carry look-ahead circuit (see Figure 3) can be used to implement a high-speed n-bit counter. The SN54ALS162B counts in BCD. The ’ALS161B, ’AS161, ’ALS163B, and ’AS163 devices count in binary. When additional stages are added, the fmax decreases in Figure 2, but remains unchanged in Figure 3. LSB Clear (L) Count (H) Disable (L) Load (L) Count (H) Disable (L) CLR LOAD ENT ENP CLK A B C D LSB CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ 1,5D CLR LOAD ENT ENP CLK Clear (L) RCO Count (H) Disable (L) Clock QA QB QC QD A B C D Load (L) CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ RCO 1,5D QA QB QC QD Clock CLR LOAD ENT ENP CLK A B C D CLR LOAD ENT ENP CLK A B C D CLR LOAD ENT ENP CLK A B C D CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ 1,5D CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ 1,5D CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ 1,5D RCO CLR LOAD ENT ENP CLK QA QB QC QD A B C D RCO CLR LOAD ENT ENP CLK QA QB QC QD A B C D RCO CLR LOAD ENT ENP CLK QA QB QC QD A B C D To More Significant Stages fmax = 1/(CLK to RCO tPLH) + (ENT to RCO tPLH) (N – 2) + (ENT tsu) Figure 2. Ripple-Mode Carry Circuit 12 POST OFFICE BOX 655303 CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ RCO 1,5D CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ QA QB QC QD RCO 1,5D CT=0 CTR M1 G3 3CT=MAX G4 C5/T,3,4+ QA QB QC QD RCO 1,5D QA QB QC QD To More Significant Stages fmax = 1/(CLK to RCO tPLH) + (ENP tsu) Figure 3. Carry Look-Ahead Circuit • DALLAS, TEXAS 75265 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. 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