SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 D D D D D Internal Look-Ahead for Fast Counting Carry Output for n-Bit Cascading Synchronous Counting Synchronously Programmable Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54HC161 . . . J OR W PACKAGE SN74HC161 . . . D OR N PACKAGE (TOP VIEW) CLR CLK A B C D ENP GND description These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs. 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC RCO QA QB QC QD ENT LOAD CLK CLR NC VCC RCO SN54HC161 . . . FK PACKAGE (TOP VIEW) A B NC C D 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 QA QB NC QC QD ENP GND NC LOAD ENT These synchronous, presettable counters feature an internal carry look-ahead for application in high-speed counting designs. The ’HC161 are 4-bit binary counters. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of the clock waveform. 1 NC – No internal connection The clear function for the ’HC161 is asynchronous. A low level at the clear (CLR) input sets all four of the flip-flop outputs low, regardless of the levels of the CLK, load (LOAD), or enable inputs. The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional gating. Instrumental in accomplishing this function are ENP, ENT, and a ripple-carry output (RCO). Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the level of CLK. These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the stable setup and hold times. The SN54HC161 is characterized for operation over the full military temperature range of –55°C to 125°C. The SN74HC161 is characterized for operation from –40°C to 85°C. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1997, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 logic symbol† 1 CLR 9 LOAD ENT ENP CLK A B C D 10 7 2 3 CTRDIV16 CT=0 M1 M2 3CT=15 RCO G4 C5/2,3,4+ 1,5D 4 5 6 [1] [2] [4] [8] † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, N, and W packages. 2 15 G3 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 14 13 12 11 QA QB QC QD SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 logic diagram (positive logic) LOAD ENT ENP 9 10 15 LD† 7 RCO CK† CLK CLR A B C D 2 1 CK LD R M1 G2 1, 2T/1C3 G4 3D 4R 3 M1 G2 1, 2T/1C3 G4 3D 4R 4 M1 G2 1, 2T/1C3 G4 3D 4R 5 M1 G2 1, 2T/1C3 G4 3D 4R 6 14 13 12 11 QA QB QC QD † For simplicity, routing of complementary signals LD and CK is not shown on this overall logic diagram. The uses of these signals are shown on the logic diagram of the D/T flip-flops. Pin numbers shown are for the D, J, N, and W packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 logic symbol, each D/T flip-flop LD (Load) M1 TE (Toggle Enable) G2 CK (Clock) 1, 2T/1C3 G4 D (Inverted Data) 3D R (Inverted Reset) 4R Q (Output) logic diagram, each D/T flip-flop (positive logic) CK LD TE LD† TG TG LD† Q TG TG CK† D TG CK† R † The origins of LD and CK are shown in the logic diagram of the overall device. 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 CK† TG CK† SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 typical clear, preset, count, and inhibit sequence The following sequence is illustrated below: 1. Clear outputs to zero (asynchronous) 2. Preset to binary 12 3. Count to 13, 14, 15, 0, 1, and 2 4. Inhibit CLR LOAD A Data Inputs B C D CLK ENP ENT QA Data Outputs QB QC QD RCO 12 13 14 15 0 1 2 Count Inhibit Sync Preset Clear Async Clear POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 5 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 absolute maximum ratings over operating free-air temperature range† Supply voltage range, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V Input clamp current, IIK (VI < 0 or VI > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Output clamp current, IOK (VO < 0 or VO > VCC) (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA Continuous output current, IO (VO = 0 to VCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA Continuous current through VCC or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±50 mA Package thermal impedance, θJA (see Note 2): D package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113°C/W N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78°C/W Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed. 2. The package thermal impedance is calculated in accordance with JESD 51, except for through-hole packages, which use a trace length of zero. recommended operating conditions SN54HC161 VCC Supply voltage VIH High-level input voltage VCC = 2 V VCC = 4.5 V VCC = 6 V VCC = 2 V VIL Low-level input voltage VI VO Input voltage Output voltage tt‡ Input transition (rise and fall) time SN74HC161 MIN NOM MAX MIN NOM MAX 2 5 6 2 5 6 1.5 1.5 3.15 3.15 4.2 4.2 V V 0 0.5 0 0.5 0 1.35 0 1.35 0 1.8 0 1.8 0 0 0 VCC VCC 0 VCC VCC VCC = 2 V VCC = 4.5 V 0 1000 0 1000 0 500 0 500 VCC = 6 V 0 400 0 400 VCC = 4.5 V VCC = 6 V UNIT V V V ns TA Operating free-air temperature –55 125 –40 85 °C ‡ If this device is used in the threshold region (from VILmax = 0.5 V to VIHmin = 1.5 V), there is a potential to go into the wrong state from induced grounding, causing double clocking. Operating with the inputs at tt = 1000 ns and VCC = 2 V does not damage the device; however, functionally, the CLK inputs are not ensured while in the shift, count, or toggle operating modes. 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCC IOH = –20 µA VOH IOL = 20 µA VOL II ICC VI = VCC or 0 VI = VCC or 0, MIN MAX SN74HC161 MIN 1.998 1.9 1.9 4.5 V 4.4 4.499 4.4 4.4 6V 5.9 5.999 5.9 5.9 4.5 V 3.98 4.3 3.7 3.84 6V 5.48 5.8 5.2 MAX UNIT V 5.34 2V 0.002 0.1 0.1 0.1 4.5 V 0.001 0.1 0.1 0.1 6V 0.001 0.1 0.1 0.1 4.5 V 0.17 0.26 0.4 0.33 6V 0.15 0.26 0.4 0.33 6V ±0.1 ±100 ±1000 ±1000 nA 8 160 80 µA 3 10 10 10 pF IO = 0 6V Ci SN54HC161 1.9 VI = VIH or VIL IOL = 4 mA IOL = 5.2 mA TA = 25°C TYP MAX 2V VI = VIH or VIL IOH = –4 mA IOH = –5.2 mA MIN 2 V to 6 V V timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock Clock frequency CLK high or low tw Pulse duration CLR low A, B, C, or D LOAD low tsu Setup time before CLK↑ ↑ ENP, ENT CLR inactive th Hold time, all synchronous inputs after CLK↑ ↑ POST OFFICE BOX 655303 TA = 25°C MIN MAX SN54HC161 SN74HC161 MIN MAX MIN MAX 2V 0 6 0 4.2 0 5 4.5 V 0 31 0 21 0 25 6V 0 36 0 25 0 29 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 80 120 100 4.5 V 16 24 20 6V 14 20 17 2V 150 225 190 4.5 V 30 45 38 6V 26 38 32 2V 135 205 170 4.5 V 27 41 34 6V 23 35 29 2V 170 255 215 4.5 V 34 51 43 6V 29 43 37 2V 125 190 155 4.5 V 25 38 31 6V 21 32 26 2V 0 0 0 4.5 V 0 0 0 6V 0 0 0 • DALLAS, TEXAS 75265 UNIT MHz ns ns ns 7 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Figure 1) PARAMETER FROM (INPUT) TO (OUTPUT) fmax RCO CLK tpd Any Q ENT RCO Any Q tPHL CLR RCO tt Any VCC MIN TA = 25°C TYP MAX SN54HC161 MIN MAX SN74HC161 MIN 2V 6 14 4.2 5 4.5 V 31 40 21 25 6V 36 44 25 29 MAX UNIT MHz 2V 83 215 325 270 4.5 V 24 43 65 54 6V 20 37 55 46 2V 80 205 310 255 4.5 V 25 41 62 51 6V 21 35 53 43 2V 62 195 295 245 4.5 V 17 39 59 49 6V 14 33 50 42 2V 105 210 315 265 4.5 V 21 42 63 53 6V 18 36 54 45 2V 110 220 330 275 4.5 V 22 44 66 55 6V 19 37 56 47 2V 38 75 110 95 4.5 V 8 15 22 19 6V 6 13 19 16 ns ns ns operating characteristics, TA = 25°C PARAMETER Cpd 8 TEST CONDITIONS Power dissipation capacitance No load POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 TYP 60 UNIT pF SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 PARAMETER MEASUREMENT INFORMATION From Output Under Test VCC High-Level Pulse Test Point 50% 50% 0V tw CL = 50 pF (see Note A) VCC Low-Level Pulse 50% 50% 0V LOAD CIRCUIT VOLTAGE WAVEFORMS PULSE DURATIONS Input VCC 50% 50% 0V tPLH Reference Input VCC 50% In-Phase Output 50% 10% 0V tsu Data Input 50% 10% 90% tr tPHL VCC 50% 10% 0 V 90% 90% tr th 90% tPHL Out-of-Phase Output 90% VOLTAGE WAVEFORMS SETUP AND HOLD AND INPUT RISE AND FALL TIMES tPLH 50% 10% tf tf VOH 50% 10% VOL tf 50% 10% 90% VOH VOL tr VOLTAGE WAVEFORMS PROPAGATION DELAY AND OUTPUT TRANSITION TIMES NOTES: A. CL includes probe and test-fixture capacitance. B. Phase relationships between waveforms were chosen arbitrarily. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, ZO = 50 Ω, tr = 6 ns, tf = 6 ns. C. For clock inputs, fmax is measured when the input duty cycle is 50%. D. The outputs are measured one at a time with one input transition per measurement. E. tPLH and tPHL are the same as tpd. Figure 1. Load Circuit and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 9 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 APPLICATION INFORMATION n-bit synchronous counters This application demonstrates how the look-ahead carry circuit can be used to implement a high-speed n-bit counter. The ’HC161 count in binary. Virtually any count mode (modulo-N, N1-to-N2, N1-to-maximum) can be used with this fast look-ahead circuit. The application circuit shown in Figure 2 is not valid for clock frequencies above 18 MHz (at 25°C and 4.5-V VCC). The reason for this is that there is a glitch that is produced on the second stage’s RCO and every succeeding stage’s RCO. This glitch is common to all HC vendors that Texas Instruments has evaluated, in addition to the bipolar equivalents (LS, ALS, AS). 10 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 LSB CTR CT=0 M1 3CT=MAX G3 CLR Clear (L) LOAD ENT Count (H)/ Disable (L) ENP CLK RCO G4 C5/2,3,4+ Load (L) A 1,5D [1] QA Count (H)/ Disable (L) B [2] QB C [3] QC Clock D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD CTR CT=0 M1 3CT=MAX G3 CLR LOAD ENT ENP CLK RCO G4 C5/2,3,4+ A 1,5D [1] QA B [2] QB C [3] QC D [4] QD To More Significant Stages Figure 2 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 11 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 The glitch on RCO is caused because the propagation delay of the rising edge of QA of the second stage is shorter than the propagation delay of the falling edge of ENT. RCO is the product of ENT, QA, QB, QC, and QD (ENT × QA × QB × QC × QD). The resulting glitch is about 7–12 ns in duration. Figure 3 shows the condition in which the glitch occurs. For simplicity, only two stages are being considered, but the results can be applied to other stages. QB, QC, and QD of the first and second stage are at logic one, and QA of both stages are at logic zero (1110 1110) after the first clock pulse. On the rising edge of the second clock pulse, QA and RCO of the first stage go high. On the rising edge of the third clock pulse, QA and RCO of the first stage return to a low level, and QA of the second stage goes to a high level. At this time, the glitch on RCO of the second stage appears because of the race condition inside the chip. 1 2 3 4 5 CLK ENT1 QB1, QC1, QD1 QA1 RCO1, ENT2 QB2, QC2, QD2 QA2 RCO2 Glitch (7–12 ns) Figure 3 The glitch causes a problem in the next stage (stage three) if the glitch is still present when the next rising clock edge appears (clock pulse 4). To ensure that this does not happen, the clock frequency must be less than the inverse of the sum of the clock-to-RCO propagation delay and the glitch duration (tg). In other words, fmax = 1/(tpd CLK-to-RCO + tg). For example, at 25°C at 4.5-V VCC, the clock-to-RCO propagation delay is 43 ns and the maximum duration of the glitch is 12 ns. Therefore, the maximum clock frequency that the cascaded counters can use is 18 MHz. The following tables contain the fclock, tw, and fmax specifications for applications that use more than two ’HC161 devices cascaded together. 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 SN54HC161, SN74HC161 4-BIT SYNCHRONOUS BINARY COUNTERS SCLS297A – JANUARY 1996 – REVISED MAY 1997 timing requirements over recommended operating free-air temperature range (unless otherwise noted) VCC fclock tw Clock frequency Pulse duration, CLK high or low TA = 25°C MIN MAX SN54HC161 SN74HC161 MIN MAX MIN MAX 2V 0 3.6 0 2.5 0 2.9 4.5 V 0 18 0 12 0 14 6V 0 21 0 14 0 17 2V 140 200 170 4.5 V 28 40 36 6V 24 36 30 UNIT MHz ns switching characteristics over recommended operating free-air temperature range, CL = 50 pF (unless otherwise noted) (see Note 3) PARAMETER FROM (INPUT) TO (OUTPUT) fmax VCC TA = 25°C MIN MAX SN54HC161 MIN MAX SN74HC161 MIN 2V 3.6 2.5 2.9 4.5 V 18 12 14 6V 21 14 17 MAX UNIT MHz NOTE 3: These limits apply only to applications that use more than two ’HC161 devices cascaded together. If the ’HC161 are used as a single unit, or only two cascaded together, then the maximum clock frequency that the device can use is not limited because of the glitch. In these situations, the device can be operated at the maximum specifications. A glitch can appear on RCO of a single ’HC161 device, depending on the relationship of ENT to CLK. Any application that uses RCO to drive any input except an ENT of another cascaded ’HC161 must take this into consideration. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 13 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER’S RISK. In order to minimize risks associated with the customer’s applications, adequate design and operating safeguards must be provided by the customer to minimize inherent or procedural hazards. TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other intellectual property right of TI covering or relating to any combination, machine, or process in which such semiconductor products or services might be or are used. TI’s publication of information regarding any third party’s products or services does not constitute TI’s approval, warranty or endorsement thereof. Copyright 1998, Texas Instruments Incorporated