SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS SDAS210C – DECEMBER 1982 – REVISED JULY 1996 D D D D D Single Down / Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic Small-Outline (D) Packages, Ceramic Chip Carriers (FK), and Standard Plastic (N) and Ceramic (J) 300-mil DIPs SN54ALS191A . . . J PACKAGE SN74ALS191A . . . D OR N PACKAGE (TOP VIEW) B QB QA CTEN D/U QC QD GND 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VCC A CLK RCO MAX/MIN LOAD C D description The outputs of the four flip-flops are triggered on a low-to-high-level transition of the clock (CLK) input if the count enable (CTEN) input is low. A high at CTEN inhibits counting. The direction of the count is determined by the level of the down/up (D/U) input. When D/U is low, the counter counts up, and when D/U is high, the counter counts down. QB B NC VCC A SN54ALS191A . . . FK PACKAGE (TOP VIEW) QA CTEN NC D/U QC 4 3 2 1 20 19 18 5 17 6 16 7 15 8 14 9 10 11 12 13 CLK RCO NC MAX/MIN LOAD QD GND NC D C The ’ALS191A are synchronous 4-bit reversible up/down binary counters. Synchronous counting operation is provided by having all flip-flops clocked simultaneously so that the outputs change coincidentally with each other when instructed by the steering logic. This mode of operation eliminates the output counting spikes normally associated with asynchronous (ripple-clock) counters. NC – No internal connection These counters feature a fully independent clock circuit. Changes at the control inputs (CTEN and D/U) that modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of the counter is dictated solely by the conditions meeting the stable setup and hold times. These counters are fully programmable. Each output can be preset to either level by placing a low on the LOAD input and entering the desired data at the data inputs. The output changes to agree with the data inputs independently of the level of the clock input. This feature allows the counters to be used as modulo-N dividers by simply modifying the count length with the preset inputs. CLK, D/U, and LOAD are buffered to lower the drive requirement, which significantly reduces the loading on (current required by) clock drivers, for long parallel words. Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. Copyright 1996, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS SDAS210C – DECEMBER 1982 – REVISED JULY 1996 description (continued) Two outputs are available to perform the cascading function: ripple clock and maximum/minimum count. The latter output produces a high-level output pulse with a duration approximately equal to one complete cycle of the clock while the count is minimum (0) counting down or maximum (15) counting up. The ripple-clock output (RCO) produces a low-level output pulse under those same conditions, but only while the clock input is low. The counter easily can be cascaded by feeding the ripple-clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used. The maximum/minimum count (MAX/MIN) output can be used to accomplish look ahead for high-speed operation. The SN54ALS191A is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74ALS191A is characterized for operation from 0°C to 70°C. logic symbol† CTEN D/U CLK LOAD A B C D 4 5 14 11 15 1 10 9 G1 CTRDIV16 M2 [DOWN] 2(CT=0)Z6 3(CT=15)Z6 M3 [UP] 1,2– / 1,3+ G4 6,1,4 13 MAX/MIN RCO C5 5D [1] [2] [4] [8] † This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12. Pin numbers shown are for the D, J, and N packages. 2 12 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 2 6 7 QA QB QC QD SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS SDAS210C – DECEMBER 1982 – REVISED JULY 1996 logic diagram (positive logic) 12 CTEN D/U CLK LOAD A MAX/ MIN 4 13 RCO 5 14 11 15 3 S QA C1 1D R B 1 2 S QB C1 1D R C 10 6 S C1 QC 1D R D 9 7 S QD C1 1D R Pin numbers shown are for the D, J, and N packages. POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 3 SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS SDAS210C – DECEMBER 1982 – REVISED JULY 1996 typical load, count, and inhibit sequences The following sequence is illustrated below: 1. Load (preset) to binary 13 2. Count up to 14, 15 (maximum), 0, 1, and 2 3. Inhibit 4. Count down to 1, 0 (minimum), 15, 14, and 13 LOAD A B Data Inputs C D CLK D/U CTEN QA QB QC QD MAX/MIN RCO 13 14 15 0 1 2 Count Up 2 2 Inhibit Load 4 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 1 0 15 14 Count Down 13 SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS SDAS210C – DECEMBER 1982 – REVISED JULY 1996 absolute maximum ratings over operating free-air temperature range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Operating free-air temperature range, TA: SN54ALS191A . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 55°C to 125°C SN74ALS191A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0°C to 70°C Storage temperature range, Tstg . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 65°C to 150°C † Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions SN54ALS191A VCC VIH Supply voltage VIL IOH Low-level input voltage IOL fclock Low-level output current tw Pulse duration tsu th TA High-level input voltage MIN NOM MAX MIN NOM MAX 4.5 5 5.5 4.5 5 5.5 2 High-level output current Hold time 2 0 0.8 – 0.4 – 0.4 20 0 CLK high or low 20 16.5 LOAD low 25 20 Data before LOAD↑ 25 20 CTEN before CLK↑ 45 20 D/U before CLK↑ 30 20 LOAD inactive before CLK↑ 20 20 Data after LOAD↑ 5 5 CTEN after CLK↑ 0 0 D/U after CLK↑ 0 0 Operating free-air temperature – 55 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 125 0 UNIT V V 0.7 4 Clock frequency Setup time SN74ALS191A V mA 8 mA 30 MHz ns ns ns 70 °C 5 SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS SDAS210C – DECEMBER 1982 – REVISED JULY 1996 electrical characteristics over recommended operating free-air temperature range (unless otherwise noted) PARAMETER SN54ALS191A TYP† MAX TEST CONDITIONS MIN VIK VOH VCC = 4.5 V, VCC = 4.5 V to 5.5 V, II = – 18 mA IOH = – 0.4 mA VOL 5V VCC = 4 4.5 IOL = 4 mA IOL = 8 mA II IIH VCC = 5.5 V, VCC = 5.5 V, VI = 7 V VI = 2.7 V VCC = 5 5.5 5V V, VI = 0 0.4 4V IIL CTEN or CLK All others SN74ALS191A TYP† MAX MIN – 1.5 VCC – 2 UNIT – 1.5 V 0.25 0.4 V 0.35 0.5 VCC – 2 0.25 0.4 0.2 0.1 mA 20 20 µA – 0.2 – 0.2 – 0.2 – 0.1 mA IO‡ VCC = 5.5 V, VO = 2.25 V – 20 – 112 – 30 – 112 mA ICC VCC = 5.5 V, All inputs at 0 12 22 12 22 mA † All typical values are at VCC = 5 V, TA = 25°C. ‡ The output conditions have been chosen to produce a current that closely approximates one half of the true short-circuit output current, IOS. switching characteristics (see Figure 1) PARAMETER FROM (OUTPUT) TO (OUTPUT) VCC = 4.5 V to 5.5 V, CL = 50 pF, RL = 500 Ω, TA = MIN to MAX§ SN54ALS191A SN74ALS191A MIN fmax tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL tPLH MAX 20 LOAD Any Q A B, A, B C, C D Any Q CLK RCO CLK Any Q CLK MAX/MIN D/U RCO D/U MAX/MIN MIN MAX 30 MHz 7 37 7 30 8 34 8 30 3 25 3 21 4 25 4 21 5 24 5 20 5 25 5 20 3 26 3 18 3 22 3 18 8 37 8 31 8 34 8 31 8 45 8 37 10 36 10 28 8 35 8 25 8 30 8 25 4 21 4 CTEN RCO tPHL 4 23 4 § For conditions shown as MIN or MAX, use the appropriate value specified under recommended operating conditions. 18 tPHL tPLH tPHL tPLH 6 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 UNIT 18 ns ns ns ns ns ns ns ns SN54ALS191A, SN74ALS191A SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS SDAS210C – DECEMBER 1982 – REVISED JULY 1996 PARAMETER MEASUREMENT INFORMATION SERIES 54ALS/74ALS AND 54AS/74AS DEVICES 7V RL = R1 = R2 VCC S1 RL R1 Test Point From Output Under Test CL (see Note A) From Output Under Test RL Test Point From Output Under Test CL (see Note A) CL (see Note A) LOAD CIRCUIT FOR BI-STATE TOTEM-POLE OUTPUTS LOAD CIRCUIT FOR OPEN-COLLECTOR OUTPUTS 3.5 V Timing Input Test Point LOAD CIRCUIT FOR 3-STATE OUTPUTS 3.5 V High-Level Pulse 1.3 V R2 1.3 V 1.3 V 0.3 V 0.3 V tsu Data Input tw th 3.5 V 1.3 V 3.5 V Low-Level Pulse 1.3 V 0.3 V 1.3 V 0.3 V VOLTAGE WAVEFORMS SETUP AND HOLD TIMES VOLTAGE WAVEFORMS PULSE DURATIONS 3.5 V Output Control (low-level enabling) 1.3 V 1.3 V 0.3 V tPZL Waveform 1 S1 Closed (see Note B) tPLZ [3.5 V 1.3 V tPHZ tPZH Waveform 2 S1 Open (see Note B) 1.3 V VOL 0.3 V VOH 1.3 V 0.3 V [0 V 3.5 V 1.3 V Input 1.3 V 0.3 V tPHL tPLH VOH In-Phase Output 1.3 V 1.3 V VOL tPLH tPHL VOH Out-of-Phase Output (see Note C) 1.3 V 1.3 V VOL VOLTAGE WAVEFORMS PROPAGATION DELAY TIMES VOLTAGE WAVEFORMS ENABLE AND DISABLE TIMES, 3-STATE OUTPUTS NOTES: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. When measuring propagation delay items of 3-state outputs, switch S1 is open. D. All input pulses have the following characteristics: PRR ≤ 1 MHz, tr = tf = 2 ns, duty cycle = 50%. E. The outputs are measured one at a time with one transition per measurement. Figure 1. Load Circuits and Voltage Waveforms POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 7 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. 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