W25Q16B,W25Q16C,W25Q80B,W25Q40B,W25Q20B,W25Q10B W25X16B,W25X80B,W25X40B,W25X20B, W25X10B AEC-Q100 RELIABILITY REPORT W25Q16B, W25Q16C, W25Q80B, W25Q40B W25Q20B, W25Q10B, W25X16B, W25X80B W25X40B, W25X20B, W25X10B PART NO. : W25Q16BV W25X16BV FUNCTION : 16M FLASH MEMORY PROCESS : 90nm CMOS (DPTM) RA ENGINEER : RA MANAGER : -1- Publication Release Date:10/5/2011 Reliability Engineering Department W25Q16B,W25Q16C,W25Q80B,W25Q40B,W25Q20B,W25Q10B W25X16B,W25X80B,W25X40B,W25X20B, W25X10B ~SUMMARY~ W25Q16BV, W25X16BV for 8 SOP 208 mil passed the qualification tests according to Winbond product qualification requirement. A summary of the test result is as follows: . Endurance Cycling with HTOL : 0/231 pcs . Endurance Cycling with Data Retention : 0/231 pcs . Dynamic Early Fail Study : 0/2400 pcs . Pre-Condition Test : 0/924 pcs . High Temp. Storage Life Test : 0/231 pcs . Pressure Cooker Test : 0/231 pcs . Temperature Cycle Test : 0/231 pcs . Highly Accelerated Stress Test : 0/231 pcs . ESD-HBM : 0/36 pcs . ESD-MM : 0/36 pcs . ESD-CDM : 0/9 pcs . Latch -Up Test : 0/18 pcs -2- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B,W25Q16C,W25Q80B,W25Q40B,W25Q20B,W25Q10B W25X16B,W25X80B,W25X40B,W25X20B, W25X10B ---CONTENTS--Ⅰ. PRODUCT DESCRIPTION A. Introduction B. Features C. Function Block Ⅱ. LIFE TEST A. Introduction 1. Endurance Cycling with HTOL 2. Endurance Cycling with Data Retention 3. Dynamic Early Fail Study B. Test Results 1. Endurance Cycling with HTOL 2. Endurance Cycling with Data Retention 3. Dynamic Early Fail Study -3- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B,W25Q16C,W25Q80B,W25Q40B,W25Q20B,W25Q10B W25X16B,W25X80B,W25X40B,W25X20B, W25X10B Ⅲ. ENVIRONMENTAL TEST A. Introduction 1. Pre-Condition Test 2. High Temp. Storage Life Test (HTSL) 3. Pressure Cooker Test (PCT) 4. Highly Accelerated Stress Testing (HAST) 5. Temperature Cycle Test (TCT) B. Test Results 1. Pre-Condition Test 2. High Temp. Storage Life Test (HTSL) 3. Pressure Cooker Test (PCT) 4. Highly Accelerated Stress Testing (HAST) 5. Temperature Cycle Test (TCT) Ⅳ. ESD & LATCH-UP A. Introduction 1. ESD 2. LATCH-UP B. Test Results 1. ESD 2. LATCH-UP -4- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B,W25Q16C,W25Q80B,W25Q40B,W25Q20B,W25Q10B W25X16B,W25X80B,W25X40B,W25X20B, W25X10B I. PRODUCT DESCRIPTION A. Introduction The W25Q16BV (16M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI(XIP) and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 5mA active and 1µA for power-down. All devices are offered in space-saving packages. The W25Q16BV array is organized into 8,192 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q16BV has 512 erasable sectors and 32 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. The W25Q16BV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0(DI),I/O1(DO),I/O2(/WP), and I/O3(/HOLD). SPI clock frequencies of up to 80MHz are supported allowing equivalent clock rates of 160MHz for Dual Output and 320MHz for Quad Output when using the Fast Read Dual/Quad Output instruction. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top -5- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B,W25Q16C,W25Q80B,W25Q40B,W25Q20B,W25Q10B W25X16B,W25X80B,W25X40B,W25X20B, W25X10B or bottom array control, provides further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. B. Features Family of Serial Flash Memories – W25Q16BV: 16M-bit / 2M -byte (2,097,152) – 256-bytes per programmable page Standard, Dual or Quad SPI – Standard SPI: CLK,/CS,DI,DO,/WP,/Hold – Dual SPI: CLK,/CS,IO0,IO1,/WP,/Hold – Quad SPI: CLK,/CS,IO0,IO1,IO2,IO3 Highest Performance Serial Flash – Up to 6X that of ordinary Serial Flash – 80MHz clock operation – 160MHz equivalent Dual SPI – 320 MHz equivalent Dual SPI – 40MB/S continuous data transfer rate. Efficient “Continuous Read Mode” – Low Instruction overhead – As few as 8 clocks to address memory – Allows true XIP(excute in place) operation – Uutperforms X16 Parallel Flash Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down (typ.) – -40° C to +105°C operating range -6- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B Flexible Architecture with 4KB sectors – Uniform Sector Erase (4K-bytes) – Block Erase (32K and 64K-bytes) – Program one to 256 bytes – More than 100,000 erase/write cycles – More than 20-year data retention Advanced Security Features – Software and Hardware Write-Protect – Top or Bottom ,Sector or Block selection – Lock-Down and OTP protection – 64-Bit Unique ID for eatch device Space Efficient Packaging – 8-pin SOIC 150/208-mil – 8-pad WSON 6x5-mm – 16-pin SOIC 300-mil – Contact Winbond for KGD and CSP options -7- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B C. Function Block -8- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B II. LIFE TEST A. Introduction 1. Endurance Cycling with HTOL 1.1 SCOPE Endurance cycling test is to measure the capability of program/erase cycle. HTOL test is performed to accelerate failure mechanisms which are thermally activated. This can be achieved by stressing the devices with bias at high temperature. 1.2 TEST CONDITION Whole chip cycling test: Temp=25 C, Td=10K Cycles with Whole Chip, pattern=FF, CHKBD, CHKBD\, 00 High-Temperature Operating Life Test (HTOL): Temp ambient = 125 C ,Vdd = 3.6V, dynamic stressing, Td = 1000 hrs (JESD22-A108) -9- Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B 2. Endurance Cycling with Data Retention 2.1 SCOPE Endurance cycling test is to measure the capability of program/erase cycle. DR test is to determine the stability of data stored in the device under high temperature environment. 2.2 TEST CONDITION Whole chip cycling test: Temp=25 C, Td=10K Cycles with Whole Chip, pattern=00, FF, CHKBD, CHKBD\ Data Retention Test (DR): Temp = 150 C , Td = 1000 hrs. (AEC-Q100-005) 3. Dynamic Early Fail Study (EFR) 3.1 SCOPE EFR test is performed to accelerate infant mortality failure mechanisms which are thermally activated. This can be achieved by stressing the devices with bias at high temperature. 3.2 TEST CONDITION Temp ambient = 125 C, Vdd = 3.6V, dynamic stressing, Td = 72 hrs. (AEC-Q100-008) - 10 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B B. Test Results 1. Endurance Cycling with HTOL RUN Lot No Whole HTOL- chip HTOL- HTOL- Remark 168 HRs 500 HRs 1000 HRs cycling: 10K #1 691800400 0/77 0/77 0/77 0/77 #2 69204A200 0/77 0/77 0/77 0/77 #3 691801500 0/77 0/77 0/77 0/77 *Criteria: Acc/Rej = 0/1. FAILURE RATE CALCULATION 2 F . R.( T ) X WHERE X 2 (1 CL , 2 N 2 EDH 2) : CHI-SQUARE Function CL : Confidence Level N : No of Failures EDH : Equivalent Device Hour Test Dev. Hours Equiv. Dev. No. of Failure Item at Hours at Failure Rate Tj=126.20 C Tj=55 C 231000 210621224.5 HTOL at 55 C 0 4.34 FIT Based on CL = 60% and Activation Energy = 1.08 eV Tj Ta Pd ja where :Tj= junction temp ,Ta=125℃ (ambient temp) - 11 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B Pd=12.72mW (power dissipated on the device) Θja=94.6℃/W (thermal resistance from junction to ambient 2. Endurance Cycling with Data Retention RUN Lot No Whole chip DR- DR- DR- Remark 168 HRs 500 HRs 1000 HRs cycling: 10K #1 691800400 0/77 0/77 0/77 0/77 #2 69204A200 0/77 0/77 0/77 0/77 #3 691801500 0/77 0/77 0/77 0/77 3. Dynamic Early Fail Study (EFR) RUN Lot No 72 Hrs #1 691800400 0/800 #2 691800400 0/800 #3 691800400 0/800 - 12 - Remark Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B III. ENVIRONMENTAL TESTS A. Introduction 1. Pre-condition Test 1.1 SCOPE Pre-condition Test is to measure the resistance of SMD(Surface Mount Devices) to the storage environment at the customer site and to thermal stress created by IR reflow or Vapor Phase Reflow. 1.2 TEST CONDITION Step 1 : TCT (-65 C/150 C, 5 cycles) Step 2 : Bake (125 C, 20 hours) Step 3 : Soak (30 C/60%RH, 192 hours) Step 4 : IR , 3 passes (JEDEC 020 D). 2. High Temperature Storage Life Test (HTSL) 2.1 SCOPE HTSL test is to determine the stability of the device in high temperature environment. 2.2 TEST CONDITION Temp = 150 C, Td = 1000 hrs. (JESD22-A103) 3. Pressure Cooker Test (PCT) 3.1 SCOPE PCT is to evaluate the device resistance to moisture penetration. 3.2 TEST CONDITION Ta = 121 C, RH = 100%, P = 2 atm, Td = 168 Hrs. (JESD22-A102-B) - 13 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B 4. Highly Accelerated Stress Testing (HAST) 4.1 SCOPE HAST is to evaluate the reliability of non hermetic packaged solid-state device in humid environments. 4.2 TEST CONDITION Ta = 130 C, Vdd=3.6V, RH% = 85%, P = 2 atm, Td = 168 Hrs. (JESD22-A110) 5. Temperature Cycle Test (TCT) 5.1 SCOPE TCT is to evaluate the resistance of device to environmental temperature change. 5.2 TEST CONDITION -65 C / 15min, transfer time 1min, +150 C/15min, 500 cycles. (JESD22-A104) - 14 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B B. Test Result 1. Pre-condition Test Run Lot No Result #1 691800400 0/385 #2 69204A200 0/385 #3 691801500 0/385 Remark *Criteria : Acc/Rej = 0/1. 2. High Temperature Storage Life Test (HTSL) RUN Lot No 168 Hrs 500 Hrs 1000 Hrs Remark #1 691800400 0/77 0/77 0/77 #2 69204A200 0/77 0/77 0/77 #3 691801500 0/77 0/77 0/77 *Criteria : Acc/Rej = 0/1 3. Pressure Cooker Test (PCT) Run Lot No 168 Hrs #1 691800400 0/77 #2 69204A200 0/77 #3 691801500 0/77 Remark *Criteria : Acc/Rej = 0/1. - 15 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B 4. Highly Accelerated Stress Testing (HAST) Run Lot No 168 Hrs #1 691800400 0/77 #2 69204A200 0/77 #3 691801500 0/77 Remark *Criteria : Acc/Rej = 0/1. 5. Temperature Cycle Test (TCT) Run Lot No 500 Cycles #1 691800400 0/77 #2 69204A200 0/77 #3 691801500 0/77 Remark *Criteria : Acc/Rej = 0/1. - 16 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B IV. ESD AND LATCH-UP A. Introduction 1. ESD 1.1 SCOPE ESD test is to evaluate the immunity of device to electrostatic discharge. 1.2 TEST CONDITION Human Body Model (HBM): AEC-Q100-002 Machine Model (MM): AEC-Q100-002 Charge Device Model (CDM): AEC-Q100-011 2. Latch-Up 2.1 SCOPE Latch-Up test is to evaluate the immunity of the devices to latch-up. 2.2 TEST CONDITION AEC-Q100-004, Temp = 25 C, VDD = Max. Operating Voltage. - 17 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B B. Test Results 1. ESD 1.1 Human Body Model Run LOT# POSITIVE NEGATIVE #1 691800400 0/6 0/6 #2 69204A200 0/6 0/6 #3 691801500 0/6 0/6 Remark *Criteria : Acc/Rej = 0/1. *| SPEC | : >2KV 1.2. Machine Model Run LOT# POSITIVE NEGATIVE Remark #1 691800400 0/6 0/6 #2 69204A200 0/6 0/6 #3 691801500 0/6 0/6 *Criteria : Acc/Rej = 0/1. *| SPEC | : >200 V 1.3. Charge Device Model Run LOT# POSITIVE / NEGATIVE #1 691800400 0/3 #2 69204A200 0/3 #3 691801500 0/3 Remark *Criteria : Acc/Rej = 0/1. *| SPEC | : >750V - 18 - Publication Release Date: 10/5/2011 Reliability Engineering Department W25Q16B, W25Q16C, W25Q80B, W25Q40B, W25Q20B, W25Q10B W25X16B, W25X80B, W25X40B, W25X20B, W25X10B 2. Latch-Up Run LOT# POSITIVE NEGATIVE Remark #1 691800400 0/3 0/3 #2 69204A200 0/3 0/3 #3 691801500 0/3 0/3 *Criteria : Acc/Rej = 0/1. *| SPEC. | : I-Test > 100mA Vsupply over voltage Test>1.5x max supply voltage - 19 - Publication Release Date: 10/5/2011 Reliability Engineering Department