W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV AEC-Q100 RELIABILITY REPORT W25Q128BV, W25Q64BV W25Q64CV, W25Q32BV PART NO. : W25Q128BV FUNCTION : 128M FLASH MEMORY PROCESS : 90nm CMOS (DPTM) RA ENGINEER : RA MANAGER : -1- Publication Release Date: 11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV ~SUMMARY~ W25Q128BV for 16 SOP 300 mil passed the qualification tests according to Winbond product qualification requirement. A summary of the test result is as follows: . Endurance Cycling with HTOL : 0/231 pcs . Endurance Cycling with Data Retention : 0/231 pcs . Dynamic Early Fail Study : 0/2400 pcs . Pre-Condition Test : 0/924 pcs . High Temp. Storage Life Test : 0/231 pcs . Pressure Cooker Test : 0/231 pcs . Temperature Cycle Test : 0/231 pcs . Highly Accelerated Stress Test : 0/231 pcs . ESD-HBM : 0/36 pcs . ESD-MM : 0/36 pcs . ESD-CDM : 0/9 pcs . Latch -Up Test : 0/18 pcs -2- Publication Release Date: 11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV ---CONTENTS--. PRODUCT DESCRIPTION A. Introduction B. Features C. Function Block . LIFE TEST A. Introduction 1. Endurance Cycling with HTOL 2. Endurance Cycling with Data Retention 3. Dynamic Early Fail Study B. Test Results 1. Endurance Cycling with HTOL 2. Endurance Cycling with Data Retention 3. Dynamic Early Fail Study -3- Publication Release Date: 11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV . ENVIRONMENTAL TEST A. Introduction 1. Pre-Condition Test 2. High Temp. Storage Life Test (HTSL) 3. Pressure Cooker Test (PCT) 4. Highly Accelerated Stress Testing (HAST) 5. Temperature Cycle Test (TCT) B. Test Results 1. Pre-Condition Test 2. High Temp. Storage Life Test (HTSL) 3. Pressure Cooker Test (PCT) 4. Highly Accelerated Stress Testing (HAST) 5. Temperature Cycle Test (TCT) . ESD & LATCH-UP A. Introduction 1. ESD 2. LATCH-UP B. Test Results 1. ESD 2. LATCH-UP -4- Publication Release Date: 11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV I. PRODUCT DESCRIPTION A. Introduction The W25Q128BV (128M-bit) Serial Flash memories provide a storage solution for systems with limited space, pins and power. The 25Q series offers flexibility and performance well beyond ordinary Serial Flash devices. They are ideal for code shadowing to RAM, executing code directly from Dual/Quad SPI (XIP) and storing voice, text and data. The devices operate on a single 2.7V to 3.6V power supply with current consumption as low as 4mA active and 1µA for power-down. All devices are offered in space-saving packages. The W25Q128BV array is organized into 65,536 programmable pages of 256-bytes each. Up to 256 bytes can be programmed at a time. Pages can be erased in groups of 16 (4KB sector erase), groups of 128 (32KB block erase), groups of 256 (64KB block erase) or the entire chip (chip erase). The W25Q128BV has 4,096 erasable sectors and 256 erasable blocks respectively. The small 4KB sectors allow for greater flexibility in applications that require data and parameter storage. The W25Q128BV supports the standard Serial Peripheral Interface (SPI), and a high performance Dual/Quad output as well as Dual/Quad I/O SPI: Serial Clock, Chip Select, Serial Data I/O0(DI),I/O1(DO),I/O2(/WP), and I/O3(/HOLD). SPI clock frequencies of up to 104MHz are supported allowing equivalent clock rates of 208MHz (104MHz x 2) for Dual I/O and 320MHz (80MHz x 4) for Quad I/O when using the Fast Read Dual/Quad I/O instructions. These transfer rates can outperform standard Asynchronous 8 and 16-bit Parallel Flash memories. The Continuous Read Mode allows for efficient memory access with as few as 8-clocks of instruction-overhead to read a 24-bit address, allowing true XIP (execute in place) operation. A Hold pin, Write Protect pin and programmable write protection, with top -5- Publication Release Date: 11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV or bottom array control, provides further control flexibility. Additionally, the device supports JEDEC standard manufacturer and device identification with a 64-bit Unique Serial Number. B. Features Family of Serial Flash Memories – W25Q128BV: 128M-bit / 16M -byte – 256-bytes per programmable page – Standard SPI: CLK,/CS,DI,DO,/WP,/Hold – Dual SPI: CLK,/CS,IO0,IO1,/WP,/Hold – Quad SPI: CLK,/CS,IO0,IO1,IO2,IO3 Highest Performance Serial Flash – 104/80MHz Dual/Quad SPI clocks – 208/320MHz equivalent Dual/Quad SPI – 40MB/S continuous data transfer rate. – Up to 8X that of ordinary Serial Flash – More than 100,000 erase/write cycles – More than 20-year data retention Efficient “Continuous Read Mode” – Low Instruction overhead – Continuous Read with 8/16/32/64-Byte Wrap – As few as 8 clocks to address memory – Allows true XIP(excute in place) operation – Outperforms X16 Parallel Flash Low Power, Wide Temperature Range – Single 2.7 to 3.6V supply – 4mA active current, <1µA Power-down current – -40° C to +105°C operating range -6- Publication Release Date: 11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV Flexible Architecture with 4KB sectors – Uniform Sector Erase (4K-bytes) – Uniform Block Erase (32K and 64K-bytes) – Program one to 256 bytes – Erase/Program Suspend&Resume Advanced Security Features – Software and Hardware Write-Protect – Top / Bottom ,4KB complement array protection – Lock-Down and OTP arry protection – 64-Bit Unique Serial Number for eatch device – 4X256-Byte Security Registers with OTP locks – Volatile&Non-volatile Status Register Bits Space Efficient Packaging – 8-pad WSON 8x6-mm – 16-pin SOIC 300-mil – Contact Winbond for KGD and CSP options -7- Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV C. Function Block -8- Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV II. LIFE TEST A. Introduction 1. Endurance Cycling with HTOL 1.1 SCOPE Endurance cycling test is to measure the capability of program/erase cycle. HTOL test is performed to accelerate failure mechanisms which are thermally activated. This can be achieved by stressing the devices with bias at high temperature. 1.2 TEST CONDITION Whole chip cycling test: Temp=105°C, Td=10K Cycles with Whole Chip, pattern=00, FF, CHKBD, CHKBD\ High-Temperature Operating Life Test (HTOL): Temp ambient = 125°C ,Vdd = 3.6V, dynamic stressing, Td = 1000 hrs (AEC Q100-005) -9- Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV 2. Endurance Cycling with Data Retention 2.1 SCOPE Endurance cycling test is to measure the capability of program/erase cycle. DR test is to determine the stability of data stored in the device under high temperature environment. 2.2 TEST CONDITION Whole chip cycling test: Temp=105°C, Td=10K Cycles with Whole Chip, pattern=00, FF, CHKBD, CHKBD\ Data Retention Test (DR): Temp = 150°C , Td = 1000 hrs. (AEC Q100-005) 3. Dynamic Early Fail Study (EFR) 3.1 SCOPE EFR test is performed to accelerate infant mortality failure mechanisms which are thermally activated. This can be achieved by stressing the devices with bias at high temperature. 3.2 TEST CONDITION Temp ambient = 125°C, Vdd = 3.6V, dynamic stressing, Td = 72 hrs. (AEC Q100-008) - 10 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV B. Test Results 1.1 Endurance Cycling with HTOL RUN Whole chip HTOL- Lot No cycling: HTOL- HTOL- Remark 168 HRs 500 HRs 1000 HRs 10K #1 69514K600 0/77 0/77 0/77 0/77 #2 60034M600 0/77 0/77 0/77 0/77 #3 60030L100 0/77 0/77 0/77 0/77 *Criteria: Acc/Rej = 0/1. 1.2 FAILURE RATE CALCULATION 2 F . R.( T ) = X WHERE X 2 (1 − CL , 2 N + 2 ) 2 EDH : CHI-SQUARE Function CL : Confidence Level N : No of Failures EDH : Equivalent Device Hour Test Dev. Hours Equiv. Dev. Item at Tj=125.86°C Hours at No. of Failure Failure Rate Tj=55°C HTOL 231000 at 55°C 205243492.3 0 4.46 FIT Based on CL = 60% and Activation Energy = 1.08 eV = + • θ where :Tj= junction temp ,Ta=125 (ambient temp) Pd=18.36mW (power dissipated on the device) ja=46.9 /W (thermal resistance from junction to ambient - 11 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV 2. Endurance Cycling with Data Retention RUN Lot No Whole chip cycling: DR- DR- DR- Remark 168 HRs 500 HRs 1000 HRs 10K #1 69514K600 0/77 0/77 0/77 0/77 #2 60034M600 0/77 0/77 0/77 0/77 #3 60030L100 0/77 0/77 0/77 0/77 3. Dynamic Early Fail Study (EFR) RUN Lot No 72 Hrs #1 69514K600 0/800 #2 60034M600 0/800 #3 60030L100 0/800 Remark *Criteria: Acc/Rej = 0/1 - 12 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV III. ENVIRONMENTAL TESTS A. Introduction 1. Pre-condition Test 1.1 SCOPE Pre-condition Test is to measure the resistance of SMD (Surface Mount Devices) to the storage environment at the customer site and to thermal stress created by IR reflow or Vapor Phase Reflow. 1.2 TEST CONDITION Step 1 : TCT (-65°C/150°C, 5 cycles) Step 2 : Bake (125°C, 24 hours) Step 3 : Soak (30°C/60%RH, 192 hours) Step 4 : IR , 3 passes (JEDEC 020 D). 2. High Temperature Storage Life Test (HTSL) 2.1 SCOPE HTSL test is to determine the stability of the device in high temperature environment. 2.2 TEST CONDITION Temp = 150°C , Td = 1000 hrs. (JESD22-A103) 3. Pressure Cooker Test (PCT) 3.1 SCOPE PCT is to evaluate the device resistance to moisture penetration. 3.2 TEST CONDITION Ta = 121°C, RH = 100%, P = 2 atm, Td = 168 Hrs. (JESD22-A102-B) - 13 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV 4. Highly Accelerated Stress Testing (HAST) 4.1 SCOPE HAST is to evaluate the reliability of non hermetic packaged solid-state device in humid environments. 4.2 TEST CONDITION Ta = 130°C, Vdd=3.6V, RH% = 85%, P = 2 atm, Td = 168 Hrs. (JESD22-A110) 5. Temperature Cycle Test (TCT) 5.1 SCOPE TCT is to evaluate the resistance of device to environmental temperature change. 5.2 TEST CONDITION -65°C / 15min, transfer time 1min, +150 °C/15min, 500 cycles. (JESD22-A104) - 14 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV B. Test Result 1. Pre-condition Test Run Lot No Result #1 69514K600 0/308 #2 60034M600 0/308 #3 60030L100 0/308 Remark *Criteria : Acc/Rej = 0/1. 2. High Temperature Storage Life Test (HTSL) RUN Lot No 168 Hrs 500 Hrs 1000 Hrs Remark #1 69514K600 0/77 0/77 0/77 #2 60034M600 0/77 0/77 0/77 #3 60030L100 0/77 0/77 0/77 *Criteria : Acc/Rej = 0/1 3. Pressure Cooker Test (PCT) Run Lot No 168 Hrs #1 69514K600 0/77 #2 60034M600 0/77 #3 60030L100 0/77 Remark *Criteria : Acc/Rej = 0/1. - 15 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV 4. Highly Accelerated Stress Testing (HAST) Run Lot No 168 Hrs #1 69514K600 0/77 #2 60034M600 0/77 #3 60030L100 0/77 Remark *Criteria : Acc/Rej = 0/1. 5. Temperature Cycle Test (TCT) Run Lot No 500 Cycles #1 69514K600 0/77 #2 60034M600 0/77 #3 60030L100 0/77 Remark *Criteria : Acc/Rej = 0/1. - 16 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV IV. ESD AND LATCH-UP A. Introduction 1. ESD 1.1 SCOPE ESD test is to evaluate the immunity of device to electrostatic discharge. 1.2 TEST CONDITION Human Body Model (HBM): AEC Q100-002 Machine Model (MM): AEC Q100-003 Charge Device Model (CDM): AEC Q100-011 2. Latch-Up 2.1 SCOPE Latch-Up test is to evaluate the immunity of the devices to latch-up. 2.2 TEST CONDITION AEC Q100-004, Temp = 25 °C, VDD = Max. Operating Voltage. - 17 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV B. Test Results 1. ESD 1.1 Human Body Model Run LOT# POSITIVE NEGATIVE #1 69514K600 0/6 0/6 #2 60034M600 0/6 0/6 #3 60030L100 0/6 0/6 Remark *Criteria : Acc/Rej = 0/1. *| SPEC | : >2KV 1.2. Machine Model Run LOT# POSITIVE #1 69514K600 0/6 0/6 #2 60034M600 0/6 0/6 #3 60030L100 0/6 0/6 NEGATIVE Remark *Criteria : Acc/Rej = 0/1. *| SPEC | : >200 V 1.3. Charge Device Model Run LOT# POSITIVE / NEGATIVE #1 69514K600 0/3 #2 60034M600 0/3 #3 60030L100 0/3 Remark *Criteria : Acc/Rej = 0/1. *| SPEC | : >750V - 18 - Publication Release Date:11/19/2010 Reliability Engineering Department W25Q128BV, W25Q64BV, W25Q64CV, W25Q32BV 2. Latch-Up Run LOT# POSITIVE #1 69514K600 0/3 0/3 #2 60034M600 0/3 0/3 #3 60030L100 0/3 0/3 NEGATIVE Remark *Criteria : Acc/Rej = 0/1. *| SPEC. | : I-Test > 100mA Vsupply over voltage Test>1.5x max supply voltage - 19 - Publication Release Date:11/19/2010 Reliability Engineering Department