LA-MachXO Product Family AEC

LA-MachXO Product Family AEC-Q100 Qualification Summary
Lattice Document # 25 – 107420
December 2014
© 2014 Lattice Semiconductor Corp. All Lattice trademarks, registered trademarks, patents, and disclaimers are listed at www.latticesemi.com/legal. All other brand or product
names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
www.latticesemi.com
Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
Dear Customer,
Enclosed is Lattice Semiconductor’s LA-MachXO Product Family AEC-Q100 Qualification Summary for the
Mie101 wafer fabrication facility.
This report was created to assist you in the decision making process of selecting and using our products. The
information contained in this report represents the entire qualification effort for this device family.
The information is drawn from an extensive qualification program of the wafer technology and packaging
assembly processes used to manufacture our products. The program adheres to JEDEC and Automotive
Industry standards for qualification of the technology and device packaging. This program ensures you only
receive product that meets the most demanding requirements for Quality and Reliability.
Your feedback is valuable to Lattice. If you have suggestions to improve this report, or the data included, we
encourage you to contact your Lattice representative.
Sincerely,
James M. Orr
Vice President,
Corporate Quality & Product Development
Lattice Semiconductor Corporation
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
2
Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
INDEX
1.0
INTRODUCTION ............................................................................................................................................ 4
2.0
LATTICE AEC-Q100 QUALIFICATION PLAN ............................................................................................... 8
3.0
LATTICE AEC-Q100 QUALIFICATION DATA............................................................................................... 9
3.1
TEST GROUP A – ACCELERATED ENVIRONMENTAL TESTS........................................................................................................13
3.1.1
SURFACE MOUNT PRECONDITIONING ......................................................................................................................................13
3.1.2
BIASED H AST......................................................................................................................................................................................13
3.1.3
UNBIASED HAST................................................................................................................................................................................14
3.1.4
TEMPER ATURE C YCLING ...............................................................................................................................................................14
3.1.5
HIGH TEMPERATURE STOR AGE LIFE ........................................................................................................................................15
3.2
TEST GROUP B – ACCELERATED LIFETIME SIMULATION TESTS...............................................................................................16
3.2.1
HIGH TEMPERATURE OPERATING LIFE ....................................................................................................................................16
3.2.2
EARLY LIFE FAILURE RATE ............................................................................................................................................................16
3.2.3
NON-VOL ATILE MEMORY CYCLING ENDURANCE & HIGH TEMP D ATA RETENTION ...................................................16
3.3
TEST GROUP C – PACKAGE ASSEMBLY INTEGRITY TESTS ........................................................................................................18
3.3.1
WIRE BOND SHEAR ..........................................................................................................................................................................18
3.3.2
WIRE BOND PULL..............................................................................................................................................................................18
3.4
TEST GROUP D – DIE FABRICATION RELIABILITY TESTS .............................................................................................................19
3.4.1
ELECTROMIGR ATION ......................................................................................................................................................................19
3.4.2
TIME DEPENDENT DIELECTRIC BREAKDOWN ........................................................................................................................19
3.4.3
HOT CARRIER INJECTION ..............................................................................................................................................................19
3.4.4
NEGATIVE BIAS TEMPER ATURE INSTABIL ITY .........................................................................................................................20
3.4.5
STRESS MIGR ATION ........................................................................................................................................................................20
3.5
TEST GROUP E – ELECTRICAL VERIFICATION .................................................................................................................................21
3.5.1
PRE/POST-ELECTRICAL TEST AND ELECTRICAL DISTRIBUTIONS ...................................................................................21
3.5.2
ELECTROSTATIC DISCHARGE – HU MAN BOD Y MODEL .......................................................................................................21
3.5.3
ELECTROSTATIC DISCHARGE – CH ARGE DEVICE MODEL .................................................................................................21
3.5.4
LATCH-UP ............................................................................................................................................................................................22
3.5.5
FAULT GRADING................................................................................................................................................................................22
3.5.6
CHARACTERIZATION .......................................................................................................................................................................23
3.6
TEST GROUP F – DEFECT SCREENING ...............................................................................................................................................24
3.6.1
PART AVER AGE TESTING ..............................................................................................................................................................24
3.6.2
STATISTICAL BIN ANAL YSIS ..........................................................................................................................................................24
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
1.0 INTRODUCTION
The new class of versatile Non-Volatile PLD’s from Lattice, LA-MachXO automotive family, offers a non-volatile,
infinitely reconfigurable solution that is tested and qualified to the AEC-Q100 standard.
The LA-MachXO automotive family combines Flash and SRAM technology to provide "instant-on" capabilities in
a single low-cost device. This combination of Flash and SRAM enables easy field updates via Lattice's unique
TransFR technology.
The LA-MachXO automotive family offers flexible LUT architectures (256 to 2280 LUTs) and multiple density-I/O
combinations in Thin Quad Flat Pack (TQFP) and Fine-Pitch Thin BGA (ftBGA) packages with user I/O counts
ranging from 78 to 271 I/Os. Table 1 shows the density (LUTs), package and I/O options, along with other key
parameters for each member of the family.
The LA-MachXO automotive family features Lattice's exclusive sysCLOCK PLLs, sysMEM embedded memory
blocks (EBRs) and high-performance I/Os. The LA-MachXO automotive family also offers flexible I/O buffer
support with wide range of interfaces including LVCMOS 3.3/2.5/1.8/1.5/1.2, LVTTL, PCI, LVDS, Bus -LVDS,
LVPECL and RSDS. The LA-MachXO automotive family is in-system programmable through the standard IEEE
1532 interface. IEEE Standard 1149.1 boundary scan testing capability also allows product testing on automated
test equipment.
The LA-MachXO automotive family is built on the 130nm Flash cell based CMOS process at Fujitsu Mie fabs
and assembled at ASE Malaysia. This report details the automotive reliability qualification and device
characterization results of the LA-MachXO Product Family products at the Fujitsu Mie fabs.
The LA-MachXO datasheet is available on the Lattice Semiconductor website (www.latticesemi.com).
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
Table 1.1. LA-MachXO Automotive Product Family Attributes
Part Attributes
LAMXO
256C/E
LAXMO
640C/E
LAXMO
640C/E
LAMXO
1200E
LAMXO
1200E
LAMXO
2280E
LAMXO
2280E
LAMXO
640C/E
LAMXO
1200E
LAMXO
2280E
LAMXO
2280E
TN100
TN100
TN144
TN100
TNl44
TN100
TN144
FTN256
FTN256
FTN256
FTN324
Fujitsu - Mie, Japan
Die Fabrication Site
Package Assembly Site
ASE Malaysia
Final Test Site
ASE Malaysia
300mm
Waf er Size
Die Family (Product Line)
Die Mask Set Rev ision
LAMXO
256C/E
LAXMO
640C/E
LAXMO
1200E
LAMXO
2280E
LAXMO
640C/E
LAMXO
1200E
LAMXO
2280E
02
03
02
02
03
02
02
Fabrication Technology
EE12 (0.13um CMOS)
0.12 micron
Die Channel Length
Number of
Transistors/Gates
12 types = (S,H,U @1.2volt; F @3.3volt; Int,Enh @5.5volt) * P,N
48
4080 x
3850 x
254-305
Number of Mask Steps
Die Dimensions (W x L x T)
in microns (um)
1940 x
2030 x
254-305
2650 x
2650 x
254-305
3350 x
3350 x
254-305
Die Metallization
2650 x
2650 x
229-305
3350 x
3350 x
229-305
4080 x
3850 x
229-305
8-Cu/1-Al
9
# of Metallization Lay ers
Thickness (per metallization
lay er)
M1 295, M2-5 IL 275, M6-8 SGL 475, M9 top-Al 1140 (nm units)
Cu, Al+0.5w t%Cu
% of alloy s (if present)
SiO/SiO/SiN
Die Interconnect Dielectric
Die Passiv ation
SiO2 / SiN / Polyimide
3
# of Passiv ation Lay ers
Oxide 1400; Nitride 500; Polyimide 2000 (nm units)
Passiv ation Thickness
Die Ov ercoat Material
Wafer Saw
Die Prep Backside Method
Die Prep Backside
Metallization
Die Prep Backside
Thickness & Tolerances
N/A
N/A
Full cut
Die Separation Method
Die Separation Kerf Width
(um)
Die Separation Kerf Depth (if
not 100% saw)
25-35
NA
Silver-filled epoxy
Die Attach Material
Die Attach Method
Dispensing
Dispensing
Dispensing
Dispensing
Dispensing
TQFP /
100
Refer Bonding Diagram
TQFP / TQFP /
TQFP /
144
100
144
Die placement diagram
Package Ty pe / Pin Count
Package Outline Drawing
TQFP /
100
TQFP /
100
TQFP /
144
Dispensing
Dispensing
Dispensing
Dispensing
Dispensing
Dispensing
FTBGA /
256
FTBGA /
256
FTBGA
/ 256
FTBGA
/ 324
pl ea s e refer to: Pa cka geDi a gra ms i n l a tti ces emi .com
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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Lattice Semiconductor
Part Attributes
December 2014
LA-MachXO Automotive Qualification Summary
LAMXO
256C/E
LAXMO
640C/E
LAXMO
640C/E
LAMXO
1200E
LAMXO
1200E
LAMXO
2280E
LAMXO
2280E
LAMXO
640C/E
LAMXO
1200E
LAMXO
2280E
LAMXO
2280E
TN100
TN100
TN144
TN100
TNl44
TN100
TN144
FTN256
FTN256
FTN256
FTN324
Mold Compound Supplier/ID
Mold Compound Type
Hitachi
Sumitomo
CEL9220HFA
EMEG770HJ
Flammability Rating
UL94 V-0
Fire retardant ty pe/Composition
Glass Transition Temperature,
Tg
Coef f icient of Thermal
Expansion, CTE (abov e & below
Tg) (ppm/C)
Organic Phosphorus(P1) and Nitrogen(N2) type
Multi-Aromatic Resin
110degc
140degc
CTE 1 - 8 ppm/degc ; CTE 2- 33 ppm/degc
CTE 1 - 8 ppm/degc ; CTE 2- 40
ppm/degc
Au / 0.9 mil
Au / 1.0 mil
Wire Bond Material/Diameter
Wire Bond Methods
Thermosonic ball
Type of w ire bond at die
Type of w ire bond at
leadframe
Wirebonding diagram
Leadframe Material
Leadframe Bonding Plating
Composition
Leadframe Bonding Plating
Thickness
Paddle/Flag Material
Paddle/Flag Width/Length
(mils)
Paddle/Flag Plating
Composition
Paddle/Flag Plating
Thickness (uinch)
External Lead Plating
Composition
External Lead Plating
Thickness (uinch)
Ball Bond
Stitch Bond
84106133
84106118
84106119
84106223
84106228
84106224
84106226
84106276
84106229
Cu Alloy
100-350
84106225
100350
NA
NA
Ag
100350
84106230
100-350
NA
70-250
100350
70-250
Cu Alloy
NA
180SQ
180SQ
276SQ
200SQ
276SQ
200SQ
276SQ
NA
Ag
Ag
Ag
Ag
Ag
Ag
Ag
NA
100350
100-350
100-350
70-250
100350
70-250
100350
NA
Matte Sn (annealed)
NA
400-800
NA
Substrate Material
NA
Substrate Thickness (mm)
Number of Substrate Metal
Layers
Plating Composition of Ball
Solderable Surface
Substrate Panel Singulation
Method
Substrate Solder Ball
Composition
Substrate Solder Ball
Diameter
Die Header Material
NA
0.36
0.36
0.36
0.36
NA
2
2
2
2
NA
NiAu
NiAu
NiAu
NiAu
NA
Package
Saw
Package
Saw
Package
Saw
Package
Saw
NA
SAC305
SAC305
SAC305
SAC305
NA
20mils
20mils
20mils
25mils
Cu
BT Resin :
CCLHL832 ;
Solder
Mask :
AUS303
BT
Resin :
CCLHL832 ;
Solder
Mask :
AUS303
BT Resin :
CCLHL832 ;
Solder
Mask :
AUS303
BT Resin :
CCLHL832 ;
Solder
Mask :
AUS303
BT substrate
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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Part Attributes
December 2014
LA-MachXO Automotive Qualification Summary
LAMXO
256C/E
LAXMO
640C/E
LAXMO
640C/E
LAMXO
1200E
LAMXO
1200E
LAMXO
2280E
LAMXO
2280E
LAMXO
640C/E
LAMXO
1200E
LAMXO
2280E
LAMXO
2280E
TN100
TN100
TN144
TN100
TNl44
TN100
TN144
FTN256
FTN256
FTN256
FTN324
Thermal Resistance, qja
please refer to: Thermal Management p.9 in latticesemi.com
Thermal Resistance, qjc
please refer to: Thermal Management p.9 in latticesemi.com
Moisture Sensitivity Level
3
E: 1.141.26V
C: 1.713.465V
E: 1.14-1.26V
Operating Supply Voltage
Range (Vcc)
E: 1.14-1.26V
C: 1.71-3.465V
E: 1.14-1.26V
Comm: 0oC to +85oC
Operating Temperature
Range Tj
Ind: -40oC to +100oC
Auto: -40oC to +125oC
configuration dependent
Operating Frequency Range
see datasheet
Analog Features/Blocks
Digital Features/Blocks
Embedded Memory - Dist
RAM (Kbits)
Embedded Memory - EBR
SRAM (Kbits)
Number of PLLs
Number of I/Os
n/a
235
LUT4s
640 LUT4s
1200 LUT4s
2280 LUT4s
640
LUT4s
1200
LUT4s
2280 LUT4s
2
6.1
6.4
7.7
6.1
6.4
7.7
0
0
9.2
27.6
0
9.2
27.6
0
78
0
74
1
113
73
2
113
73
113
0
1
159
211
2
211
271
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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December 2014
LA-MachXO Automotive Qualification Summary
2.0 LATTICE AEC-Q100 QUALIFICATION PLAN
The LA-MachXO automotive family was qualified for automotive applications using the Stress Test Qualification
for Integrated Circuits, AEC-Q100-Rev-H (May 17, 2014), test requirements and methods. The LA-MachXO
automotive family operates over the Automotive Grade 2 (-40°C to +105°C) ambient operation temperature
range. All low and high temperature test read-outs were performed at the Grade 2 temperature extremes.
Today, The LA-MachXO product family is in high volume production. The MachXO devices are implemented on
a cost-effective, production-proven, low-k, 130nm Flash CMOS process with copper metallization fabricated by
Fujitsu Semiconductor Limited. The devices for this AEC-Q100 qualification were assembled in Thin Quad Flat
Pack (TQFP) packages and Saw-Singulated Pb-free Fine Pitch Thin Ball Grid Array (FTBGA) packages at ASE
Malaysia. To verify product reliability, Lattice Semiconductor maintains an active Reliability Monitor program on
the MachXO products. Lattice Semiconductor publishes the Reliability Monitor Data quarterly.
Deviations to AEC-Q100- Rev-H (May 17, 2014): None
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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December 2014
LA-MachXO Automotive Qualification Summary
3.0 LATTICE AEC-Q100 QUALIFICATION DATA
Table 3.1. LA-MachXO Product Family AEC-Q100 Test Plan and Summary of Results
Automotive Grade Level: 2 (-40 to +105C); MSL Level: 3
Supplier Name:
Supplier Code:
Supplier Part Number:
Supplier Contact:
Supplier Family Type:
Device Description:
Lattice Semiconductor Corp.
LAMXO Family
LA-MachXO family
FPGA
General Specification:
Supplier Wafer Fabrication:
Supplier Wafer Test:
Supplier Assembly Site:
Supplier Final Test Site:
Supplier Reliability Signature:
AEC-Q100 Rev. H (May 17, 2014)
Fujitsu, Mie
Lattice Semiconductor Corp.
ASE, Malaysia
ASE, Malaysia
TEST GROUP A – ACCELERATED ENVIRONMENTAL TESTS
Test
PC
(Surface Mount
Preconditioning)
#
Reference
Test Conditions
A1
JESD22-A113F
J-STD-020D.1
JESD22-A104D
Test @ Rm/Hot
5cycles -55 to 125°C TC, 24h 125C Bake,
192h 30°C/60%RH TH, 260°C Reflow
Test @ Rm/Hot
+130°C/85%RH, 96 hours; VCC=1.26V,
VCCIO=3.47, VCCAUX=3.47V, alternate pin
biasing
Test @ Rm/Hot
+110°C/85%RH, 264 hours; VCC=1.26V,
VCCIO=3.47, VCCAUX=3.47V, alternate pin
biasing
Test @ Rm/Hot
+130°C/85%RH, 96 hours
Test @ Rm/Hot
+110°C/85%RH, 264 hours
BHAST
(Biased Highly
Accelerated Stress
Test)
A2
UHAST
(Unbiased Highly
Accelerated Stress
Test)
A3
TC
(Temperature Cycling)
A4
JESD22-A104D
AEC-Q100
RevG/H
Test @ Hot
1000 cycles -55 to 125°C
HTSL
(High Temp Storage
Life)
A6
JESD22-A103D
AEC-Q100
RevG/H
Test @ Rm/Hot
+150°C, 500 hours
JESD22-A110D
AEC-Q100
RevG/H
JESD22-A118A
AEC-Q100
RevG/H
DEVICE
Lots
SS/Lot
(units)
Total
RESULTS
LAMXO2280E-02-FTN324
LAMXO2280E-02-FTN256
LAMXO2280E-02-TN100
LAMXO2280E-02-TN144
3
1
3
3
738
231
738
231
0 failures
0 failures
0 failures
0 failures
LAMXO2280E-02-TN100
3
231
0 failures
231
0 failures
231
0 failures
231
0 failures
231
231
231
231
0 failures
0 failures
0 failures
0 failures
45
0 failures
45
0 failures
77
LAMXO2280E-02-FTN324
3
LAMXO2280E-02-TN100
3
77
LAMXO2280E-02-FTN324
3
LAMXO2280E-02-FTN324
LAMXO2280E-02-FTN256
LAMXO2280E-02-TN100
LAMXO2280E-02-TN144
3
1
3
3
LAMXO2280E-02-FTN324
3
LAMXO2280E-02-TN100
3
77
45
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP B – ACCELERATED LIFETIME SIMULATION TESTS
Test
HTOL
(High Temp Operating
Life)
ELFR
(Early Life Failure Rate)
NVCE + HTDR
(Non-volatile Cycling
Endurance + High Temp
Data Retention)
#
B1
Reference
JESD22-A108D
AEC-Q100
RevG/H
B2
JESD22-A108D
AEC-Q100008A
AEC-Q100
RevG/H
B3
AEC-Q100005D1
AEC-Q100
RevG/H
Extended NVCE
Lots
SS/Lot
(units)
Total
RESULTS
LAMXO2280E-02-FTN324
3
77
231
0 failures
LAMXO640C-03-FTN256
3
77
231
0 failures
Test @ Rm/Hot/Cold
+105°C ambient, 48 hours; pattern
continuously exercised at VCC=1.26V,
VCCIO=2.63, VCCAUX=3.47V
LAMXO2280E-02-FTN324
3
800
2400
0 failures
Test @ Rm/Hot
1000 hours, +150°C ambient
LAXP2-17E-FTN256*
3
77
231
0 failures
Test @ Rm/Hot
20u split between room/hot and chk/chk#
running at 40k cycles
LAMXO2280E-02-TN100
1
80
80
0 failures
Test Conditions
DEVICE
Test @ Rm/Hot/Cold
+105°C ambient, 1000 hours; pattern
continuously exercised at VCC=1.26V,
VCCIO=2.63, VCCAUX=3.47V
Test @ Rm/Hot/Cold
+105°C ambient, 1000 hours; pattern
continuously exercised at VCC=3.47V,
VCCIO=3.47, VCCAUX=3.47V
* The LAMXO uses the same Flash memory cells and are fabricated in the same wafer fab as the LAXP2 which follows AEC-Q100 Appendix 1: Definition
of a Product Qualification Family. Therefore, the LAMXO Flash Non-volatile Cycling Endurance + High Temp Data Retention is Qualified-by-Similarity
from the LAXP2 Non-volatile Cycling Endurance + High Temp Data Retention qualification data.
TEST GROUP C – PACKAGE ASSEMBLY INTEGRITY TESTS
Test
WBS
(Wire Bond Shear Test)
WBP
(Wire Bond Pull Test)
#
C1
C2
Reference
AEC-Q100001C
AEC-Q100
RevG/H
MIL-STD883G, Method
2011.7
AEC-Q100
RevG/H
Test Conditions
DEVICE
5 bonds tested per device, 45 bonds
total/package
5 bonds tested per device, 45 bonds
total/package
Lots
SS/Lot
(units)
Total
RESULTS
9
Cpk >2.01
LAMXO2280E-02-FTN324
3
LAMXO2280E-02-TN144
3
9
Cpk >1.74
LAMXO2280E-02-FTN324
3
9
Cpk >2.70
LAMXO2280E-02-TN144
3
9
Cpk >1.70
3
3
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP D – DIE FABRICATION RELIABILITY TESTS
Test
#
Reference
Test Conditions
RESULTS
EM
(Electromigration)
D1
JESD61A.01
0.1% cumulative failure rate @ +125°C and design rule limits for current
density
PASS, > 16 years
TDDB
(Time Dependent
Dielectric Breakdown)
D2
JESD35-A
@ +125°C and Vccmax, for 0.1% cumulative failure rate for the maximum
allowed gate area device
PASS, > 220 years
HCI
(Hot Carrier Injection)
D3
JESD28-1
JESD60A
@ Vccmax, room temperature and Isubmax
PASS, > 18 years
NBTI
(Negative Bias
Temperature Instability)
D4
JESD90
@ Vccmax, +125°C temperature for SAT = 10%.
PASS, > 68 years
SM
(Stress Migration)
D5
JESD87
@ +125°C
PASS, > 11 years
TEST GROUP E – ELECTRICAL VERIFICATION
Test
#
TEST
(Pre and Post-Stress
Electrical Test)
E1
HBM
(Electrostatic Discharge Human Body Model)
E2
Reference
Test Conditions
DEVICE
AEC
Q100-007
AEC
Q100-002
Test @ Rm/Hot
3 units at each stress voltage
LAMXO2280E-02-FTN324
LAMXO1200E-02-FTN256
LAMXO640E-03-FTN256
LAMXO640C-03-FTN256
LAMXO256E-02-TN100
LAMXO256C-02-TN100
Lots
SS/Lot
(units)
Total
RESULTS
All
All
All
Testing Completed
12
12
12
12
12
12
12
>2000V (H2)
>1500V (H1C)
>2000V (H2)
>2000V (H2)
>2000V (H2)
>2000V (H2)
1
1
1
1
1
1
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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Lattice Semiconductor
Test
CDM
(Electrostatic Discharge Charge Device Model)
LU
(Latch Up)
December 2014
#
E3
E4
Reference
AEC-Q100011C1
AEC-Q100
RevG/H
AEC-Q100004D
JEDEC
EIA/JESD78
AEC-Q100
RevG/H
LA-MachXO Automotive Qualification Summary
Test Conditions
Test @ Rm/Hot)
3 units at each stress voltage
Test @ Rm/Hot
6units/test (I-test/Vsupply
over-voltage test)
ED
(Electrical Distributions)
E5
AEC-Q100-009
Test @ Rm/Hot/Cold
FG
(Fault Grading)
E6
AEC-Q100007B
Design Simulations of Test
Coverage
CHAR
(Characterization)
E7
AEC-Q003
Test @ Rm/Hot/Cold
DEVICE
Lots
SS/Lot
(units)
Total
RESULTS
12
12
12
12
12
12
12
>1000V (C6)
>1000V (C6)
>1000V (C6)
>1000V (C6)
>1000V (C6)
>1000V (C6)
>100mA & >1.5X supply
(Class II)
>100mA & >1.5X supply
(Class II)
>100mA & >1.5X supply
(Class II)
>100mA & >1.5X supply
(Class II)
>100mA & >1.5X supply
(Class II)
>100mA & >1.5X supply
(Class II)
LAMXO2280E-02-FTN324
LAMXO1200E-02-FTN256
LAMXO640E-03-FTN256
LAMXO640C-03-FTN256
LAMXO256E-02-TN100
MXO256C-02-TN100
1
1
1
1
1
1
LAMXO2280E-02-FTN324
1
3
LAMXO1200E-02-FTN256
1
3
LAMXO640E-03-FTN256
1
3
3
LAMXO640C-03-FTN256
1
3
LAMXO256E-02-TN100
1
3
LAMXO256C-02-TN100
1
3
All
3
300
Pass
Fault coverage = 91.3%
All
3
2,933
Pass
TEST GROUP F – DEFECT SCREENING TESTS
Test
#
Reference
PAT
(Process Average
Testing)
F1
AEC-Q001
SBA
(Statistical Bin/Yield
Analysis)
F2
AEC-Q002A
DEVICE
Lots
SS/Lot
(units)
Total
RESULTS
All
All
All
All
Pass
Wafer
All
All
All
Pass
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
Return to INDEX
12
Lattice Semiconductor
3.1
December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP A – ACCELERATED ENVIRONMENTAL TESTS
3.1.1 SURFACE MOUNT PRECONDITIONING
The Surface Mount Preconditioning (SMPC) Test is used to model the surface mount assembly conditions during
component solder processing. All devices, stressed through Biased HAST, Unbiased HAST, Temperature
Cycling and Power Temp Cycling and High Temperature Storage Life were preconditioned.
Consistent with JEDEC JESD22-A113F “Preconditioning of Nonhermetic Surface Mount Devices Prior to
Reliability Testing”, the devices are subjected to 5 temperature cycles between -55°C and +125°C in an air
environment, a moisture bake out for 24 hours at +125°C, a controlled moisture soak for 192 hours at 30°C/60%
relative humidity, followed by 3 cycles through Pb-free 260°C reflow simulation temperature profile as defined in
IPC/JEDEC J-STD-020D.1 “Moisture/Reflow Sensitivity Classification for Nonhermetic Solid State Surface
Mount Devices”. This preconditioning is consistent with JEDEC Moisture Sensitivity Level 3 package moisture
sensitivity and dry-pack storage requirements. 40x visual inspection was performed pre and post-SMPC process.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E devices pre and post- reliability
stress. No failures were observed.
PRODUCT
PACKAGE
FTN324
LAMXO2280E-02
TN100
TN144
FTN256
LOT
QM424MXOA
QM424MXOB
QM424MXOC
QM424MXOD
QM424MXOE
QM424MXOF
QM424MXOG
QM424MXOH
QM424MXOI
QM424MXOJ
FABLOT
4K6416701
4K6426901
4K6435601
4K6416701
4K6426901
4K6463001
4K6416701
4K6426901
4K6463001
4K6416701
QTY
276
276
276
276
276
276
77
77
77
224
FAIL
0
0
0
0
0
0
0
0
0
0
3.1.2 BIASED HAST
Highly Accelerated Stress Test (HAST) testing uses both pressure and temperature to accelerate penetration of
moisture into the package and to the die surface. The Biased HAST test is used to accelerate threshold shifts
in the MOS device associated with moisture diffusion into the gate oxide region as well as electrochemical
corrosion mechanisms within the device package. Consistent with JEDEC JESD22-A110D “Highly-Accelerated
Temperature and Humidity Stress Test (HAST)”, the biased HAST conditions are with VCC and VCCI/O/VCCAUX bias
of 1.26V and 3.47V, respectively and alternate pin biasing in an ambient of either +130°C, 85% relative humidity
for 96 hrs or +110°C, 85% relative humidity for 264 hrs.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E devices pre and post- reliability
stress. No failures were observed.
PRODUCT
PACKAGE
FTN324
LAMXO2280E-02
PACKAGE
TN100
LOT
QM424MXOA
QM424MXOB
QM424MXOC
LOT
QM424MXOD
QM424MXOE
QM424MXOF
FABLOT
4K6416701
4K6426901
4K6435601
FABLOT
4K6416701
4K6426901
4K6463001
QTY
77
77
77
QTY
77
77
77
FAIL (110C/264hrs)
0
0
0
FAIL (130C/96hrs)
0
0
0
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
Return to INDEX
13
Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
3.1.3 UNBIASED HAST
Unbiased Highly Accelerated Stress Test (uHAST) testing uses both pressure and temperature to accelerate
penetration of moisture into the package and to the die surface. The Unbiased HAST test is designed to detect
ionic contaminants present within the package or on the die surface, which can cause galvanic corrosion.
Consistent with JEDEC JESD22-A118A, “Accelerated Moisture Resistance - Unbiased HAST,” the uHAST
conditions are +130°C, 85% relative humidity for 96 hrs or +110°C, 85% relative humidity for 264 hrs.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E devices pre and post- reliability
perstress. No failures were observed.
PRODUCT
PACKAGE
FTN324
LAMXO2280E-02
PACKAGE
TN100
LOT
QM424MXOA
QM424MXOB
QM424MXOC
LOT
QM424MXOD
QM424MXOE
QM424MXOF
FABLOT
4K6416701
4K6426901
4K6435601
FABLOT
4K6416701
4K6426901
4K6463001
QTY
77
77
77
QTY
77
77
77
FAIL (110C/264hrs)
0
0
0
FAIL (130C/96hrs)
0
0
0
3.1.4 TEMPERATURE CYCLING
The Temperature Cycling (TC) Test is used to accelerate those failures resulting from mechanical stresses
induced by differential thermal expansion of adjacent films, layers, and metallurgical interfaces in the die and
package. Devices are exposed for 1000 cycles between -55°C and +125°C in an air environment consistent
with JEDEC JESD22-A104D “Temperature Cycling” and AEC-Q100 RevG Grade 2 Temperature Cycling Stress
requirements.
The LAMXO2280E in the FTN256 and TN100 has the largest die-to-package ratio while the FTN324 and TN144
has the largest package size in Saw Singulated and Thin Quad Flat Pack packages, respectively. These were
chosen as the generic qualification vehicle for Temperature Cycling.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E devices pre and post- reliability
stress. No failures were observed. Wire bond pull strength was found to be >2.5 grams on 9 devices from FTN324
and TN144 sampled post-temperature cycling stress.
PRODUCT
PACKAGE
FTN324
LAMXO2280E-02
TN100
TN144
FTN256
LOT
QM424MXOA
QM424MXOB
QM424MXOC
QM424MXOD
QM424MXOE
QM424MXOF
QM424MXOG
QM424MXOH
QM424MXOI
QM424MXOJ
FABLOT
4K6416701
4K6426901
4K6435601
4K6416701
4K6426901
4K6463001
4K6416701
4K6426901
4K6463001
4K6416701
QTY
77
77
77
77
77
77
77
77
77
224
FAIL
0
0
0
0
0
0
0
0
0
0
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
Return to INDEX
14
Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
3.1.5 HIGH TEMPERATURE STORAGE LIFE
High Temperature Storage Life (HTSL) Test is typically used to determine the effect of time and temperature,
under storage conditions, for thermally accelerated failure mechanisms of solid state electronic devices. Devices
were stressed at +150°C for 500 hrs consistent with JEDEC JESD22-A103D “High Temperature Storage Life”
and AEC-Q100 RevG Grade 2-4 High Temp Storage Life stress requirements.
All units were tested and data-logged +25°C/+105°C for the LAMXO2280E devices pre and post- reliability
stress. No failures were observed.
PRODUCT
PACKAGE
FTN324
LAMXO2280E-02
TN100
LOT
QM424MXOA
QM424MXOB
QM424MXOC
QM424MXOD
QM424MXOE
QM424MXOF
FABLOT
4K6416701
4K6426901
4K6435601
4K6416701
4K6426901
4K6463001
QTY
45
45
45
45
45
45
FAIL
0
0
0
0
0
0
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
Return to INDEX
15
Lattice Semiconductor
3.2
December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP B – ACCELERATED LIFETIME SIMULATION TESTS
3.2.1 HIGH TEMPERATURE OPERATING LIFE
The High Temperature Operating Life (HTOL) Test is used to thermally accelerate those wear out and failure
mechanisms that would occur as a result of operating the device continuously in a system application. A pattern
specifically designed to exercise the maximum amount of circuitry is programmed into the device and this pattern
is continuously exercised at VCC and VCCI/O bias of 1.26V and 2.63V (VCCAUX = 3.47V), respectively for the low
voltage (MOX2280E) devices and 3.47V and 3.47V (VCCAUX = 3.47V), respectively, for the upper voltage
(MXO640C) devices at +105°C ambient for 1000 hrs consistent with JEDEC JESD22-A108D “Temperature,
Bias, and Operating Life” and AEC-Q100 RevG Grade 2 High Temperature Operating Life stress requirements.
All units were tested and data-logged at -40°C/+25°C/+105°C for the LAMXO2280E and LAMXO640C devices
pre and post- reliability stress. No failures or significant parameter shifts were observed.
PRODUCT
PACKAGE
LAMXO2280E-02
FTN324
LAMXO640C-03
FTN256
LOT
QM424MXOA
QM424MXOB
QM424MXOC
QM424MXOM
QM424MXON
QM424MXOO
FABLOT
4K6416701
4K6426901
4K6435601
4K6564601
4K6581801
4K6590801
QTY
77
77
77
77
77
77
FAIL
0
0
0
0
0
0
3.2.2 EARLY LIFE FAILURE RATE
An Early Life Failure Rate (ELFR) evaluation is generated using the HTOL test conditions to verify device quality.
ELFR is used to thermally accelerate those wear out and failure mechanisms that would occur as a result of
operating the device continuously in a system application. A pattern specifically designed to exercise the
maximum amount of circuitry is programmed into the device and this pattern is continuously exercised at VCC
and VCCI/O bias of 1.26V and 2.63V (VCCAUX = 3.47V), respectively, for the low voltage (MOX2280E) devices at
+105°C ambient for 48 hrs consistent with AEC-Q100-008 RevA “Early Life Failure Rate” .
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E devices pre and post- reliability
stress. No failures were observed.
PRODUCT
PACKAGE
LAMXO2280E-02
FTN324
LOT
QM424MXOA
QM424MXOB
QM424MXOC
FABLOT
4K6416701
4K6426901
4K6435601
QTY
800
800
800
FAIL
0
0
0
3.2.3 NON-VOLATILE MEMORY CYCLING ENDURANCE & HIGH TEMP DATA RETENTION
The LAMXO uses the same Flash memory cells and are fabricated in the same wafer fab as the LAXP2. (See
AEC-Q100 Appendix 1: Definition of a Product Qualification Family). Therefore, the LAMXO Flash NVM Cycling
Endurance & Data Retention is Qualified-by-Similarity from the LAXP2 HTRX data.
Since the LAXP2 uses Flash memory cells, qualification testing includes the AEC-Q100-005-Rev-B, Nonvolatile
Memory Program/Erase Endurance, Data Retention, and Operational Life Test. The normal mode of the LAXP2
Flash Array is unbiased (Idle mode).
High Temperature Data Retention test measures the Flash cell reliability while the High Temperature Operating
Life test is structured to measure functional operating circuitry failure mechanisms. The High Temperature Data
Retention test is specifically designed to accelerate charge gain on to or charge loss off of the floating gates in
the device's array. Since the charge on these gates determines the actual pattern and function of the device,
this test is a measure of the reliability of the device in retaining programmed information. During normal
operation, the Flash cells are unbiased after initial power on configuration. Therefore, in High Temperature Data
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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16
Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
Retention, the Flash cell reliability is determined by monitoring the cell margin after unbiased 150°C storage. All
cells in all arrays are life tested in both programmed and erased states.
Prior to data retention testing, all LAXP2 devices are programmed and erased 10,000 times.
All units were tested and data-logged at -+25°C/+105°C prior to reliability stress and after reliability stress. No
failures or significant parameter shifts were observed.
PRODUCT
PACKAGE
LAXP2-17E
FTN256
LOT
8
9
10
QTY
100
80
80
FAIL
0
0
0
Additionally, 80u of LAMXO2280E devices are split into 20u room/hot/chk/chk# matrix combination and are
subjected to extended program/erase cycles in order to exercise high voltage control circuits in the flash array
that will verify no difference in 300mm reliability.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E devices pre and post- reliability
stress. No failures were observed up to 40,000 program/erase cycles.
PRODUCT
PACKAGE
LOT
FABLOT
LAMXO2280E-02
TN100
QM411MXOJ
4K6416701
CONDITION
CHK @ 25C
CHK @ 85C
CHK# @ 25C
CHK# @ 85C
QTY
20
20
20
20
FAIL
0
0
0
0
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
Return to INDEX
17
Lattice Semiconductor
3.3
December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP C – PACKAGE ASSEMBLY INTEGRITY TESTS
3.3.1 WIRE BOND SHEAR
Wire Bond Shear (WBS) Test is used to measure the strength of the interface between a gold ball bond and a
package bonding surface on post-encapsulation devices. This strength measurement is extremely important in
determining the integrity of the metallurgical bond which has been formed and the reliability of gold wire bonds
to die or package bonding surfaces. Wire bond shear was tested consistent with the AEC-Q100-001 RevC “Wire
Bond Shear Test”.
Forty-five bonds from nine devices per package were used for the Wire Bond Shear test. All bond shear readings
were >23.7 grams and >23.4 grams passing the minimum shear strength for a 324-ball ftBGA package with 1.7
mils ball bond diameter and a 144-ball TQFP package with 1.9 mils ball bond diameter, respectively.
The average measured bond shear results were Cpk of >2.01 for FTN324 and Cpk of >1.74 for TN144.
3.3.2 WIRE BOND PULL
Wire Bond Pull (WBP) Test is used to measure the wire bond strength at the ball joints and stitch bonds. Wire
bond strength was tested consistent with Military Standard MIL-STD-883G, Method 2011.7 “Bond Strength”.
Forty-five bonds from nine devices per package were used for Wire Bond Pull test. All bond pull readings were
>5.7 grams and >4.2 grams for a 324-ball ftBGA package and a 144-ball TQFP package, respectively, passing
the minimum bond strength for a 0.9 mil gold wire post-seal.
The average measured bond pull strength results were Cpk of >2.70 for FTN324 and Cpk of >1.70 for TN144.
.
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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18
Lattice Semiconductor
3.4
December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP D – DIE FABRICATION RELIABILITY TESTS
3.4.1 ELECTROMIGRATION
When a metal conductor conducts electrons some degree of metal atom fluence occurs due to electron impact
with the metal conductor atoms. Over time this fluence of metal atoms results in a voiding of the metal upstream
from the electron current and a pile-up of metal atoms downstream. The metal line will eventually fail due to an
“open” upstream or due to shorting to adjacent metal lines downstream (extrusion).
The Electromigration Lifetime (EML) of a given conductor is highly dependent on current density and
temperature. MOS technology features a high density of metal conductors at more than one level on the chip.
This results in large current density in numerous areas on chip and a definite susceptibility to EML failure. The
130 nm Flash technology design rules prevent extrusion by minimum spacing requirements and prevents “opens”
by imposing current density limits.
The EML resistance of a MOS technology also depends upon the conductor material properties and upon the
conductor line width and thickness control, especially over “terrain”.
The EML lifetime is monitored by applying accelerated conditions of constant current density and temperature.
The stress data is used to predict conductor lifetime under maximum design rule current density and maximum
device temperature. A minimum 10 year lifetime for EML is required by Lattice Semiconductor for all
technologies in production.
The LA-MachXO family electromigration lifetimes for a 0.1% cumulative failure rate are >16 years @ +125°C
and design rule limits for current density.
3.4.2 TIME DEPENDENT DIELECTRIC BREAKDOWN
The lifetimes of the insulator elements of MOS technology depend upon their inherent material properties and
also upon their environment, e.g. the electric field strength applied and the temperature.
When any insulator in a MOS circuit fails the circuit itself either fails or exhibits errors in operation. The most
critical insulators are the MOSFET Gate oxides because the electric field strength applied to them is m uch
greater than that applied to any other part of the circuit.
When an electric field (voltage) is applied to an oxide a small current flows in the direction of the field vector.
The charge carriers are normally electrons and some of them become trapped in the oxide. The total amount of
trapped charges (electrons) is a function of time, temperature, and oxide quality. The trapped charge eventually
reaches the point where the internal electric field generated by these trapped charges overcomes the (opposite)
applied field and then exceeds the dielectric strength of the oxide. At this point the oxide fails (becomes shorted).
The effect is called Time Dependent Dielectric Breakdown (TDDB).
TDDB stress is monitored by accelerated conditions of constant applied electric field strength and temperature.
The stress time to fail data is used to predict dielectric lifetime under constant worst case circuit conditions. All
Lattice Semiconductor technologies require the gate oxides to survive 10 years lifetime under maximum design
rule conditions.
The TDDB lifetimes for the LA-MachXO family are >220 years @ +125°C and VCCMAX, for 0.1% cumulative failure
rate for the maximum allowed gate area device.
3.4.3 HOT CARRIER INJECTION
The lifetime of a MOSFET is determined by the rate of change of its operational device parameters.
When one or more of these device parameters degrades in excess of the limits of the circuit design requirements
for the device, the circuit can; lose speed, intermittently lose data, exhibit logic errors, and eventually fail to
operate.
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
19
Return to INDEX
Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
Two of the MOSFET parameters that have been observed to be the most problematical are the Threshold
Voltage and the Transconductance. For an N-Channel MOSFET the transconductance decreases and the
threshold voltage increases with time. This effect is a result of charge trapping in the gate oxide which is induced
by excess substrate current and is dependent upon the actual device’s bias conditions within the circuit
configuration. The degradation mechanism is called “hot” carrier (HC) because the channel charge carriers have
energy in excess of that required to breach the oxide-silicon barrier and then cause trapping in the oxide.
Transconductance is directly proportional to the linear region current and is not an extrapolated measurement.
However, the drive current, IDSAT, is the most useful parameter to monitor. A degradation of 10% in IDSAT is
considered to be the point where many circuits will start to exhibit some form of circuit performance effects.
Therefore, for purposes of monitoring, a 10% decrease in IDSAT is considered a “fail”.
Despite the name, Hot Carrier degradation is worse at low temperatures than at higher temperatures largely
because the substrate current decreases with increasing temperature. Hot carrier degradation is monitored at
room temperature in order to accelerate the test and to provide a safety factor in lifetime predictions. Lattice
Semiconductor requires greater than 10 years predicted lifetime for all of its production technologies.
The LA-MachXO products’ Hot Carrier Injection AC lifetime is >18 years @ VCCMAX, room temperature and
ISUBMAX.
3.4.4 NEGATIVE BIAS TEMPERATURE INSTABILITY
Degradation of P Channel transistors at negative Vg when all other terminals are zero has been shown to
represent a significant circuit condition below 130 nm gate widths. A similar positive Vg effect exists for N
channels at 90nm gate widths and smaller. Negative Bias Temperature Instability (NBTI) is dominant at elevated
temperature and Vg. The same degradation parameters and percentage as for HCI are applied to NBTI. Stress
is performed at Tjrel at 3 or more elevated Vg (>2*Vcc). The time to fail (TTF) is plotted vs Vg or 1/Vg and
extrapolated to nominal VG to obtain the lifetime.
The most commonly reported parameters are Idsat and Vth. It is also useful to use a specific Vth shift in place
of “10%” to quote lifetime (e.g. 50 mV). TTF is reported at Tstress = Tjrel.
The LA-MAchXO products’ NTBI is >68 years @ VCCMAX, +125°C temperature for DSAT = 10%.
3.4.5 STRESS MIGRATION
Microscopic voids exist in Dual Damascene Copper structures. These voids can migrate when driven by
elevated temperature and they can coalesce into larger voids, which eventually cause open metal lines. Stress
in surrounding material (e.g. the IMD) also drives void migration. In most cases the highest stress point is where
the top of the Via meets the metal line. For each metal group a large Via chain (typically >1e6 Vias total) is
designed which incorporates all metal lines and vias within the metal group. A change in via resistance of 10%
is the convention for a failure. Stress is conducted unbiased at Tjrel (or higher). Readpoints are taken at selected
intervals usually with a given maximum stress time limit (1000hr). The Arrhenius equation (and a geometrical
form factor for the DUT) is used to calculate the min TTF from the max stress limit if no fails occur. Otherwise,
a lognormal plot is used.
The LA-MachXO family Stress Migration lifetimes are >11 years @ 125°C.
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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20
Lattice Semiconductor
3.5
December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP E – ELECTRICAL VERIFICATION
3.5.1 PRE/POST-ELECTRICAL TEST AND ELECTRICAL DISTRIBUTIONS
All the pre and post-stress electrical tests performed on the LA-MachXO production test system included DC,
AC, and functional tests with datalogging of key parameters enabled.
Electrical Distribution assessment was done using material sampled from nominal wafers from production tested
at -40°C/+25°C and +105°C for the LAMXO2280E, LAMXO1200E, LAMXO640E/C and LAMXO256E/C devices.
All data is within PAT limits for all test temps.
A Parametric Drift of Individuals assessment was also done using the parametric data collected at each readout
of each stress to determine any significant device performance changes for each stress test consistent with
reference document AEC-Q100-009 RevB “Electrical Distributions Assessment”, section 3.6. A copy of the
results is available upon request.
3.5.2 ELECTROSTATIC DISCHARGE – HUMAN BODY MODEL
Each member of the LA-MachXO product family was tested per the AEC-Q100-002 RevD “Human Body Model
(HBM) Electrostatic Discharge (ESD) Test” criteria for measuring HBM ESD Sensitivity of electronic devices.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E, LAMXO1200E, LAMXO640E/C
and LAMXO256E/C devices pre and post- reliability stress. HBM performance for this product meets AEC-Q100002D Classification H1C.
PRODUCT
PACKAGE
LOT
HBM PASSING VOLTAGE
AEC-Q100-002
Component Classification
LAMXO2280E-02
LAMXO1200E-02
LAMXO640E-03
LAMXO640C-03
LAMXO256E-02
LAMXO256C-02
FTN324
QM411MXOE
QM424MXOL
QM424MXOP
QM424MXOM
QM424MXOR
QM424MXOQ
>2000V
>1500V
>2000V
>2000V
>2000V
>2000V
H2
H1C
H2
H2
H2
H2
FTN256
TN100
3.5.3 ELECTROSTATIC DISCHARGE – CHARGE DEVICE MODEL
Each member of the LA-MachXO product family was tested per the AEC-Q100-011 RevB “Charge Device Model
(CDM) Electrostatic Discharge Test” criteria for measuring CDM ESD sensitivity of electronic devices.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E, LAMXO1200E, LAMXO640E/C and
LAMXO256E/C devices pre and post- reliability stress. CDM performance for this product meets AEC-Q100-011B
Classification C6.
PRODUCT
PACKAGE
LOT
CDM PASSING VOLTAGE
AEC-Q100-011
Component Classification
LAMXO2280E-02
LAMXO1200E-02
LAMXO640E-03
LAMXO640C-03
LAMXO256E-02
LAMXO256C-02
FTN324
QM411MXOE
QM424MXOL
QM424MXOP
QM424MXOM
QM424MXOR
QM424MXOQ
>1000V
>1000V
>1000V
>1000V
>1000V
>1000V
C6
C6
C6
C6
C6
C6
FTN256
TN100
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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21
Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
3.5.4 LATCH-UP
Each member of the LA-MachXO product family was tested per the AEC-Q100-004 RevC “IC Latch-up Test”
criteria, which references the JEDEC EIA/JESD78 IC Latch-up Test procedure.
All units were tested and data-logged at +25°C/+105°C for the LAMXO2280E, LAMXO1200E, LAMXO640E/C and
LAMXO256E/C devices pre and post- reliability stress. No failures were observed within the passing
classification.
PRODUCT
PACKAGE
LOT
I-TEST LATCHUP RESULTS
LAMXO2280E-02
LAMXO1200E-02
LAMXO640E-03
LAMXO640C-03
LAMXO256E-02
LAMXO256C-02
FTN324
QM411MXOE
QM424MXOL
QM424MXOP
QM424MXOM
QM424MXOR
QM424MXOQ
>100mA @ +105C
>100mA @ +105C
>100mA @ +105C
>100mA @ +105C
>100mA @ +105C
>100mA @ +105C
JEDEC/JESD78
LATCH UP LEVEL
Class II
Class II
Class II
Class II
Class II
Class II
PRODUCT
PACKAGE
LOT
V-SUPPLY OVERVOLTAGE
TEST LATCHUP RESULTS
JEDEC/JESD78
LATCH UP LEVEL
LAMXO2280E-02
LAMXO1200E-02
LAMXO640E-03
LAMXO640C-03
LAMXO256E-02
LAMXO256C-02
FTN324
QM411MXOE
QM424MXOL
QM424MXOP
QM424MXOM
QM424MXOR
QM424MXOQ
FTN256
TN100
FTN256
TN100
>1.5x V-supply @
>1.5x V-supply @
>1.5x V-supply @
>1.5x V-supply @
>1.5x V-supply @
>1.5x V-supply @
+105C
+105C
+105C
+105C
+105C
+105C
Class
Class
Class
Class
Class
Class
II
II
II
II
II
II
3.5.5 FAULT GRADING
The fault coverage for the LA-MachXO family was calculated to be 91.3%.
--------
*****************************************************************************
*
*
*
SynTest TurboFault 2005
*
*
*
*
Fault Simulation Coverage Report
*
*
*
*****************************************************************************
------
*****************************************************************************
*
*
*
Statistic Data
*
*
*
*****************************************************************************
-- Number of Faults:
-- Number of Collapsed Faults:
844791
709762
-----------
457098
176015
138177
62677
0
0
7
10815
2
0
Number
Number
Number
Number
Number
Number
Number
Number
Number
Number
of
of
of
of
of
of
of
of
of
of
Hard Detected Faults:
Probably Detected Faults:
Potentially Detected Faults:
Undetected Faults:
Hyperactive Faults:
Hypertrophic Faults:
Oscillatory Faults:
Untestable Faults:
Error Faults:
Uncompleted Faults:
-- Coverage Number:
-- Optimal Coverage Number:
54.1078%
74.9432%
-- Total Fault Coverage (Hard + Probable + Pot)
91.2995%
( 54.1078%)
( 20.8353%)
( 16.3564%)
( 7.4192%)
( 0.0000%)
( 0.0000%)
( 0.0008%)
( 1.2802%)
( 0.0002%)
( 0.0000%)
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
22
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Lattice Semiconductor
December 2014
LA-MachXO Automotive Qualification Summary
All fault simulations were performed using the Syntest TurboFault 2005 fault simulator.
Fault simulation and analysis was performed by generating a gate-level model of the MachXO-256 device
and applying all applicable functional test vectors from the manufacturing test programs.
The LA-MachXO family of devices was developed using a design-reuse methodology (i.e.: all family members
were built from a “common design element” library). Similarly, the manufacturing test patterns and test
methodologies were also common to all family members and, as such, the MachXO -256 fault simulation
results are deemed to be representative of all devices in the family.
3.5.6 CHARACTERIZATION
Each device in the Automotive LA-MachXO family was characterized at the time of product release over the
automotive temperature range of –40°C to +125°C. In all cases, characterization was performed over CD
and Vt process splits in order to gather performance data across the entire process distribution for those
parameters. These reports are available upon request.
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
Return to INDEX
23
Lattice Semiconductor
3.6
December 2014
LA-MachXO Automotive Qualification Summary
TEST GROUP F – DEFECT SCREENING
3.6.1 PART AVERAGE TESTING
Part Average Testing (PAT) is a method for removing units with statistically abnormal characteristics (outliers)
from semiconductors supplied to automotive customers. PAT based on LA-MachXO device characterization has
been implemented into the automotive flow manufacturing test programs per the AEC-Q001 RevC “Guidelines
for Part Average Testing”. A copy of the PAT results is available upon request.
3.6.2 STATISTICAL BIN ANALYSIS
Statistical Bin Yield Analysis (SBYA) is a method for screening rogue wafers using statistically generated
screens. SBYA based on LA-MachXO device characterization has been implemented into the automotive
flow manufacturing test programs per the AEC-Q002-Rev-A Guidelines for Statistical Yield Analysis. A copy
of the SBYA results is available upon request.
Lattice Semiconductor Corporation Doc. 25-107420 Rev . A
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24
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