TSM900N10 Taiwan Semiconductor N-Channel Power MOSFET 100V, 15A, 90mΩ FEATURES KEY PERFORMANCE PARAMETERS ● ● ● 100% avalanche tested Low gate charge for fast switching Pb-free plating ● RoHS compliant ● Halogen-free mold compound PARAMETER VALUE UNIT VDS 100 V RDS(on) (max) VGS = 10V 90 VGS = 4.5V 100 mΩ Qg APPLICATION ● Networking ● Load Switching ● LED Lighting Control ● AC-DC Secondary Rectification TO-251S (IPAK SL) 9.3 nC TO-252 (DPAK) Notes: Moisture sensitivity level: level 3. Per J-STD-020 ABSOLUTE MAXIMUM RATINGS (TA = 25°C unless otherwise noted) PARAMETER SYMBOL LIMIT UNIT Drain-Source Voltage VDS 100 V Gate-Source Voltage VGS ±20 V Continuous Drain Current Pulsed Drain Current TC = 25°C (Note 1) ID TC = 100°C (Note 2) Total Power Dissipation @ TC = 25°C 15 9.5 A IDM 60 A PDTOT 50 W Single Pulsed Avalanche Energy (Note 3) EAS 18 mJ Single Pulsed Avalanche Current (Note 3) IAS 6 A TJ, TSTG - 55 to +150 °C SYMBOL LIMIT UNIT Junction to Case Thermal Resistance RӨJC 2.5 °C/W Junction to Ambient Thermal Resistance RӨJA 62 °C/W Operating Junction and Storage Temperature Range THERMAL PERFORMANCE PARAMETER Notes: RӨJA is the sum of the junction-to-case and case-to-ambient thermal resistances. The case thermal reference is defined at the solder mounting surface of the drain pins. R ӨJA is guaranteed by design while RӨCA is determined by the user’s board design. RӨJA shown below for single device operation on FR-4 PCB in still air. Document Number: DS_P0000173 1 Version: A15 TSM900N10 Taiwan Semiconductor ELECTRICAL SPECIFICATIONS (TA = 25°C unless otherwise noted) PARAMETER Static CONDITIONS SYMBOL MIN TYP MAX UNIT (Note 4) Drain-Source Breakdown Voltage VGS = 0V, ID = 250µA BVDSS 100 -- -- V Gate Threshold Voltage VDS = VGS, ID = 250µA VGS(TH) 1.2 1.6 2.5 V Gate Body Leakage VGS = ±20V, VDS = 0V IGSS -- -- ±100 nA Zero Gate Voltage Drain Current VDS = 100V, VGS = 0V IDSS -- -- 1 µA -- 72 90 75 100 Drain-Source On-State Resistance Dynamic VGS = 10V, ID = 5A VGS = 4.5V, ID = 3A RDS(on) mΩ (Note 5) Total Gate Charge VDS = 48V, ID = 5A, Gate-Source Charge VGS = 10V Gate-Drain Charge Input Capacitance VDS = 50V, VGS = 0V, Output Capacitance Reverse Transfer Capacitance Gate Resistance Switching f = 1.0MHz F = 1MHz, open drain Qg -- 9.3 -- Qgs -- 2.1 -- Qgd -- 1.8 -- Ciss -- 1480 -- Coss -- 480 -- Crss -- 35 -- Rg -- 1.3 -- td(on) -- 2.9 -- tr -- 9.5 -- td(off) -- 18.4 -- tf -- 5.3 -- VSD -- -- 1 V IS -- -- 15 A ISM -- -- 60 A nC pF Ω (Note 6) Turn-On Delay Time VDD = 30V, Turn-On Rise Time RGEN = 3.3Ω, Turn-Off Delay Time ID = 1A, VGS = 10V, Turn-Off Fall Time Source-Drain Diode ns (Note 4) Forward On Voltage IS = 3.3A, VGS = 0V Continuous Drain-Source Diode Pulse Drain-Source Diode VG=VD=0V, Force Current Notes: 1. Current limited by package 2. Pulse width limited by the maximum junction temperature 3. L = 0.1mH, IAS = 6A, VDD = 50V, RG = 25Ω, Starting TJ = 25 C 4. Pulse test: PW ≤ 300µs, duty cycle ≤ 2% 5. For DESIGN AID ONLY, not subject to production testing. 6. Switching time is essentially independent of operating temperature. o Document Number: DS_P0000173 2 Version: A15 TSM900N10 Taiwan Semiconductor ORDERING INFORMATION (EXAMPLE) PART NO. TSM900N10CH X0G PACKAGE PACKING TO-251S (IPAK SL) 75pcs / Tube TSM900N10CP ROG TO-252 (DPAK) 2,500pcs / 13” Reel Note: 1. Compliant to RoHS Directive 2011/65/EU and in accordance to WEEE 2002/96/EC 2. Halogen-free according to IEC 61249-2-21 definition Document Number: DS_P0000173 3 Version: A15 TSM900N10 Taiwan Semiconductor CHARACTERISTICS CURVES (TC = 25°C unless otherwise noted) Gate Charge ID, Continuous Drain Current (A) VGS, Gate to Source Voltage (V) Continuous Drain Current vs. T C Qg, Gate Charge (nC) TC, Case Temperature (°C) Threshold Voltage vs. Junction Temperature Normalized On Resistance (m) Normalized Gate Threshold Voltage (V) On-Resistance vs. Junction Temperature TJ, Junction Temperature (°C) Normalized Thermal Transient Impedance Curve ID, Continuous Drain Current (A) Normalized Thermal Response (RθJC) Maximum Safe Operating Area TJ, Junction Temperature (°C) Square Wave Pulse Duration (s) VDS, Drain to Source Voltage (V) Document Number: DS_P0000173 4 Version: A15 TSM900N10 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) TO-251S (IPAK SL) MARKING DIAGRAM Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr ` S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000173 5 Version: A15 TSM900N10 Taiwan Semiconductor PACKAGE OUTLINE DIMENSIONS (Unit: Millimeters) TO-252 (DPAK) SUGGESTED PAD LAYOUT MARKING DIAGRAM Y = Year Code M = Month Code for Halogen Free Product O =Jan P =Feb Q =Mar R =Apr ` S =May T =Jun U =Jul V =Aug W =Sep X =Oct Y =Nov Z =Dec L = Lot Code (1~9, A~Z) Document Number: DS_P0000173 6 Version: A15 TSM900N10 Taiwan Semiconductor Notice Specifications of the products displayed herein are subject to change without notice. TSC or anyone on its behalf, assumes no responsibility or liability for any errors or inaccuracies. Information contained herein is intended to provide a product description only. No license, express or implied, to any intellectual property rights is granted by this document. Except as provided in TSC’s terms and conditions of sale for such products, TSC assumes no liability whatsoever, and disclaims any express or implied warranty, relating to sale and/or use of TSC products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any patent, copyright, or other intellectual property right. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications. Customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify TSC for any damages resulting from such improper use or sale. Document Number: DS_P0000173 7 Version: A15