RT7020 - Richtek

®
RT7020
0.3A/0.6A Half-Bridge Gate Driver
General Description
Features
The RT7020 is a high-voltage gate driver IC with dual
outputs. The IC, together with an external bootstrap
network, drives dual N-MOSFETs or IGBTs in a half-bridge
configuration with input voltage rail up to 600V.
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Floating Channel Designed for Bootstrap Operation
with Input Voltage up to 600V
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The IC is equipped with a “common-mode dV/dt noise
canceling technique” to provide high dV/dt immunity which
enables stable operation under high dV/dt noise
circumstances. Two Under-Voltage Lockout (UVLO)
functions continuously monitor the bias voltages on VCC
and BOOT-to-LX for preventing malfunction when the bias
voltages are lower than the specified threshold voltages.
A dead time control prevents shoot-through of the external
power MOSFETs. The logic level of the PWM signal input
pins are compatible with standard TTL logic level for ease
of interfacing with controlling devices.
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300mA/600mA Sourcing/Sinking Current
High dV/dt Immunity : ±50V/ns
VCC and VBOOT − LX Supply Range from 10V to 20V
Under-Voltage Lockout Functions for Both Channels
Matched Propagation Delays Between Both
Channels
TTL Compatible Logic Input
Internal Dead-Time Setting
High-Side Output In-Phase with HIN Input Signal
Low-Side Output Out of Phase with LIN Input Signal
RoHS Compliant and Halogen Free
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Ordering Information
RT7020
Package Type
S : SOP-8
N : DIP-8
Applications
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PDP Scan Driver
Fluorescent Lamp Ballast
SMPS
Motor Driver
Lead Plating System
G : Green (Halogen Free and Pb Free)
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Simplified Application Circuit
VCC
Up to 600V
RUGATE
UGATE
VCC
BOOT
C1
RT7020
LX
PWM
Signal
LIN
GND
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October 2013
To Load
HIN
RLGATE
LGATE
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RT7020
Marking Information
Pin Configurations
(TOP VIEW)
RT7020GS
RT7020GS : Product Number
RT7020
GSYMDNN
8
VCC
YMDNN : Date Code
2
7
UGATE
LIN
3
6
LX
GND
4
5
LGATE
RT7020GN
SOP-8
RT7020GN : Product Number
RichTek
RT7020
GNYMDNN
BOOT
HIN
YMDNN : Date Code
BOOT UGATE LX LGATE
8
7
6
5
2
3
4
VCC HIN
LIN GND
DIP-8
Functional Pin Description
Pin No.
Pin Name
Pin Function
SOP-8
DIP-8
1
1
VCC
Supply Voltage Input.
2
2
HIN
Logic Input for High-Side Gate Driver.
3
3
LIN
Logic Input for Low-Side Gate Driver.
4
4
GND
Logic Ground and Low-Side Driver Return.
5
5
LGATE
Low-Side Driver Output.
6
6
LX
Return for High-Side Gate Driver.
7
7
UGATE
High-Side Driver Output.
8
8
BOOT
Bootstrap Supply for High-Side Gate Driver.
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RT7020
Function Block Diagram
BOOT
BOOT-to-LX
UVLO1
Under-Voltage
Lockout
Driver
Pulse
Generator
Level
Shifter
Noise
Filter
R
S
UGATE
Q
LX
UGATE High/Low
VCC
VCC
HIN
VCC
UVLO2
Under-Voltage
Lockout
IIN+
Dead
Time
Control
VCC
IIN+
Driver
LGATE High/Low
LGATE
Delay
GND
LIN
Operation
The RT7020 is a high-voltage gate driver for driving highside and low-side MOSFETs in a half-bridge configuration.
The RT7020 uses ultra high voltage device and floating
well to allow UGATE to drive external MOSFET operating
up to 600V. When the HIN voltage is above the logic-high
threshold, the UGATE voltage goes to turn on the external
MOSFET. When the HIN voltage is below the logic-low
threshold, the MOSFET is turned off.
The operating behavior of the LGATE, controlled by the
LIN pin, is like the behavior of the UGATE.
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Under-Voltage Lockout (UVLO) Function
When the VCC or BOOT-to-LX voltage is lower than the
UVLO threshold, the UGATE and LGATE output will be
disabled.
Pulse Generator
The pulse generator is used to transmit the HIN input signal
to the UGATE driver.
Dead-Time Control
The dead-time control function is designed to prevent the
high-side and low-side MOSFETs form shoot-through.
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RT7020
Absolute Maximum Ratings
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(Note 1)
VCC Supply Voltage, VCC ---------------------------------------------------------------------------------LX to GND -----------------------------------------------------------------------------------------------------BOOT to LX, VBOOT−LX --------------------------------------------------------------------------------------UGATE to LX -------------------------------------------------------------------------------------------------LGATE to GND -----------------------------------------------------------------------------------------------HIN, LIN to GND ----------------------------------------------------------------------------------------------Allowable LX Voltage Slew Rate,dVLX/dt ---------------------------------------------------------------Power Dissipation, PD @ TA = 25°C
−0.3 to 25V
−0.3V to 625V
−0.3V to 25V
−0.3V to VBOOT−LX + 0.3V
−0.3V to VCC + 0.3V
−0.3V to VCC + 0.3V
−50V/ns to 50V/ns
SOP-8 ----------------------------------------------------------------------------------------------------------DIP-8 -----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
SOP-8, θJA ----------------------------------------------------------------------------------------------------DIP-8, θJA ------------------------------------------------------------------------------------------------------Junction Temperature ---------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------
0.53W
0.74W
Recommended Operating Conditions
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188°C/W
134.9°C/W
150°C
260°C
−65°C to 150°C
(Note 3)
VCC Supply Voltage, VCC ---------------------------------------------------------------------------------BOOT-to-LX, VBOOT−LX --------------------------------------------------------------------------------------LX to GND -----------------------------------------------------------------------------------------------------UGATE to LX -------------------------------------------------------------------------------------------------LGATE to GND -----------------------------------------------------------------------------------------------HIN, LIN to GND ---------------------------------------------------------------------------------------------Junction Temperature Range ------------------------------------------------------------------------------Ambient Temperature Range -------------------------------------------------------------------------------
10V to 20V
10V to 20V
0 to 600V
0 to VBOOT−LX
0 to VCC
0 to VCC
−40°C to 125°C
−40°C to 85°C
Electrical Characteristics
(VCC = VBOOT − LX = 15V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
VCC Under-Voltage Lockout
Threshold (On)
V THON_VCC
9
10.5
12
V
VBOOT − LX Under-Voltage
Lockout Threshold (On)
V THON_BOOT
9
10.5
12
V
VCC Under-Voltage Lockout
Threshold (Off)
V THOFF_VCC
8
9.5
11
V
VBOOT − LX Under-Voltage
Lockout Threshold (Off)
V THOFF_BOOT
8
9.5
11
V
VCC Under-Voltage Lockout
Hysteresis
V HYS_VCC
--
1
--
V
VBOOT − LX Under-Voltage
Lockout Hysteresis
V HYS_BOOT
--
1
--
V
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is a registered trademark of Richtek Technology Corporation.
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RT7020
Parameter
Symbol
Test Conditions
Typ
Max
Unit
--
--
50
μA
LX Leakage Current
ILK
VCC Quiescent Current
IQ_VCC
--
220
400
μA
BOOT-to-LX Quiescent
Current
IQ_BOOT−LX
--
100
200
μA
VCC Operating Current
IP_VCC
--
--
600
μA
BOOT-to-LX Operating
Current
IP_ BOOT−LX
--
--
600
μA
2.5
--
--
--
--
0.8
--
50
200
HIN, LIN
Input Voltage
UGATE, LGATE
Output Voltage
VBOOT = V LX = 600V
Min
Frequency = 20kHz,
UGATE = LGATE = Open
Logic-High VIH
Logic-Low
VIL
High-Lev el VOH
Low-Level
VOL
Sinking Current = 2mA,
V BOOT − VUGATE, V CC − VLGATE
Sinking Current = 2mA, VUGATE−LX,
V LGATE
V
mV
--
20
100
Logic-High IIN+
HIN = VCC, LIN = GND
--
2
10
Logic-Low
HIN = GND, LIN = VCC
−1
--
--
UGATE and LGATE Sourcing
IO+
Current
UGATE = LX, LGATE = GND, Current
pulse width < 10μs, Low duty
--
290
--
UGATE and LGATE Sinking
Current
UGATE = LX, LGATE = GND, Current
pulse width < 10μs, Low duty
--
600
--
Min
Typ
Max
Unit
--
680
820
ns
--
150
300
ns
HIN Input
Current
IIN−
IO−
μA
mA
Dynamic Electrical Characteristics (Note 4)
(VCC = VBOOT − LX = 15V, LX = GND, CL = 1000pF, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Turn-on Delay
t ON
Turn-off Delay
t OFF
Turn-on Rising Time
tR
--
70
170
ns
Turn-off Falling Time
tF
--
35
90
ns
Dead-Time
t Dead
--
520
650
ns
V LX = 0 or 600V
(Note 5)
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7.
Note 3. The device is not guaranteed to function outside its operating conditions.
Note 4. Please refer to the Timing Diagram and Dynamic Waveforms in the Application Information.
Note 5. Turn-off Delay for VLX = 600V is guaranteed by design.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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October 2013
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RT7020
Typical Application Circuit
VCC
Up to 600V
1
UGATE
VCC
RT7020
2 HIN
3 LIN
4 GND
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RUGATE
BOOT 8
C1
PWM
Signal
7
LX 6
LGATE 5
To Load
RLGATE
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RT7020
Typical Operating Characteristics
Turn-On Delay Time vs. Temperature
Turn-On Delay Time vs. VCC
800
Turn-On Delay Time (ns)1
Turn-On Delay Time (ns)1
800
700
LGATE
600
UGATE
500
700
600
LGATE
UGATE
500
TA = 25°C
400
400
-50
-25
0
25
50
75
100
125
10
12
14
18
20
Turn-Off Delay Time vs. VCC
Turn-Off Delay Time vs. Temperature
400
400
Turn-Off Delay Time (ns)
Turn-Off Delay Time (ns)
16
VCC (V)
Ambient Temperature (°C)
300
200
LGATE
100
UGATE
300
200
LGATE
100
UGATE
TA = 25°C
0
0
-50
-25
0
25
50
75
100
125
10
12
16
18
20
Turn-On Rising Time vs. VCC
Turn-On Rising Time vs. Temperature
160
Turn-On Rising Time (ns)1
160
Turn-On Rising Time (ns)1
14
VCC (V)
Ambient Temperature (°C)
120
UGATE
80
LGATE
40
120
UGATE
80
LGATE
40
TA = 25°C
0
0
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
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October 2013
125
10
12
14
16
18
20
VCC (V)
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RT7020
Turn-Off Falling Time vs. VCC
Turn-Off Falling Time vs. Temperature
50
Turn-Off Falling Time (ns)
Turn-Off Falling Time (ns)
50
40
30
LGATE
20
UGATE
10
40
30
LGATE
20
UGATE
10
TA = 25°C
0
0
-50
-25
0
25
50
75
100
10
125
12
14
Ambient Temperature (°C)
800
800
VLGATE Rising − VUGATE Falling
400
18
20
Dead-Time vs. VCC
1000
Dead-Time (ns)
Dead-Time (ns)
Dead-Time vs. Temperature
1000
600
16
VCC (V)
VUGATE Rising − VLGATE Falling
600
VLGATE Rising − VUGATE Falling
400
200
200
0
0
VUGATE Rising − VLGATE Falling
TA = 25°C
-50
-25
0
25
50
75
100
10
125
12
VCC Operating Current vs. Temperature
16
18
20
VCC Operating Current vs. VCC
600
VCC Operating Current (µA)
600
VCC Operating Current (µA)
14
VCC (V)
Ambient Temperature (°C)
500
400
300
200
100
500
400
300
200
100
TA = 25°C
0
0
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
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125
10
12
14
16
18
20
VCC (V)
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RT7020
VBOOT - LX Operating Current vs. VBOOT-LX
300
VBOOT - LX Operating Current (µA) 1
VBOOT - LX Operating Current (µA) 1
VBOOT - LX Operating Current vs. Temperature
240
180
120
60
300
240
180
120
60
TA = 25°C
0
0
-50
-25
0
25
50
75
100
125
10
12
14
Ambient Temperature (°C)
20
3.0
Logic-High Input Voltage (V)
LX Leakage Current (uA) 1
18
Logic-High Threshold Voltage vs. Temperature
LX Leakage Current vs. Temperature
15
12
9
6
3
2.5
HIN
2.0
LIN
1.5
1.0
0
-50
-25
0
25
50
75
100
-50
125
-25
Logic-High Threshold Voltage vs. VCC
25
50
75
100
125
Logic-Low Threshold Voltage vs. Temperature
3.0
Logic-Low Threshold Voltage (V)
2.0
2.5
HIN
2.0
LIN
1.5
TA = 25°C
1.0
1.8
1.6
HIN
1.4
LIN
1.2
1.0
10
12
14
16
18
VCC (V)
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Ambient Temperature (°C)
Ambient Temperature (°C)
Logic-High Threshold Voltage (V)1
16
VBOOT-LX (V)
October 2013
20
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
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RT7020
Logic-Low Threshold Voltage vs. VCC
High-Level Output Voltage vs. Temperature
100
High-Level Output Voltage (mV)1
Logic-Low Threshold Voltage (V)
2.0
1.8
1.6
HIN
1.4
LIN
1.2
TA = 25°C
1.0
80
VCC − VLGATE
60
VBOOT − VUGATE
40
20
0
10
12
14
16
18
20
-50
-25
VCC (V)
50
75
100
125
Low-Level Output Voltage vs. Temperature
25
100
Low-Level Output Voltage (mV)
High-Level Output Voltage (mV)1
25
Ambient Temperature (°C)
High-Level Output Voltage vs. VCC or VBOOT-LX
80
VCC − VLGATE
60
40
VBOOT − VUGATE
20
TA = 25°C
20
VLGATE
15
VUGATE-LX
10
5
0
0
10
12
14
16
18
-50
20
-25
VCC or VBOOT-LX (V)
0
25
50
75
100
125
Ambient Temperature (°C)
Output Sourcing Current vs. Temperature
Low-Level Output Voltage vs. VCC or VBOOT-LX
600
Output Sourcing Current (mA)1
25
Low-Level Output Voltage (mV)
0
20
VLGATE
15
VUGATE-LX
10
5
TA = 25°C
500
400
LGATE
300
UGATE
200
100
0
0
10
12
14
16
18
VCC or VBOOT-LX (V)
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10
20
-50
-25
0
25
50
75
100
125
Junction Temperature (°C)
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RT7020
Output Sourcing Current vs. VCC or VBOOT-LX
Output Sinking Current vs. Temperature
1000
Output Sink Current (mA)1
Output Sourcing Current (mA)1
600
500
400
LGATE
300
UGATE
200
100
800
UGATE
600
LGATE
400
200
TA = 25°C
0
0
10
12
14
16
18
-50
20
-25
VCC or VBOOT-LX (V)
25
50
75
100
125
VTHON_VCC / VTHOFF_VCC vs. Temperature
Output Sinking Current vs. VCC or VBOOT-LX
1000
15
800
UGATE
600
LGATE
VTHON_VCC / VTHOFF_VCC (V)
Output Sinking Current (mA)1
0
Junction Temperature (°C)
400
200
12
V THON_VCC
9
VTHOFF_VCC
6
3
TA = 25°C
0
0
10
12
14
16
18
20
-50
-25
VCC or VBOOT-LX (V)
VTHON_BOOT / VTHOFF_BOOT vs. Temperature
25
50
75
100
125
VHYS_VCC vs. Temperature
2.0
15
12
VTHON_BOOT
1.5
VHYS_VCC (V)
VTHON_BOOT / VTHOFF_BOOT (V)
0
Ambient Temperature (°C)
9
VTHOFF_BOOT
6
1.0
0.5
3
0.0
0
-50
-25
0
25
50
75
100
Ambient Temperature (°C)
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125
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
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RT7020
VHYS_BOOT vs. Temperature
2.0
VHYS_BOOT (V)
1.5
1.0
0.5
0.0
-50
-25
0
25
50
75
100
125
Ambient Temperature (°C)
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is a registered trademark of Richtek Technology Corporation.
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RT7020
Application Information
Timing Diagram and Dynamic Waveforms
90%
VUGATE
Figure 1 is the RT7020 input/output timing diagram, and
Figure 2 is a definition of dynamic characteristics. You
can know those definitions and the relationship between
input and output from these figures. For example : tON,
10%
tDead
tDead
90%
VLGATE
10%
tOFF, tR, tF...
Figure 3. Deadtime Definition
VHIN
Matched Propagation Delays between Both
Channels
VLIN
Because the IC internal level shifter circuit causes the
propagation delay of the high-side output signal, shown
in Figure 4. The RT7020 adds a propagation delay
matching circuit in the low-side logic circuit, so that highside and low-side output signals approximately
synchronization.
VUGATE
VLGATE
Figure 1. Input/Output Timing Diagram
BOOT
VHIN
50%
tON tR
BOOT-to-LX
UVLO1
Under-Voltage
Lockout
50%
Pulse
Generator
tOFF
Level
Shifter
Noise
Filter
R
S
Driver
UGATE
Q
LX
tF
90%
VUGATE
10%
UGATE High/Low
10%
IIN+
VLIN
50%
tON tR
50%
IIN+
90%
VLGATE
10%
Dead
Time
Control
VCC
tOFF
VCC
VCC
HIN
VCC
UVLO2
Under-Voltage
Lockout
LGATE High/Low
Driver
LGATE
Delay
GND
LIN
tF
10%
Figure 4. Propagation Delay Matching Circuit
Figure 2. Dynamic Electrical Characteristics Definition
Thermal Considerations
Deadtime, tDead
To avoid the simultaneous conduction of high-side and
low-side power switches cause shoot through, the
switching operation of the IC control circuit introduces a
deadtime function. In the deadtime period, even if the input
sends another power switch conduction signal, the control
circuit will remain closed drive state. Figure 3 illustrates
the definition of deadtime and the relationship between
the high-side and low-side gate signals.
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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October 2013
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
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RT7020
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications, the
maximum junction temperature is 125°C. The junction to
ambient thermal resistance, θJA, is layout dependent. For
SOP-8 package, the thermal resistance, θJA, is 188°C/W
on a standard JEDEC 51-7 four-layer thermal test board.For
DIP-8 package, the thermal resistance, θJA, is 134.9°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :
Layout Consideration
A proper PCB layout for power supply can reduce
unnecessary waveform noise and electromagnetic
interference problems to ensure proper system operation,
please refer to the following PCB layout considerations:
`
For the high voltage and high current loop layout of
power supply should be as thick and short. Avoid
excessive layout generated parasitic inductance and
resistors to cause significant noise.
`
In order to shorten the length of IC layout, you need to
consider the relative placement for IC and the power
switches. It is recommended that the power switches
placed in a symmetrical manner, and the IC close to
high-side and low-side elements.
`
In order to reduce the noise coupling, it is recommended
that the ground layout should not be placed under or
near the high voltage floating side.
`
The layout between high-side and low-side power
switches should be thick and straight, avoiding the
formation of long loops. Too long distance will increase
the loop area, and electromagnetic interference
suppression capabilities would be affected. However,
too short distance may cause overheating situation. It
is necessary to consider the most appropriate way.
`
Refer to typical application circuit, the VCC capacitor
(C1), BOOT to LX capacitor (CBOOT), and bootstrap diode
(DBOOT) need to be placed as close to the IC as possible
to minimize parasitic inductance and resistance. The
CBOOT selected range is from 0.1μF to 0.47μF, and the
VCC capacitor (C1) is greater than ten times CBOOT. It is
recommended to use fast or ultra fast reverse recovery
time bootstrap diode DBOOT.
`
In Figure 5, the LX pin voltage drop can be improved by
adding RLX (RLX = 1 to 10Ω), because the dv/dt is
affected by (RLX + RUGATE).
PD(MAX) = (125°C − 25°C) / (188°C/W) = 0.53W for
SOP-8 package
PD(MAX) = (125°C − 25°C) / (134.9°C/W) = 0.74W for
DIP-8 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. The derating curve in Figure 5 allows the
designer to see the effect of rising ambient temperature
on the maximum power dissipation.
Maximum Power Dissipation (W)1
1.0
Four-Layer PCB
0.9
DIP-8
0.8
0.7
0.6
SOP-8
0.5
0.4
0.3
0.2
0.1
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 5. Derating Curve of Maximum Power Dissipation
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
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is a registered trademark of Richtek Technology Corporation.
DS7020-00
October 2013
RT7020
VCC
+VDC+
DBOOT
BOOT
CBOOT
RUGATE
Q1
UGATE
RLX
LX
Figure 5. LX Pin Resister
`
If the gate current loop opens circuit for some factors,
at this time, the current flows through the gate loop via
the power MOSFET drain-to-gate parasitic capacitor. The
current will charge the gate-to-source parasitic capacitor
to result in power MOSFET wrong action. The power
switches can be damaged or burned out, the resisters
(about least 10kΩ) are connected between the gate and
source pin can prevent malfunction of the power
switches.
`
The selection of larger parasitic capacitor power switch
or gate resister may result in too long turn-off time
making the high-side and low-side power switches shoot
through. In order to prevent the situation, reverse parallel
with diodes (DUGATE & DLGATE) in the RUGATE and RLGATE
(shown in Figure 6), providing a fast discharge path for
the power switches in a short time to complete the
closing operation.
VCC
+VDC+
DBOOT
BOOT
CBOOT
DUGATE
RUGATE
Q1
UGATE
To
Load
LX
DLGATE
RLGATE
LGATE
Q2
Figure 6. Reverse Parallel with Diodes
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
DS7020-00
October 2013
is a registered trademark of Richtek Technology Corporation.
www.richtek.com
15
RT7020
Outline Dimension
H
A
M
J
B
F
C
I
D
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
4.801
5.004
0.189
0.197
B
3.810
3.988
0.150
0.157
C
1.346
1.753
0.053
0.069
D
0.330
0.508
0.013
0.020
F
1.194
1.346
0.047
0.053
H
0.170
0.254
0.007
0.010
I
0.050
0.254
0.002
0.010
J
5.791
6.200
0.228
0.244
M
0.400
1.270
0.016
0.050
8-Lead SOP Plastic Package
Copyright © 2013 Richtek Technology Corporation. All rights reserved.
www.richtek.com
16
is a registered trademark of Richtek Technology Corporation.
DS7020-00
October 2013
RT7020
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
3.700
4.320
0.146
0.170
A1
0.381
0.710
0.015
0.028
A2
3.200
3.600
0.126
0.142
b
0.360
0.560
0.014
0.022
b1
1.143
1.778
0.045
0.070
D
9.050
9.550
0.356
0.376
E
6.200
6.600
0.244
0.260
E1
7.620
8.255
0.300
0.325
e
L
2.540
3.000
0.100
3.600
0.118
0.142
8-Lead DIP Plastic Package
Richtek Technology Corporation
14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789
Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS7020-00
October 2013
www.richtek.com
17