RT9104 3W Stereo Class-D Audio Power Amplifier with DC Volume Control General Description Features The RT9104 is a stereo, high efficiency, filter free Class-D audio amplifier capable of delivering 3W per channel into 3Ω speakers. For application flexibility, the gain can be set by external DC volume control. Thermal protection as well as overcurrent protection functions are included in the stereo amplifier. The SOP-16 packaging without additional heat sink makes the RT9104 Class-D amplifier an ideal choice for monitor applications. The RT9104 is also well suited for battery powered applications because of its operating voltage (from 4.5V to 5.5V) and very low shutdown current. z z z z z z z z Applications z The RT9104 is available in WQFN-16L 3x3, SOP-16 and DIP-16 packages. Ordering Information RT9104 4.5V to 5.5V Input Supply Range Ω Speakers (THD+N = 10%) 3W Per Channel into 3Ω 300kHz High Internal Switching Frequency Efficiency Greater than 85% DC Volume Control from −70dB to 20dB Fade In at Enable and Power On Thin 16-Lead WQFN and SOP-16 and DIP-16 Packages RoHS Compliant and Halogen Free z z LCD Monitors Consumer Device Powered Speakers Pin Configurations (TOP VIEW) BYPASS INR INL VOLUME_IN Package Type QW : WQFN-16L 3x3 (W-Type) S : SOP-16 N : DIP-16 Lead Plating System G : Green (Halogen Free and Pb Free) Note : Richtek products are : RoHS compliant and compatible with the current require- 16 15 14 13 ROUT+ PVDD GND ROUT- ments of IPC/JEDEC J-STD-020. 1 12 2 11 GND 3 9 5 6 7 8 GND SHDN AVDD GND Suitable for use in SnPb or Pb-free soldering processes. 10 17 4 LOUT+ PVDD GND LOUT- WQFN-16L 3x3 INR BYPASS ROUT+ PVDD GND ROUTGND SHDN 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 INL VOLUME_IN LOUT+ PVDD GND LOUTGND AVDD SOP-16/DIP-16 DS9104-01 April 2011 www.richtek.com 1 RT9104 Marking Information RT9104GQW GU=YM DNN RT9104GS GU= : Product Code YMDNN : Date Code RT9104GS : Product Number YMDNN : Date Code RT9104 GSYMDNN RT9104GN RT9104GN : Product Number YMDNN : Date Code RichTek RT9104 GNYMDNN Typical Application Circuit RT9104 AVDD VDD CAVDD 0.1µF CPVDD1 10µF CPVDD2 0.1µF VOLUME_IN PVDD BYPASS CB 2.2µF CINR 0.22µF INR Audio Input CVOL 1µF In from DAC or Potentiometer (DC Volatge) SHDN CINL 0.22µF INL RL Ferrite Bead Ferrite Bead CROUT+ 1nF www.richtek.com 2 CROUT1nF Ferrite Bead ROUT+ LOUT+ ROUT- LOUT- RL Ferrite Bead GND CLOUT1nF CLOUT+ 1nF DS9104-01 April 2011 RT9104 Functional Pin Description Pin No. Pin Name Pin Function SOP-16/DIP-16 WQFN-16L 3x3 1 15 INR Right Channel Audio Signal Input. 2 16 BYPASS Common Mode Voltage Output. 3 1 ROUT+ Positive Right Channel BTL Output. 4, 13 5, 7, 10, 12 6 2, 11 PVDD 3, 10, 5, 8, GND 17 (Exposed Pad) 4 ROUT− 8 6 Power Supply. Ground. The exposed pad must be soldered to a large PCB and connected to GND for maximum power dissipation. Negative Right Channel BTL Output. Shutdown Pin, Enable when SHDN = ’1’, SHDN Disable when SHDN = ’0’ . Analog Reference Input Voltage. Connect to a regulator output voltage as better. 9 7 AVDD 11 9 LOUT− Negative Left Channel BTL Output. 14 12 LOUT+ Positive Left Channel BTL Output. 15 13 VOLUME_IN Volume Control Pin. DC in for controlling volume. 16 14 INL Left Channel Audio Signal Input. Function Block Diagram - INR + Bypass PWM Generator AVDD Output Power Stage PVDD ROUT+ ROUTPGND + Bypass VOLUME_IN DC Volume Control Circuit SHDN Over Temperature /Over Current Protection Depop Circuit BYPASS - INL Bypass PWM Generator Output Power Stage PVDD LOUT+ LOUTPGND - GND Bypass DS9104-01 April 2011 + + www.richtek.com 3 RT9104 Absolute Maximum Ratings z z z z z z z z (Note 1) Supply Voltage, AVDD, PVDD ---------------------------------------------------------------------------------Input Voltage, INL, INR ------------------------------------------------------------------------------------------Power Dissipation, PD @ TA = 25°C WQFN-16L 3x3 ----------------------------------------------------------------------------------------------------SOP-16 -------------------------------------------------------------------------------------------------------------DIP-16 ---------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-16L 3x3, θJA ----------------------------------------------------------------------------------------------WQFN-16L 3x3, θJC ----------------------------------------------------------------------------------------------SOP-16, θJA --------------------------------------------------------------------------------------------------------DIP-16, θJA ----------------------------------------------------------------------------------------------------------Junction Temperature --------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------Storage Temperature Range ------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Mode) --------------------------------------------------------------------------------------MM (Machine Mode) ---------------------------------------------------------------------------------------------- Recommended Operating Conditions z z z 0.3V to 6V 0.3V to (VDD + 0.3V) 1.471W 1.176W 1.333W 68°C/W 7.5°C/W 85°C/W 75°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Voltage Range, AVDD, PVDD --------------------------------------------------------------------------- 4.5V to 5.5V Junction Temperature Range ------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VDD = 5V, Gain = 6dB, RL = 8Ω, TA = 25°C, unless otherwise specified) Parameter Under Voltage Lockout Threshold VDD Under Voltage Lockout Hysteresis SHDN Input Threshold Voltage Symbol VUVLO Test Conditions VDD Rising Min Typ Max Unit -- 4 -- V -- 100 -- mV Logic-High VIH 2 -- -- Logic-Low VIL -- -- 0.4 V Quiescent Current IQ VDD = 5.5V, No Load , -- 3 -- mA Shutdown Current ISHDN VSHDN = 0V, VDD = 4.5 V to 5.5V -- -- 10 μA VSHDN = 0V -- >1 -- kΩ VDD = 4.5V to 5.5V -- 300 -- kHz 20 -- -- kΩ 130 150 170 °C Output Impedance in SHDN Switching Frequency Resistance from Shutdown to GND Thermal Shutdown fSW TSD To be continued www.richtek.com 4 DS9104-01 April 2011 RT9104 Parameter Output Power (Per Channel) Total Harmonic Distortion Plus Noise Symbol PO THD+N Crosstalk Signal-to-Noise Ratio Start-Up Time from Shutdown Efficiency SNR Test Conditions Min Typ Max THD+N = 10%, f = 1kHz, RL = 3Ω -- 3 -- THD+N = 1%, f = 1kHz, RL = 3Ω -- 2.35 -- THD+N = 10%, f = 1kHz, RL = 4Ω -- 2.7 -- THD+N = 1%, f = 1kHz, RL = 4Ω -- 2.3 -- THD+N = 10%, f = 1kHz, RL = 8Ω -- 1.6 -- THD+N = 1%, f = 1kHz, RL = 8Ω -- 1.25 -- PO = 1W, RL = 8Ω, f = 1kHz -- 0.2 -- % f = 1kHz, VDD = 4.5V to 5.5V, PO = 2W, RL = 4Ω -- −85 -- dB PO = 1W, RL = 8Ω, A Weighting -- 90 -- dB -- 300 -- ms -- 85 -- % Load = (8Ω + 33μH) Unit W Note 1. Stresses listed as the above “ Absolute Maximum Ratings” may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a high effective thermal conductivity four-layer test board of JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the package Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. DS9104-01 April 2011 www.richtek.com 5 RT9104 Typical Operating Characteristics Efficiency vs. Output Power 100 90 90 80 80 70 70 Efficiency (%) Efficiency (%) Efficiency vs. Output Power 100 60 50 40 30 60 50 40 30 20 20 VDD = 5V, RL = 4Ω, 33μH, f = 1kHz, Gain = 20dB) 10 VDD = 5V, RL = 8Ω, 33μH, f = 1kHz, Gain = 20dB) 10 0 0 0 0.5 1 1.5 2 2.5 3 0 3.5 0.4 10 10 5 5 2 2 1 Right Channel Left Channel 0.2 0.05 0.05 0.01 50m 100m 200m 500m 1 2 Left Channel 0.02 VDD = 5V, RL = 4Ω, f = 1kHz, Gain = 20dB 10m 20m Right Channel 0.5 0.1 0.01 5 VDD = 5V, RL = 8Ω, f = 1kHz, Gain = 20dB 10m 20m 500m 1 2 5 THD+N vs. Frequency 20 10 10 5 5 2 2 THD+N (%) THD+N (%) THD+N vs. Frequency 20 1 0.5 Left Channel 0.2 Right Channel 0.05 1 0.5 0.2 Left Channel Right Channel 0.1 0.05 0.02 0.01 50m 100m 200m Output Power (W) Output Power (W) 0.1 2 1 0.1 0.02 1.6 THD+N vs. Output Power 20 THD+N (%) THD+N (%) THD+N vs. Output Power 20 0.2 1.2 Output Power (W) Output Power (W) 0.5 0.8 VDD = 5V, RL = 4Ω, PO = 1W, Gain = 20dB 20 50 100 200 500 1k 2k Frequency (Hz) www.richtek.com 6 5k 10k 20k 0.02 0.01 VDD = 5V, RL = 8Ω, PO = 1W, Gain = 20dB 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) DS9104-01 April 2011 RT9104 THD+N vs. Frequency 20 10 10 5 5 2 2 THD+N (%) THD+N (%) THD+N vs. Frequency 20 1 0.5 Left Channel 0.2 0.1 Right Channel 0.2 Left Channel Right Channel 0.05 0.02 0.02 VDD = 5V, RL = 4Ω, PO = 1W, Gain = 6dB 20 50 100 200 500 1k 2k 5k 0.01 10k 20k Frequency (Hz) Crosstalk vs. Frequency Noise Floor (dB) -60 -70 R to L -90 L to R -100 -110 VDD = 5V, RL = 8Ω, PO = 1W, Gain = 6dB -120 20 50 100 200 500 1k 2k Frequency (Hz) DS9104-01 April 2011 20 50 100 200 500 1k 2k 5k 10k 20k Noise Floor vs. Frequency -50 -80 VDD = 5V, RL = 8Ω, PO = 0.5W, Gain = 6dB Frequency (Hz) -40 Crosstalk (dB) 0.5 0.1 0.05 0.01 1 5k 10k 20k +20 +10 +0 -10 -20 -30 -40 -50 -60 -70 Right Channel -80 -90 -100 -110 Left Channel -120 -130 RL = 4Ω, Gain = 20dB -140 20 50 100 200 500 1k 2k 5k 10k 20k Frequency (Hz) www.richtek.com 7 RT9104 Application information The RT9104 is a single-ended input and high efficiency Class-D stereo audio amplifier featuring low resistance internal power MOSFETs and over 85% power efficiency. It requires only a few external components with small footprints. The RT9104 also supports DC volume control from −70dB to 20dB. Therefore, it is very suitable for portable devices and LCD monitor applications. With a filter-less modulation feature, the RT9104 can limit the number of external components to a minimum. DC Volume control The voltage gain of RT9104 can be set by the external DC voltage through the “VOLUME_IN” pin. There are a total of 32 discrete gain steps of the amplifier with a range from −70dB to 20dB for BTL operation. A pictorial representation of the typical volume control can be found in Figure 1. Table 1. VOLUME_IN Voltage for Gain Control Gain (dB) 20 19.5 19 18.5 18 17.5 17 16.5 16 15.5 15 14 13 12 11 10 VOLUME_IN (V) 3.4 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 Gain (dB) 9 8 7 6 5 4 3 2 1 0 -2 -4 -7 -19 -37 -70 VOLUME_IN (V) 1.8 1.7 1.6 1.5 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 Gain Table 30 Fade In For design flexibility, a fade mode is provided to slowly ramp up the amplifier gain when coming out of shutdown mode. This mode provides a smooth transition between the active and shutdown states and virtually eliminates any pops or clicks on the outputs. Gain (dB) 10 -10 -30 Decoupling Capacitor -50 -70 0.3 0.7 1.1 1.5 1.9 2.3 2.7 3.1 VOLUME_IN (V) Figure 1. Typical DC Voltage Control Operation www.richtek.com 8 3.5 The RT9104 is a high performance Class-D audio amplifier that requires adequate power supply decoupling to ensure high efficiency and low total harmonic distortion (THD). To filter out higher frequency transients, spikes, or digital hash on the line, a low equivalent-series-resistance (ESR) ceramic capacitor (typically 10μF), placed as close as possible to the PVDD pins will achieve the best performance. Placing this decoupling capacitor close to the RT9104 is very important, since any resistance or inductance in the trace between the device and the capacitor can cause a loss in efficiency. For filtering out lower frequency noise signals, a 10μF or greater capacitor can be placed near the audio power amplifier. DS9104-01 April 2011 RT9104 Short Circuit Protection PD(MAX) = (TJ(MAX) − TA) / θJA The RT9104 has short circuit protection circuitry on the outputs which prevents damage to the device during unexpected applications. When a short circuit is detected, the outputs are disabled immediately .However, once the short is removed, the device will re-activate again. where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. The RT9104 incorporates circuitry designed to detect low supply voltage level. When the supply voltage falls to 4V or below, the RT9104 goes into a state of shutdown and the current consumption drops from milliamperes to microamperes. The device will resume normal function again once VDD > 4.2V. Thermal Protection Thermal protection on the RT9104 automatically disables the outputs when the junction temperature exceeds 150°C in order to prevent damage to the device. There is a ±20 degree tolerance on this trip point from device to device. Once the temperature cools below 130°C, the device will auto-resume normal operations. How to Reduce EMI Most applications require a ferrite bead filter as shown in Figure 2. The ferrite filter reduces EMI of around 1MHz and higher. When selecting a ferrite bead, choose one with high impedance at high frequencies and low impedance at low frequencies. Ferrite Bead OUT+ OUT- Ferrite Bead 1nF 1nF Figure 2. Typical Ferrite Chip Bead Filter Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : DS9104-01 April 2011 thermal resistance, θ JA , is layout dependent. For WQFN-16L 3x3 packages, the thermal resistance, θJA, is 68°C/W on a standard JEDEC 51-7 four-layer thermal test board. For SOP-16 packages, the thermal resistance, θJA, is 85° C/W on a standard JEDEC 51-7 four-layer thermal test board. For DIP-16 packages, the thermal resistance, θJA, is 75°C/W on a standard JEDEC 51-7 four-layer thermal test board.The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (68°C/W) = 1.471W for WQFN-16L 3x3 package PD(MAX) = (125°C− 25°C) / (85°C/W) = 1.176W for SOP-16 package PD(MAX) = (125°C − 25°C) / (75°C/W) = 1.333W for DIP-16 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT9104 packages, the derating curves in Figure 3 allow the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 Low Supply Voltage Detection For recommended operating condition specifications of the RT9104, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0.0 Four-Layer PCB WQFN-16L 3x3 SOP-16 DIP-16 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curves for RT9104 Package www.richtek.com 9 RT9104 Layout Considerations For best performance of the RT9104, the below PCB Layout guidelines must be strictly followed. Place the decoupling capacitors as close as possible to the PVDD, AVDD and GND pins. Keep the differential output traces as wide and short as possible. The traces of (INR & INL) and (LOUT+ & LOUT−, ROUT+ & ROUT−) should be kept equal width and length respectively. Connect power sections directly to the ground plane for maximum thermal dissipation and noise protection. IN_L IN_R INR BYPASS Ferrite Bead ROUT+ PVDD CROUT+ CPVDD1 GND CROUTROUTFerrite Bead GND The decoupling capacitor SHDN must be placed as close to the IC as possible CB RL CINL CINR GND 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VDD GND CVOL INL VOLUME_IN Ferrite Bead LOUT+ CLOUT+ PVDD CPVDD2 RL GND CLOUTLOUTFerrite Bead GND AVDD The decoupling capacitor CAVDD must be placed as close to the IC as possible GND Figure 4. PCB Layout Guide www.richtek.com 10 DS9104-01 April 2011 RT9104 Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 16L QFN 3x3 Package DS9104-01 April 2011 www.richtek.com 11 RT9104 H A M B J F C I D Symbol Dimensions In Millimeters Dimensions In Inches Min Max Min Max A 9.804 10.008 0.386 0.394 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.178 0.254 0.007 0.010 I 0.102 0.254 0.004 0.010 J 5.791 6.198 0.228 0.244 M 0.406 1.270 0.016 0.050 16–Lead SOP Plastic Package www.richtek.com 12 DS9104-01 April 2011 RT9104 Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 3.700 4.320 0.146 0.170 A1 0.381 0.710 0.015 0.028 A2 3.200 3.600 0.126 0.142 b 0.360 0.560 0.014 0.022 b1 1.143 1.778 0.045 0.070 D 18.800 19.300 0.740 0.760 E 6.200 6.600 0.244 0.260 E1 7.620 8.255 0.300 0.325 e L 2.540 3.000 0.100 3.600 0.118 0.142 16-Lead DIP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9104-01 April 2011 www.richtek.com 13