RT9258 Two Phases Synchronous Buck PWM Controller General Description Features The RT9258 is a two phases synchronous Buck PWM controller with integrated drivers which is optimized for high-performance graphic microprocessor and computer applications. The IC integrates a voltage mode PWM controller, two 5V MOSFET drivers with internal bootstrap diodes, as well as output current monitoring and protection functions into a WQFN-24L 4x4 package. z Two-Phase Power Conversion with Single 12V Power Supply z Embedded 5V Upper Gate Driver and 12V Lower Gate Driver Internal Regulated 5V Output Precise Core Voltage Regulation Selectable Internal / External Reference Differential Inductor DCR Current Sense External Programmable Voltage Droop Control Enable Control for External Shutdown Adjustable Operating Frequency Adjustable Soft Start Power Good and Output Current Indication Adjustable Over Current Protection Over Voltage Protection Under Voltage Protection Over Temperature Protection RoHS Compliant and Halogen Free z z z z z z z z z z z Pin Configurations (TOP VIEW) FB z z SS z Middle to High End GPU Core Power High End Desktop PC Memory Core Power Low Voltage, High Current DC / DC Converter Voltage Regulator Modules REFIN/EN z z REFOUT/PGOOD Applications BOOT2 include output current indication, adjustable operating frequency, adjustable soft-start, power good, external compensation, and enable/shutdown functions. z UGATE2 The inductor currents are sensed by lossless DCR current sensing technique for current balance and over current protection. The RT9258 also features a reference tracking mode operation in which the feedback voltage is regulated and tracks external input reference voltage. Other features z 24 23 22 21 20 19 Ordering Information RT9258 Package Type QW : WQFN-24L 4x4 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) PHASE2 1 18 COMP Note : LGATE2 2 17 RT Richtek products are : DROOP 3 16 IOUT/IMAX VCC 4 15 CSP2 ments of IPC/JEDEC J-STD-020. LGATE1 5 14 CSN2 Suitable for use in SnPb or Pb-free soldering processes. PHASE1 6 13 CSN1 PGND DS9258-01 April 2011 9 10 11 12 CSP1 For marking information, contact our sales representative directly or through a Richtek distributor located in your area. 8 EN2B Marking Information UGATE1 7 AGND 25 5VCC ` RoHS compliant and compatible with the current require- BOOT1 ` WQFN-24L 4x4 www.richtek.com 1 RT9258 Typical Application Circuit VCC 12V EXT_12V + EXT_12V EXT_12V_DETB DET Circuits R1 11 R2 R3 C1 Internal Reference mode 5VCC C2 R4 C4 18 COMP C5 R7 R16 Optional C18 LGATE2 CSN1 CSP2 R8 3 DROOP Q1 C8 EXT_12V /VCC12V CSP1 VOUT L1 6 5 Q2 23 R15 C10 C12 C11 C13 C9 24 Q3 L2 PHASE2 1 CSN2 19 FB 7 + 16 IOUT/ IMAX R5 R6 BOOT1 22 REFOUT/ PGOOD UGATE1 4 VCC PHASE1 9 5VCC LGATE1 21 REFIN/ EN 10 AGND BOOT2 20 SS 17 UGATE2 RT C7 R14 + C3 External Reference Voltage (0.45 to 2.5V) EN2B 8 + Optional C6 RT9258 2 C14 Q4 14 R10 13 R11 15 R12 12 R13 C16 C15 PHASE2 PHASE1 C17 R9 Figure 1. Typical Application Circuit with 12V Input www.richtek.com 2 DS9258-01 April 2011 RT9258 Function Block Diagram 5VCC EN2B 5VCC VCC BOOT1 Gate Control Logic & Shoot Through Prevention 5VCC Regulator & Power On Reset Oscillator & Ramp Generator RT REFIN/EN SS AGND REFOUT/ PGOOD REF Select Pulse Width Modulator & Central Control Logic 0.6V REF Soft Start LGATE1 PGND BOOT2 Gate Control Logic & Shoot Through Prevention UGATE2 PHASE2 VCC LGATE2 PGND OCP Error Amplifier + Current SENSE COMP + GM1 + GM2 - - FB PHASE1 VCC 5VCC REF Buffer 72.5% 50% 115% UV/OV Protection & PGOOD UGATE1 IOUT/IMAX CSP1 CSN1 CSP2 CSN2 DROOP Power up scheme to support dual power rails application This feature is to support the following case in the application where one phase is powered by PCIEBUS_12V and the other phase is powered by EXT_12V. `When the system is powered without EXT_12V Cable, RT9258 will work with one phase and be able to boot system into Dos Warning screen. `The Warning message tells user to power off the system first, plug in the EXT_12V Cable, and then reboot the system again. `After system re-boot, RT9258 could work with two phases. Below is the power up sequence for dual VIN (PCIEBUS_12V & EXT_12V) application. This application is classified into two cases : <1> The external connector is not plugged while power on The EXT_12V_DETB is pulled up to High. Soft-start will be released to ramp up after POR. After T1, RT9258 latches EN2B signal and determines to operate in single phase. The time interval T1 is used to wait EN2B ready. Once single phase is confirmed, the external 12V power connector plugged or not will not affect the status. <2> The external connector is plugged while power on The EXT_12V_DETB is grounded by external cable detection circuits. RT9258 latches EN2B at T1 and determines to operate in two phases. If the connector is removed later, RT9258 will turn off phase 2 and enter single phase operation mode. Further plugged in/out will not affect the status anymore. DS9258-01 April 2011 www.richtek.com 3 RT9258 ~us First PWM Pulse VIN Detection Latch Signal T1 Soft-Start EN2B/EXT_12V_DETb One/Two Phase Operation Two Phase One Phase Figure 2. External Connector is not Plugged ~us First PWM Pulse VIN Detection Latch Signal T1 Soft-Start EN2B/EXT_12V_DETb One/Two Phase Operation Two Phase One Phase Figure 3. External Connector is Plugged www.richtek.com 4 DS9258-01 April 2011 RT9258 Functional Pin Description PHASE2 (Pin 1), PHASE1 (Pin 6) CSN1 (Pin 13), CSN2 (Pin 14) These pins are return nodes of the high-side driver. Connect these pins to high-side MOSFET sources together with the low-side MOSFET drain and the inductors. These pins are negative input of current sensing transconductance amplifiers 1 and 2. IOUT/IMAX (Pin 16) Lower Gate Drivers. Theses pins provide the gate drive for the converter's low-side MOSFET. Connect these pins to the low-side MOSFET gate. Output Current Indication. This pin sends a current out (IX) referred to the sum of two sensed inductor currents sense value. Connect this pin through a resistor to ground. (IOUT = 4 x IX). This pin also sets maximum current limit threshold. DROOP (Pin 3) RT (Pin 17) Set the load line for droop control. Connect this pin with a resistor to ground. Frequency Timing Resistor. Connect a resistor from RT to AGND to set the clock frequency. VCC (Pin 4) COMP (Pin 18) Provide a 12V supply voltage for the IC. Connect a 10Ω/1uF low pass filter to sustain high PSRR. Compensation Pin. This pin is the output of the error amplifier. LGATE2 (Pin 2), LGATE1 (Pin 5) FB (Pin 19) UGATE1 (Pin 7), UGATE2 (Pin 24) Upper Gate Drivers. Theses pins provide the gate drive for the converter's high-side MOSFET. Connect these pins to the high-side MOSFET gate. Feedback Pin. This pin is connected to the PWM converter output's voltage or a resistor divider. This pin also connects to the inverting input of error amplifier and the PGOOD/ UV/OV detection circuits. BOOT1 (Pin 8), BOOT2 (Pin 23) SS (Pin 20) Bootstrap Power Pins. Theses pins power the high-side MOSFET drivers. Soft-Start Pin. Connect a capacitor from this pin to ground to set the soft-start interval. 5VCC (Pin 9) REFIN/EN (Pin 21) Internal Regulator Power Pin. The regulated voltage provides power supply for all low-voltage circuits. Bypass at least 1uF ceramic capacitor to sustain high PSRR. External Reference Input. AGND (Pin 10) Signal ground for the IC. All voltage levels are measured with respect to this pin. `If pulled up to 5VCC, internal reference is used (0.6V) `If driven by external voltage ranged from 0.45V to 2.5V, external reference is used `If pulled below 0.4V, device is disabled. REFOUT/PGOOD (Pin 22) EN2B (Pin 11) EXT_12V Detection Pin. RT9258 latches high/low status of this pin in soft start period. If the result is low, RT9258 will enter two phase operation. If it's high, RT9258 turns off phase2 and operate in single phase only. Reference Out and Power GOOD. This pin drives 1.15V out once FB exceeds 75% of the reference voltage after soft- start ends. This pin keeps at this voltage regardless of internal or external reference is used. PGND [Exposed Pad (25)] CSP1 (Pin 12), CSP2 (Pin 15) These pins are positive input of current sensing transconductance amplifiers 1 and 2. DS9258-01 April 2011 Power ground pin. Tie the synchronous PWM converter's low-side MOSFET source to this pin. www.richtek.com 5 RT9258 Absolute Maximum Ratings (Note 1) Supply Voltage, VCC ----------------------------------------------------------------------------------PHASE to GND DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z BOOT to PHASE --------------------------------------------------------------------------------------z BOOT to GND DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z UGATE DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z LGATE DC ---------------------------------------------------------------------------------------------------------< 200ns --------------------------------------------------------------------------------------------------z Other Input, Output or I/O Voltage -----------------------------------------------------------------z Power Dissipation, PD @ TA = 25°C WQFN−24L 4x4 ----------------------------------------------------------------------------------------z Package Thermal Resistance (Note 2) WQFN−24L 4x4, θJA ----------------------------------------------------------------------------------z Lead Temperature (Soldering, 10 sec.) -----------------------------------------------------------z Junction Temperature ---------------------------------------------------------------------------------z Storage Temperature Range -------------------------------------------------------------------------z ESD Susceptibility (Note 3) HBM (Human Body Mode) ---------------------------------------------------------------------------MM (Machine Mode) ----------------------------------------------------------------------------------z −0.3V to 15V z Recommended Operating Conditions z z z −2V to 15V −5V to 22V −0.3V to 7V −0.3V to VCC + 7V −0.3V to 30V VPHASE −0.3V to VBOOT + 0.3V VPHASE −2V to VBOOT + 0.3V −0.3V to VCC + 0.3V −2V to VCC + 0.3V −0.3V to 7V 1.923W 52°C/W 260°C 150°C −40°C to 150°C 2kV 200V (Note 4) Supply Voltage ------------------------------------------------------------------------------------------ +12V ±10% Junction Temperature Range ------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range ------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, PGND = 0V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions Min Typ Max Unit 10.8 12 13.2 V -- 5 -- mA VCC Supply Input VCC Supply Voltage VCC VCC Supply Current ICC REFIN/EN = 0V (static) 5VCC Supply Voltage V5VCC VCC = 12V 4.8 5.15 5.5 V 5VCC Output Sourcing I5VCC VCC = 12V 20 -- -- mA 5VCC Supply Output To be continued www.richtek.com 6 DS9258-01 April 2011 RT9258 Parameter Symbol Test Conditions Min Typ Max Unit 6.7 7.5 8.3 V -1 0.45 1.15 -1.3 V V 0.35 0.4 0.45 V -- 50 -- mV 0.45 -- 2.5 V 0.591 0.6 0.609 V −1.5 -- +1.5 % −6 -- +6 mV −1 -- +1 % 1.127 1.15 1.173 V −2 -- +2 % 3 5 -- mA Power-On Reset VCC Rising Threshold VVCCTH VCC Rising VCC Hysteresis EN2B High Threshold VVCCHY VEN2BTH EN2B Rising Enable Rising Threshold VENTH REFIN/EN Rising Enable Hysteresis VENHYS REFIN/EN REFIN Tracking Range Reference Voltage Accuracy (use Internal Reference) Reference Voltage Accuracy VREF REFIN Pull-High to 5VCC FB Coupled to COMP Reference Voltage Accuracy (use External Reference) VREFIN = 0.45V to 0.6V Accuracy VREFIN = 0.6V to 2.5V REFOUT / PGOOD REFOUT/PGOOD Voltage Accuracy REFOUT Output Sourcing Error Amplifier VREFOUT VFB > Power Good Threshold IREFOUT DC Gain ADC No load -- 70 -- dB Gain-Bandwidth GBW CLOAD = 10pF -- 8 -- MHz Slew Rate SR CLOAD = 10pF 5 -- -- V/us Transconductance GM -- 2400 -- uA/V Current Sense Amplifier IGM(MAX) VCSP = 1V Sink Current from CSN 100 -- -- uA Running Frequency fOSC RRT = 20kΩ 450 500 550 kHz Max Duty Cycle D 70 75 80 % Ramp Amplitude ΔV RAMP -- 2.6 -- V Soft Start Soft Start Current ISS 14 20 30 uA Max Current Oscillator Protection Over Current Threshold VOCP Sweep IOUT/IMAX Voltage 2.07 2.3 2.53 V Over-Voltage Threshold VOVP Sweep FB Voltage 115 125 135 % Under-Voltage Threshold VUVP Sweep FB Voltage 45 55 63 % Over Temperature Threshold TOTP -- 160 -- °C 65 72.5 80 % Power GOOD Active Threshold VFB Rising To be continued DS9258-01 April 2011 www.richtek.com 7 RT9258 Parameter Symbol Test Conditions Min Typ Max Unit -- 1.5 3 Ω Gate Driver BOOT − PHASE = 5V Upper Drive Source RUSOURCE Upper Drive Sink RUSINK BOOT − PHASE = 5V 250mA Sink Current -- 1.5 4 Ω Lower Drive Source ILSOURCE VCC = 12V VLGATE = 6V 1 -- -- A Lower Drive Sink RLSINK VCC = 12V 250mA Sink Current -- 0.9 2 Ω 250mA Source Current Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in the natural convection at T A = 25°C on a low effective thermal conductivity test board of JEDEC 51-3 thermal measurement standard. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. www.richtek.com 8 DS9258-01 April 2011 RT9258 Typical Operating Characteristics Switching Frequency vs. Temperature Start Up in Short Circuit 430 Switching Frequency (kHz)1 VIN = 12V 420 IOUT/IMAX (2V/Div) VOUT (1V/Div) 410 400 390 380 ILOAD (50A/Div) 370 360 VIN = 12V, VOUT = 1.2V, No Load, RRT = 26.1k PHASE2 (10V/Div) 350 -40 -20 0 20 40 60 80 100 120 140 Time (250us/Div) Temperature (°C) Over Current Protection Power On from REFIN VIN = 12V, VOUT = 1.2V IOUT/IMAX (2V/Div) SS (1V/Div) VOUT (1V/Div) VOUT (1V/Div) ILOAD (50A/Div) REFIN (200mV/Div) PHASE2 (10V/Div) PGOOD (1V/Div) VIN = 12V, VOUT = 1.2V, IOUT = 55A Time (250us/Div) Time (2ms/Div) Power Off from REFIN Power On from VCC SS (1V/Div) SS (1V/Div) VOUT (1V/Div) VOUT (1V/Div) REFIN (500mV/Div) VCC (5V/Div) PGOOD (1V/Div) VIN = 12V, VOUT = 1.2V, IOUT = 55A Time (1ms/Div) DS9258-01 April 2011 PGOOD (1V/Div) VIN = 12V, VOUT = 1.2V, IOUT = 55A Time (2ms/Div) www.richtek.com 9 RT9258 Single-phase Operation Power Off from VCC SS (1V/Div) UGATE1 (20V/Div) VOUT (1V/Div) EN2B (2V/Div) VCC (5V/Div) VOUT (1V/Div) PGOOD (1V/Div) UGATE2 (20V/Div) VIN = 12V, VOUT = 1.2V, IOUT = 55A VIN = 12V, VOUT = 1.2V, No Load Time (100us/Div) Time (50ms/Div) Inductor Current vs. Output Current Two-phase to Single-phase 30 25 Inductor Current (A) UGATE1 (20V/Div) EN2B (2V/Div) VOUT (1V/Div) 20 IL1 15 IL2 10 5 UGATE2 (20V/Div) VIN = 12V, VOUT = 1.2V, No Load VIN = 12V, VOUT = 1.2V, FSW = 400kHz 0 0 Time (50ms/Div) 5 10 15 20 25 30 35 40 45 50 55 Output Current (A) Efficiency vs. Output Current 90 FSW = 300kHz 85 FSW = 400kHz Efficiency (%) 80 75 70 65 60 55 VIN = 12V, VOUT = 1.2V 50 0 5 10 15 20 25 30 35 40 45 50 55 Output Current (A) www.richtek.com 10 DS9258-01 April 2011 RT9258 Application Information The RT9258 is a dual-phase voltage-mode synchronous buck controller with embedded MOSFET drivers and protection functions for low-voltage high-current applications. The bootstrap diode is integrated into the IC to reduce the external component count. In addition, the number of operating phase (two-phase/single-phase) is selectable to provide user with more flexibility in circuit design. The inductor current is sensed by innovative DCR current sensing technique for current balance and over current protection. Power On Reset The RT9258 initiates its soft start cycle only after the IC power supply, VCC, and the internal regulated 5VCC are ready. The internally regulated 5VCC is used for all of the internal logic control circuit and the embedded high-side MOSFET driver. The bootstrap diode for the high-side MOSFET driver is integrated into the IC to reduce the external component count. In addition, VCC is used for the low-side MOSFET driver to reduce the RDS(ON) of the low-side MOSFET for enhanced efficiency consideration. The power on reset (POR) circuitry monitors the supply voltage to ensure that the supply voltage is high enough for controller's normal operation. Once VCC and 5VCC exceed the POR rising threshold, the RT9258 releases the reset state, and works according to the settings. Additionally, once any one of these two voltages is lower than its POR falling threshold value, the chip turns off. The hysteresis between the rising and falling thresholds ensures that once the chip is enabled, it will not be inadvertently turned off unless the bias voltage drops substantially. VVCCTH ˜ 7.5V VCC SS 72.5% of VOUT VOUT PGOOD Figure 1. Power on Sequence During the soft start, the voltage on SS pin gradually increases, and the output voltage of the error amplifier is clamped to prevent the inrush current from the input capacitors. Once the output voltage exceeds the power good threshold level (72.5% of output voltage), REFOUT/ PGOOD pin will drive and maintain an reference voltage 1.15V unless VCC falls below POR threshold or Under Voltage occurs. Internal/External Reference The RT9258 supports the selectable internal/external reference voltage to provide more flexibility in practical applications. The selection of the internal/external reference is described in detail as follows. a. Using Internal Reference The internal reference voltage of the RT9258 is set at 0.6V. When using the internal reference, REFIN/EN pin should be connected to 5VCC. REFIN/EN pin is also used for the enable function, the RT9258 will not be enabled at start up if the voltage at the REFIN/EN pin is lower than VENTH. b. Using External Reference Soft Start and Power Good Once the POR state is released, the soft start cycle begins. A 20uA current source charges the capacitor, CSS, which is connected between SS pin and GND to set the soft start time. Figure 1 shows the power on sequence. DS9258-01 April 2011 To use the external reference, the applied voltage on REFIN/EN pin should be within the tracking range (typically between 0.45V and 2.5V). This externally input voltage is used as the reference voltage for the error amplifier. Therefore, the RT9258 operates in the tracking mode because the feedback voltage continuously tracks the external reference voltage. www.richtek.com 11 RT9258 Operating Frequency Setting The converter switching frequency is programmed by simply connecting the resistor RRT between RT pin and GND. Make sure the RRT is firmly connected between RT pin and GND with a short trace length. If the RRT is removed, there will not be any free running frequency. Figure 2 illustrates the switching frequency versus RRT. Switching Frequency vs. RRT 1100 As shown in Figure 3, the differential GM amplifier converts the voltage signal to a current signal IX for current balance and output voltage droop control. The following equations provide the calculation to determine the parameter values of the current sensing network and RCSN. If 1000 Switching Frequency (kHz) R-C network is equal to the time constant of the inductor, the voltage drop across the DCR is equal to the voltage across the capacitor, namely VDCR = VC. 900 L = R × C, than V = V C DCR = DCR × IL DCR The GM amplifier output current IX = 800 VC RCSN 700 L 600 500 DCR + V DCR - IL 400 C 300 R 200 + VC - + 100 - 0 GMx 0 25 50 75 100 125 150 175 200 225 R CSN Ix RRT (k ٛ) (kΩ) Figure 3. DCR Current Sense Circuit Figure 2. Switching Frequency vs. RT Resistance Dead Zone Elimination Control Loop The RT9258 is a two-phase voltage-mode PWM controller. The control loop includes the power stage (MOSFETs, inductors and output capacitors), the error amplifier, the compensation network and the PWM modulator. The converter's output voltage is sensed as the feedback voltage through the divider resistors and then fed into the negative input of the high-gain error amplifier. The twophase PWM signals are generated by the PWM modulator, which compares the output voltage of the error amplifier with two sawtooth waves, which are out of phase. Therefore, the output voltage of the converter is determined by the on-time duty ratio of the PWM signals. With proper compensation, the feedback voltage can be regulated to be equal to the reference voltage VREF with required transient response. Inductor Current Sense Setting When the converter is in the light load condition, the voltage across the sensing capacitor, VC, will be negative. However, the RT9258 can not provide a negative IX and consequently is not able to sense the negative inductor current. This results in a dead zone in the load line application. Therefore, a technique as shown in Figure 4 is utilized to eliminate the dead zone of the load line at light load condition. Referring to Figure 4, IX can be expressed as follows when voltage VC is negative. IX = (VOUT + IL × DCR) IL × DCR + RCSN2 RCSN To make sure that the RT9258 can sense the inductor current, the right hand side of the above equation should always be positive : VOUT I × DCR IL × DCR + L + ≥0 RCSN2 RCSN2 RCSN The DCR current sensing is a well-known lossless technique to obtain a voltage signal which is proportional to the inductor current. When the time constant of the www.richtek.com 12 DS9258-01 April 2011 RT9258 Since RCSN2 >> DCR in practical application, the above equation can be simplified as : Sensed Output Current (IX1 + IX2 ) x 2 VOUT I × DCR ≥ L RCSN2 RCSN IOUT/IMAX Therefore, RCSN2 ≤ VOUT × RCSN IL × DCR R IMAX For example, assuming the negative inductor current is equal to -5A at no load condition. For RCSN = 390Ω, DCR = 1.7mΩ, VOUT = 1.2V, 390 -5 × 1.7 × 10-3 ≤ 55.06kΩ RCSN2 ≤ 1.2 × RCSN2 Choose RCSN2 = 54.9kΩ L IL R DCR + V DCR C + VC - V OUT + - GMx Ix OCP Circuit R CSN R CSN2 Figure 4. Application Circuit for Dead Zone Elimination Optional Figure 5. Over Current Protection Function Output Voltage Droop Control and Load Line Setting The RT9258 supports the adaptive voltage droop control. The concept of the output voltage droop control is to set the output voltage level to be regulated slightly higher than the minimum value at light load, and somewhat lower than the maximum value at full load. As shown in Figure 6, a larger downward voltage drop during step load is allowed, which means the number of the required output capacitors can be reduced or allows the use of capacitor with higher ESR. As a result, the full window of output voltage tolerance can be used during the transient period (see Figure 7), which reduces the overall cost. Another advantage of output voltage droop control is that the output power of the converter at full load is reduced, which greatly facilitates the thermal design. IOUT Over Current Protection Function RIMAX = ΔI ?IOUT V OUT(max) V OUT With Droop ? V OUT ΔV OUT V OUT(min) Figure 6. Output Voltage with Droop Output Voltage Tolerance Window The over current threshold is determined by the resistor connected to IOUT/IMAX pin. The two GM amplifier's output currents are summed together and doubled, and then flows out into the resistor RIMAX, which is connected between IOUT/IMAX pin and the ground. As shown in Figure 5, the RT9258 uses an external resistor RIMAX to set a programmable over current trip point. Once the voltage across the RIMAX exceeds the threshold VOCP, the OCP function will be triggered. The following equation provides the calculation of the RIMAX value for a given maximum inductor current. If necessary, a small ceramic capacitor is recommended to be paralleled with the resistor for noise filtering to obtain accurate over current protection. VOUT (V) V OUT(max) V OUT(min) VOCP × RCSN 2 × ILOAD(MAX) × DCR IOUT (A) No Load Full Load Figure 7. Load Line DS9258-01 April 2011 www.richtek.com 13 RT9258 The two GM amplifier output currents (IX1 & IX2) are internally summed and doubled, and then sent to DROOP pin for droop setting. This current flows through the external resistor RDROOP, which is connected between DROOP and GND. Therefore, the voltage across RDROOP becomes loadcurrent-dependent. As shown in Figure 8, the voltage across RDROOP is subtracted from the internal/external reference voltage and then sent to the positive input of the error amplifier. Therefore, the load line slope can be calculated using the following equation. Load line slope = ΔVOUT 2 × DCR × RDROOP + ΔIOUT RCSN Internal/External Reference + EA - - To PWM Comparator Sensed Output Current (IX1 + IX2) x 2 FB COMP + R DROOP V DROOP - Figure 8. Output Voltage Droop Setting Operating Phase Selection The number of operating phase is designed to be selectable to have more flexibility in different applications. EN2B pin is used to select the number of operating phases. After the initial turn-on of RT9258, an internal logic circuit checks the voltage at EN2B pin. The threshold voltage of dual-phase/single-phase operation is typically 1.15V. To set RT9258 as the dual-phase PWM controller, the voltage at EN2B pin should be kept below 1.15V. To set RT9258 as a pure single-phase PWM controller, connecting EN2B pin to a voltage that is higher than 1.15V at power on. The RT9258 then disables phase 2 (UGATE2 and LGATE2 are both held low) and operates as a singlephase PWM controller. In addition to the selectable number of operating phase, the RT9258 supports the operating phase transition. Notice that if the controller is set to be in dual-phase operation (voltage at EN2B pin is below the threshold), further changing the voltage at EN2B pin to be higher than the www.richtek.com 14 Besides, also notice that if the RT9258 is set to be in single-phase operation (voltage at EN2B pin is higher the threshold), it can not be changed to operate in dual-phase no matter what voltage change is made at EN2B pin. This dual-phase to single-phase operation transition is unidirectional. Compensation Network Design + DROOP threshold will change the controller’s operating state to single-phase operation. However, this operating phase transition can only be carried out one time and is NOT reversible. This means that once the controller changes its operating state from dual-phase to single-phase, it can not back to dual-phase operation no matter what the voltage change is made at EN2B pin. In order to have an accurate output voltage regulation with fast transient response, an adequate compensator design is necessary. The RT9258 uses a high-gain operational transconductance amplifier (OTA) as the error amplifier. As Figure 9 shows, the OTA works as the voltage controlled current source because it takes the difference of the two voltages as the input for current conversion. ΔIOUT , where ΔVM = (VIN+ ) − (VIN- ) ΔVM and ΔVC = ΔIOUT × ZOUT GM = V IN+ V IN- + GM - IOUT VC Z OUT Figure 9. Operational Transconductance Amplifier, OTA The OTA output current flows through an impedance to produce a voltage, which is referred to as the control voltage. This control voltage is then fed to the PWM modulator to compare with the sawtooth wave. The first step of compensator design is to calculate the dc gain of the PWM modulator. Figure 10 shows the PWM modulator, which is composed of the PWM comparator, the drivers and both the high-side and low-side MOSFET. The dc gain of the modulator is calculated by the input voltage of the regulator, VIN, divided by the peak-to-peak voltage of the oscillator, ΔVOSC. DS9258-01 April 2011 RT9258 Gainmodulator = VIN ΔVRAMP V REF V IN PWM Comparator Error Amplifier Output, V C ?V OSC FB RF Driver + PHASE - + GM - R1 V OUT VCOMP C2 C1 R2 Figure 12. Type II Compensator Driver Figure 10. PWM Modulator As shown in Figure 11, the inductor and the output capacitor together form a low-pass L-C output filter. The input to the L-C output filter is the PHASE node and the output is the regulator output. The ESR of the output capacitor plays an important role in the compensator design. The L-C filter introduces a double pole to the system transfer function with a slope of -40dB/dec above its corner frequency and a total phase lag of 180 degree. The ESR of the output capacitor introduces a zero to the system transfer function with a total phase shift of 90 degree. PHASE LOUT DCR Regulator Output Figure 13 shows the Bode diagram of the Type II compensator. The frequencies of the single zero and the two poles are determined as follows. FP1 = 0 1 FP2 = ( 2π × R2 × C1× C2 C1+C2 1 FZ1 = 2π × R2 × C2 ) F P1 F Z1 F P2 ESR C OUT Figure 11. Inductor and Output Capacitor The second step is therefore to calculate the frequencies of the pole and the zero. The frequency of the double pole is determined as follows. FP(LC) = 1 2π × LOUT × COUT The frequency of the zero is determined as follows. FZ(ESR) = 1 2π × COUT × ESR Note that the output capacitor(s) should have enough ESR to satisfy the stability requirement. The third step is to design the compensation network. There are two kinds of compensation network: Type II and Type III, both consist of the error amplifier and the impedance network. Figure 12 shows the Type II compensator. DS9258-01 April 2011 Figure 13. Gain Curve of Type II Compensator Figure 14 shows the Bode plot of the converter's gain vs. frequency. The compensator helps to shape the profile of the gain curve with respect to frequency. The zero gives a 90° boost to the phase to counteract the phase decay of the double pole of the L-C filter. The first pole, FP1, gives a shift to the gain curve in the low frequency range while the second pole, FP2, provides further attenuation in the high frequency range. In general, a converter system control loop with high bandwidth can achieve fast transient response but usually tends to lose stability. Therefore, it is always a trade-off between the control bandwidth and the system stability. Empirically, FZ1 is placed at about 10% lower than the double pole frequency of the L-C filter to have enough phase margin. In general, the control bandwidth should be higher than the frequency of the ESR zero but less than 1/5 of the switching frequency. In addition, the FP2 should be placed at half of the switching frequency. www.richtek.com 15 RT9258 Loop Gain FZ1 60 40 40 Compensation Gain Gain (dB) 20 0 1 2π × R3 × C3 1 = 2π × R2 × C2 1 = 2π × (R1+R3) × C3 FP3 = 80 80 FZ2 0 F P1 Modulator Gain -20 -40-40 -60-60 10Hz 10vdb(vo) 100Hz vdb(comp2)100 vdb(lo) 1.0KHz 10KHz 1k 10k Frequency (Hz) Frequency 100KHz 100k 1.0MHz 1M F Z1 Figure 14. Converter System Bode Plot with Type II Compensator Figure 15 shows the Type III compensator, which introduces an extra pole-zero pair by inserting a series RC circuit between the VOUT node and the FB node. F P2 F P3 Figure 16. Gain Curve of Type III Compensator Figure 17 shows the Bode diagram of the converter's gain vs. frequency with Type III compensator. It is recommended that FZ1 is placed at half of the L-C double pole, FZ2 is placed at the LC double pole, FP1 is placed at the ESR zero and FP2 is placed at half of the switching frequency. Loop Gain 60 40 Compensation Gain 20 0 dB For systems with low DCR and ESR parameters, the overall efficiency can be higher and the output voltage ripple can be lower. However, systems that have such L-C filters will experience a very sharp slope downward in the phase curve at the double pole and will be more difficult to compensate. Compared to the Type II compensator, the Type III compensator adds a pole-zero pair. The Type III compensator utilizes two zeros to give a 180° phase boost, and is usually used to compensate a converter with low ESR output capacitors (e.g. OSCON or pure MLCC) to provide the necessary phase margin for stability. F Z2 Gain -20 -40 C3 V REF -60 + GM - R1 V OUT Modulator Gain R3 FB RF V COMP C2 R2 C1 Figure 15. Type III Compensator Figure 16 shows the Bode diagram of the Type III compensator. The frequencies of the three poles and two zeros are determined as follows. FP1 = 0 FP2 = 1 ( 2π × R2 × C1× C2 C1+C2 www.richtek.com 16 -80 2 3 4 5 6 7 Log Frequency Figure 17. Converter System Bode Plot with Type III Compensator Over Temperature Protection The operating temperature within the chip is continuously monitored. The chip will be shut down when OTP occurs with a typical trip point of 160°C. ) DS9258-01 April 2011 RT9258 Power Stages One of the most important concerns in designing a multiphase converter is to determine the number of phases. Determining the number of phases highly depends on the overall cost, the system constraints, and usually differs case by case. The main concerns for the circuit designer include the total available board space, the type of component that can be used (through-hole/surface mount device), the maximum load current, and of the most importance, total cost. In general, the most economical solutions are those in which each phase handles a current ranging from 20A to 25A (using one high-side MOSFET and one low-side MOSFET). Design with all surface mount devices will tend toward to the lower end of this current range due to the power dissipation capability. If the power device in through-hole type is available, higher current per phase is possible. In cases where the board area is the design limitation, the current per phase can be pushed up to 40A. However, these designs require appropriate heat sinks and forced air cooling to remove the large amount of heat, which is generated by the power MOSFETs, the inductors and the PCB copper traces. MOSFET Selection The majority of power loss in the step-down power conversion is due to the loss in the power MOSFETs. In the low-voltage high-current applications, the duty cycle of the high-side MOSFET is small. Therefore, the switching loss of the high-side MOSFET is of concern. Power MOSFETs with lower total gate charge are preferred in choosing the high-side power devices. However, the small duty cycle means the low-side MOSFET is on for most of the switching cycle. Therefore, the conduction loss tends to dominate the total power loss of the converter. To improve the overall efficiency, the MOSFETs with low RDS(ON) are preferred in the circuit design. In some cases, more than one MOSFET are connected in parallel to further decrease the on-state resistance. However, this depends on the low-side MOSFET driver capability and the budget. Package Power dissipation It is also important to consider the amount of power being dissipated in the two embedded MOSFET drivers when DS9258-01 April 2011 choosing power switches. Since there are two drives in the same package, the total power dissipation must not exceed the maximum allowable power dissipation for the WQFN package. Calculating the power dissipation in the drivers is crucial to ensure a safe operation of the controller. Exceeding the maximum allowable power dissipation will let the IC to be operated beyond the recommended maximum junction temperature of 125°C. The maximum power dissipation for the 4x4 WQFN package is approximately equal to 1.923W at room temperature. The following equations provide the integrated drivers' power dissipation estimation. PD = (CUGATE x VBOOT − PHASE2 x fSW) + (CLGATE x VCC2 x fSW) TJ = TA + (θJA x PD) where the CUGATE and the CLGATE represent the CISS of the high-side MOSFET and the low-side MOSFET, respectively. From the above equations, it is clear that the junction temperature is directly proportional to the total CISS of all the external MOSFETs. For instance, if CUGATE = 1nF, CLGATE = 5nF (two MOSFETs in parallel), VBOOT−PHASE = 5V, VCC = 12V, switching frequency fsw = 300kHz, the power dissipation in the driver per phase can be obtained : PD ≈ 1n x 52 x 300k + 2 x 5n x 122 x 300k = 439mW Assuming the room temperature is equal to 30°C, the junction temperature for two-phase operation is : TJ = 30°C + (52°C/W) x (0.439W x 2) = 75.6°C < 125°C, which means the junction temperature is below the maximum recommended value for a safe operation. Layout Considerations Layout plays a critical role in modern high-frequency switching converter design. Circuit board with careful layout can help the IC function properly and achieve low losses, low switching noise, and stable operation with improved performance. Without a carefully layout, the PCB could radiate excessive noise, causing noise-induced IC problems and then contribute to the converter instability. The following guidelines can be used to achieve optimal IC performance. www.richtek.com 17 RT9258 1. Power components should be placed first. Place the input capacitors close to the power MOSFETs, then locate the filter inductors and output capacitors between the power MOSFETs and the load. 2. Place both the ceramic and bulk input capacitor close to the drain pin of the high-side MOSFET. This can reduce the impedance presented by the input bulk capacitance at high switching frequency. If there is more than one high-side MOSFET in parallel, each should have its own individual ceramic capacitor. setting components and any bypass capacitors. These components belong to the high-impedance circuit loop and are inherently sensitive to noise pick-up. Therefore, they must be located close to their respective controller pins and away from the noisy switching nodes. 9. A multi-layer PCB design is recommended. Make use of one single layer as the power ground and have a separate control signal ground as the reference of all signals. 3. Keep the power loops as short as possible. For lowvoltage high-current applications, power components are the most critical part in the layout because they switch a large amount of current. The current transition from one device to another at high speed causes voltage spikes due to the parasitic components on the circuit board. Therefore, all of the high-current switching loops should be kept as short as possible with large and thick copper traces to minimize the radiation of electromagnetic interference. 4. Minimize the trace length between the power MOSFETs and its drivers. Since the drivers use short, high-current pulses to drive the power MOSFETs, the driving traces should be sized as short and large as possible to reduce the trace inductance. This is especially true for the low-side MOSFET, since this can reduce the possibility of the shoot-through. 5. Provide enough copper area around the power MOSFETs and the inductors to aid in heat sinking. Use thick copper PCB to reduce the resistance and inductance for improved efficiency. 6. The bank of output capacitor should be placed physically close to the load. This can minimize the impedance seen by the load, and then improves the transient response. 7. Place all of the high-frequency decoupling ceramic capacitors close to their decoupling targets. 8. Small signal components should be located as close as possible to the IC. The small signal components include the feedback components, current sensing components, the compensation components, function www.richtek.com 18 DS9258-01 April 2011 RT9258 Outline Dimension D2 D SEE DETAIL A L 1 E E2 e b 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A A3 A1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 3.950 4.050 0.156 0.159 D2 2.300 2.750 0.091 0.108 E 3.950 4.050 0.156 0.159 E2 2.300 2.750 0.091 0.108 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 24L QFN 4x4 Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS9258-01 April 2011 www.richtek.com 19