RT8105A 5V/12V Synchronous Buck PWM DC/DC Controller General Description Features The RT8105A is a synchronous buck PWM controller with embedded MOSFET gate drivers. This part operates with 5V/12V supply voltage, has fixed 300kHz switching frequency, and utilizes voltage mode control. The feedback control loop is compensated internally to simplify the converter design. z 5V or 12V Supply Voltage z Embedded Non-Overlapping N-MOSFET Driver 300kHz Fixed Switching Frequency Internal Control Loop Compensation Enable/Disable Control Full 0 to 100% Duty Ratio Low Side MOSFET RDS(ON) Current Sense Adjustable Over Current Protection with Improved Noise Immunity Full-Time Over Voltage Protection Fast Transient Response Internal Soft-Start RoHS Compliant and Halogen Free The RT8105A provides enable/disable function to support power sequence control. This device also provides full fault protection functions to protect the load. This part uses lossless low side MOSFET R DS(ON) current sense technique for over current protection with adjustable threshold. Other features include internal soft-start and VIN detection function. Ordering Information RT8105A z z z z z z z z z z Applications z z Package Type S : SOP-8 Lead Plating System G : Green (Halogen Free and Pb Free) Z : ECO (Ecological Element with Halogen Free and Pb free) z z z Graphic Card Motherboard IA Equipment Telecomm Equipment Mid-Power DC/DC Regulator Pin Configurations (TOP VIEW) Note : Richtek products are : ` RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. ` Suitable for use in SnPb or Pb-free soldering processes. BOOT 8 PHASE UGATE 2 7 OPS GND 3 6 FB LGATE 4 5 VCC SOP-8 Marking Information RT8105AGS RT8105AGS : Product Number RT8105A GSYMDNN RT8105AZS RT8105A ZSYMDNN YMDNN : Date Code RT8105AZS : Product Number YMDNN : Date Code DS8105A-02 April 2011 www.richtek.com 1 RT8105A Typical Application Circuit +5V to +12V D1 BAT54 VIN 5V to 12V RBOOT 0 C2 0.1µF R1 10 RT8105A 1 5 C1 1µF 6 3 BOOT VCC FB UGATE PHASE OPS GND LGATE 2 8 7 L1 1µH Q2 ML Q3 MMBT3904 C4 470µF Q1 MU ROCSET 4 Disable > R2 1.15k RUGATE 0 C3 1µF R C C6 to C8 1000µFx3 * Optional VOUT = VREF × (1+ R3 ) R2 VREF : Internal reference voltage (0.8V ± 2%) * : Each has ESR(MAX) = 28mΩ R3 1k R4 VOUT C5 Optional Functional Pin Description BOOT (Pin 1) VCC (Pin 5) Bootstrap supply pin for the upper gate driver. Connect the bootstrap capacitor between BOOT pin and the PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. Connect this pin to a well-decoupled 5V or 12V bias supply. It is also the positive supply for the lower gate driver, LGATE. FB (Pin 6) UGATE (Pin 2) Upper gate driver output. Connect to the gate of high side power N-MOSFET. This pin is monitored by the adaptive shoot through protection circuitry to determine when the upper MOSFET has turned off. GND (Pin 3) Both signal and power ground for the IC. All voltage levels are measured with respect to this pin. Ties the pin directly to the low-side MOSFET source and ground plane with the lowest impedance. LGATE (Pin 4) Lower gate drive output. Connect to the gate of low-side power N-MOSFET. This pin is monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. www.richtek.com 2 Switcher feedback voltage. This pin is the inverting input of the error amplifier. FB senses the switcher output through an external resistor divider network. OPS (OCSET, POR and Shutdown) (Pin 7) This pin provides multi-function of the over current setting, UGATE turn-on POR sensing, and shut-down features. Connecting a resistor (ROCSET) between OPS and PHASE pins sets the over-current trip point. Pulling the pin to ground resets the device and all external MOSFETs are turned off allowing the output voltage power rails to float. This pin is also used to detect VIN in power on stage and issues an internal POR signal. PHASE (Pin 8) Connect this pin to the source of the upper MOSFET and the drain of the lower MOSFET. DS8105A-02 April 2011 RT8105A Function Block Diagram VCC EN + - Bias & Regulators (3V_Logic & 3VDD_Analog) Power On Reset Reference PH_M 0.1V + 0.8VREF - 1.5V 3V 0.6V + IOC UV_S Soft-Start & Fault Logic - OC + OVP 1V 1.3V 40µA 0.4V OPS + VOC BOOT UGATE + FB GM PHASE EO + - - Gate Control Logic VCC LGATE GND DS8105A-02 April 2011 Oscillator (300kHz) www.richtek.com 3 RT8105A Absolute Maximum Ratings (Note 1) Supply Voltage, VCC -------------------------------------------------------------------------------------- 16V BOOT to PHASE ------------------------------------------------------------------------------------------ 15V z UGATE to PHASE DC ------------------------------------------------------------------------------------------------------------- −0.3V to (VBOOT−PHASE + 0.3V) < 20ns ------------------------------------------------------------------------------------------------------- −5V to (VBOOT−PHASE + 5V) z PHASE to GND DC ------------------------------------------------------------------------------------------------------------- −0.5V to 15V < 20ns ------------------------------------------------------------------------------------------------------- −5V to 25V z LGATE to GND DC ------------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V) < 20ns ------------------------------------------------------------------------------------------------------- −5V to (VCC + 5V) z Input, Output or I/O Voltage ----------------------------------------------------------------------------- GND − 0.3V to 7V z Power Dissipation, PD @ TA = 25°C (Note 2) SOP-8 -------------------------------------------------------------------------------------------------------- 0.625W z Package Thermal Resistance SOP-8, θJA -------------------------------------------------------------------------------------------------- 160°C/W z Junction Temperature ------------------------------------------------------------------------------------- 150°C z Lead Temperature (Soldering, 10 sec.) --------------------------------------------------------------- 260°C z Storage Temperature Range ---------------------------------------------------------------------------- −65°C to 150°C z ESD Susceptibility (Note 3) HBM (Human Body Mode) ------------------------------------------------------------------------------ 2kV MM (Machine Mode) -------------------------------------------------------------------------------------- 200V z z Recommended Operating Conditions z z z (Note 4) Supply Voltage, VCC -------------------------------------------------------------------------------------- 4.75V to 13.2V Junction Temperature Range ---------------------------------------------------------------------------- −20°C to 125°C Ambient Temperature Range ---------------------------------------------------------------------------- −20°C to 85°C Electrical Characteristics (VCC = 5V/12V, TA = 25°C, unless otherwise specified) Parameter Symbol Test Conditions I CC UGATE and LGATE Open, VCC = 12V POR Threshold VCCRTH VCC Rising Hysteresis VCCHYS Nominal Supply Current Min Typ Max Unit -- 4 15 mA 3.8 4.1 4.35 V 0.35 0.55 -- V Power-On Reset Switcher Reference VREF VCC = 12V 0.784 0.8 0.816 V Free Running Frequency fOSC VCC = 12V 250 300 350 kHz Ramp Amplitude ΔVOSC VCC = 12V -- 1.5 -- VP-P Feedback Reference Voltage Oscillator To be continued www.richtek.com 4 DS8105A-02 April 2011 RT8105A Parameter Symbol Test Conditions Min Typ Max Unit Error Amplifier (GM) E/A Transconductance gm (Note 5) -- 0.2 -- ms Open Loop DC Gain AO (Note 5) -- 90 -- dB 0.6 1 -- A -- 4 8 Ω PWM Controller Gate Drivers (VCC = 12V) Upper Gate Source IUGATE VBOOT − VPHASE = 12V, VUGATE − VPHASE = 6V VBOOT − VPHASE = 12V, VUGATE − VPHASE = 1V Upper Gate Sink RUGATE Lower Gate Source ILGATE VCC = 12V, VLGATE = 6V 0.6 1 -- A Lower Gate Sink RLGATE VCC = 12V, VLGATE = 1V -- 3 5 Ω FB Under-Voltage Trip Δ FBUVT FB Falling 70 75 80 % OC Current Source IOC VPHASE = 0V 35 40 45 μA Pre-OVP Threshold (Before POR) VOVP1 VCC = 3V, Sweep VFB -- 0.7 1.3 V OVP Threshold (After POR) VOVP2 VCC = 5V, Sweep VFB 1 1.3 1.5 V Soft-Start Interval TSS -- 4.5 -- ms Protection Note 1. Stresses listed as the above "Absolute Maximum Ratings" may cause permanent damage to the device. These are for stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may remain possibility to affect device reliability. Note 2. θJA is measured in natural convection at TA = 25°C on a low-effective thermal conductivity single-layer test board of JEDEC 51-3 thermal measurement standard. The measurement case position of θJC is on the lead of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Guarantee by design. DS8105A-02 April 2011 www.richtek.com 5 RT8105A Typical Operating Characteristics Power On from VIN V CC (10V/Div) VIN (5V/Div) VIN (5V/Div) VOUT (1V/Div) UGATE (20V/Div) LGATE (20V/Div) VIN and VCC Power Sequence UGATE (20V/Div) VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 20A VOUT (1V/Div) VIN comes after VCC VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 20A Time (2ms/Div) Time (2ms/Div) Enable from OPS Disable from OPS OPS (2V/Div) OPS (2V/Div) VOUT (1V/Div) VOUT (1V/Div) UGATE (20V/Div) LGATE (20V/Div) UGATE (20V/Div) LGATE (20V/Div) VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 5A VIN = VCC = 12V, VOUT = 1.5V, ILOAD = 5A Time (2ms/Div) Time (40μs/Div) Under Voltage Protection Over Voltage Protection VIN = 5V, VCC = 12V, VOUT = 1.5V, No Load FB (500mV/Div) FB (500mV/Div) UGATE (10V/Div) UGATE (10V/Div) LGATE (10V/Div) LGATE (10V/Div) Time (20μs/Div) www.richtek.com 6 VIN = 5V, VCC = 12V, VOUT = 1.5V, No Load Time (20μs/Div) DS8105A-02 April 2011 RT8105A Over Current Protection Short Circuit Over Current Protection Low side MOSFET RDS(ON) = 9mΩ VIN = VCC = 12V, Low side MOSFET RDS(ON) = 9mΩ ROCSET = 15kΩ Inductor Current (20A/Div) Inductor Current (20A/Div) VOUT (2V/Div) VOUT (200mV/Div) UGATE (20V/Div) UGATE (20V/Div) LGATE (20V/Div) LGATE (20V/Div) VIN = VCC = 12V, VOUT = 1.5V, ROCSET = 15.4kΩ short circuit output terminal than power up Time (20μs/Div) Time (1ms/Div) Switching Frequency vs. Temperature 400 0.812 380 Switching Frequency (kHz)1 Reference Voltage (V) Reference Voltage vs. Temperature 0.816 0.808 0.804 0.800 0.796 0.792 0.788 VIN = VCC = 5V, No Load 0.784 360 340 320 300 280 260 240 220 VIN = VCC = 5V, No Load 200 -50 -25 0 25 50 Temperature (°C) DS8105A-02 April 2011 75 100 125 -50 -25 0 25 50 75 100 125 Temperature (°C) www.richtek.com 7 RT8105A Application Information The RT8105A is a fixed-frequency, single phase synchronous buck controller with embedded MOSFET gate drivers. This part provides precise output voltage regulation, supports enable/disable control, and has complete fault protection functions. The RT8105A utilizes lossless RDS(ON) current sense technique, and provides adjustable over current protection. This IC uses voltage mode control and the control loop is internally compensated to eliminate external component count. Count = 2 Count = 4 Count = 1 Count = 3 1 st nd 2 rd 3 4 th OPS 1.5V UGATE VIN Ready VCC Power on Reset and VIN Detection At start up, when VCC initially rises above the power on reset (POR) rising threshold VCCRTH, UGATE pin will output continuous pulses (about 10kHz, 1% duty cycle) for converter input voltage VIN detection. The RT8105A detects the voltage pulses at OPS pin to recognize that VIN is ready. Figure 1 shows the operation of input voltage VIN detection. If the OPS voltage exceeds 1.5V for four times, making internal counter = 4 (both rising edge + falling edge for counter increment = 1), VIN is recognized ready. Once VIN is recognized ready, controller will initiates soft start operation. Because an internal current source (for over current protection) will continuously flow out of OPS pin, ROCSET is highly recommended to be less than 30kΩ to ensure correct operation. 3V IOC OC OPS + VOC + - VIN Detection Counter ROCSET Voltage Clamp Disable + - + 1.5V UGATE PHASE Figure 1. VIN Detection Function Soft-Start Once VIN is recognized ready, LGATE will go high for a short period of time to discharge the pre-biased voltage at the output capacitor. After that, controller will initiate soft start operation. RT8105A provides soft start function internally. The soft start function is used to prevent the large inrush current while converter is powered up. The FB signal will track the internal soft start signal, which is controlled by an internal digital counter and ramps up from zero in a monotone during soft start period. Therefore the duty cycle of UGATE signal will increase gradually and so does the input current. The typical soft start time duration is 3ms. Over Current Protection (OCP) The RT8105A utilizes RDS(ON) current sense technique to detect the inductor valley current for over current protection. Figure 2 shows the Over Current Protection (OCP) scheme of RT8105A. A resistor ROCSET connected from PHASE pin to OPS pin sets the threshold. An internal current source IOC flows out of OPS pin through ROCSET determines the OCP trip point IOCSET, which can be calculated using the following equation : IOCSET ≈ www.richtek.com 8 40 μ A × ROCSET − 0.4 RDS(ON) of the low side MOSFET DS8105A-02 April 2011 RT8105A Because the R DS(ON) of MOSFET increases with temperature, it is necessary to take this thermal effect into consideration in calculating OCP point. 3V VIN IOC OC Comparator - OPS + ROCSET + 0.4V Q1 + IOC x ROCSET - PHASE L ID x RDS(ON) Q2 + Figure 2. Over Current Protection Scheme Inductor valley current exceeds OCP trip point IOCSET in one switching cycle is regarded as an over current event. The controller has an internal counter to monitor the over current event. To avoid OCP false tripping, only four consecutive over current events will trip OCP. When OCP is tripped, the controller shuts down, both UGATE and LGATE will go low to stop the energy transfer to the load. The OCP is a latched protection, it can only be reset by toggling VCC POR. Over Voltage Protection (OVP) The feedback voltage at FB pin is continuously monitored for over voltage protection. When OVP is tripped, UGATE will go low and LGATE will go high to discharge the output capacitor. RT8105A provides full-time over voltage protection whenever soft start completes or not. Over voltage protection has two operating conditions: before soft start completes and after soft start completes. Each condition is described as follows. Before soft start completes, the typical OVP threshold is 125% of the internal reference voltage VREF. RT8105A provides non-latched OVP before soft start completes. The controller will return to normal operation if over voltage condition is removed. After soft start completes, however, the OVP threshold is typically raised to 162.5% of VREF. RT8105A provides latched OVP, which means controller will shut down. Under this condition, the controller can only be reset if VCC POR is toggled. DS8105A-02 April 2011 Under Voltage Protection (UVP) The feedback voltage at FB pin is also monitored for under voltage protection. The under voltage protection has a 10μs triggered time delay. When UVP is triggered, both UGATE and LGATE will go low. The UVP is not a latched protection, controller will always try to restart in a hiccupped way. Enable/Disable Control The RT8105A supports enable/disable control function to provide the flexibility in power sequence control. The controller is disabled by pulling OPS pin to ground. It is recommended to use bipolar junction transistor (BJT) to implement the enable/disable function. Note that the OCP point is very sensitive to the parasitic capacitance at OPS pin. Parasitic capacitance at OPS pin will have influence on the OCP point. To minimize PCB trace parasitic component, it is recommended to place the BJT and ROCSET close to IC, and use short copper trace. Input Capacitor Selection The selection of input capacitor depends on the converter input ripple current. The buck converter draws current from the input capacitor when high side MOSFET is on, this input current is pulsating. The RMS value of the ripple current flowing through the input capacitor can be expressed as follows : Irms = IOUT D(1 − D) (A) The input capacitor must be able to handle this RMS current. It is recommended to add ceramic capacitors and place them physically close to the drain of the high side MOSFET. This can effectively reduce the input ripple voltage of the converter. Output Inductor Selection The selection of output inductor depends on the output current and operating frequency. Low inductance value provides fast transient response, but the associated large current ripple will cause large output voltage ripple and decrease efficiency. The first step is to determine the inductor current ripple according to the rated load current IOUT, which is given by the converter specification. In general, a 20% to 40% of www.richtek.com 9 RT8105A inductor ripple current percentage (ΔIL/IOUT) is preferred in practical application. Therefore the inductor current ripple ΔIL can be obtained. The minimum inductance can then be determined as follows : L = (VIN − VOUT ) × VOUT VIN × fS × ΔIL Control Loop Stability The RT8105A utilizes operational transconductance amplifier (OTA) as the error amplifier and implements the control loop compensation network internally. Figure 3 shows the internal Type II compensator, which provides two poles and one zero to the control loop. Where : VIN = Input voltage VCOMP GM VOUT = Output voltage C1 ΔIL = Inductor current ripple R1 C2 fS = Switching frequency Output Capacitor Selection The selection of output capacitor depends on the inductor ripple current, the output ripple voltage and the amount of voltage undershoot during load transient. The output ripple voltage is a function of both the capacitance and the equivalent series resistance (ESR). The output ripple voltage can be expressed as follows : ΔVOUT = ΔVOR + ΔVOC 1 t2 ∫ iC dt COUT t1 OUT V = ΔIL × ESR + 1 OUT (1− D)TS2 8 COUT ΔVOUT = ΔIL × ESR + ΔVOUT where ΔVOR is caused by ESR, and ΔVOC is related to the capacitance value. For electrolytic capacitor application, major of the output voltage ripple is typically contributed by the ESR. Therefore, the output voltage ripple can be simplified as follows : ΔVOUT = ΔIL x ESR Therefore the ESR can be determined for a given output voltage ripple requirement as the reference of capacitor selection. The output capacitor must be able to handle the inductor ripple current that is determined in the first step. Refer to the capacitor datasheet and choose capacitor with sufficient ripple current rating, the ESR can also be obtained from the datasheet. Once the L, C and ESR are known, the next step is to check the close loop stability. www.richtek.com 10 Figure 3. Internal Type II Compensator One of the poles is located at low frequency to increase the low frequency gain to improve the DC regulation accuracy, the location of the other pole and the zero can be calculated as follows : 1 1 FZ = ; FP = 2π × R1× C1 ⎛ C1× C2 ⎞ 2π × R1× ⎜ ⎟ ⎝ C1+ C2 ⎠ The transconductance and the internal compensation values are : gm = 0.2mA/V, R1 ≈ 75kΩ, C1 ≈ 2.5nF, C2 ≈ 10pF. The gain of the internal compensator at middle frequency can be calculated as follows : Gmid-freq. = gm x R1 Figure 4 shows the system Bode plot. The close loop gain is the sum of the modulation gain and the compensation gain. The goal is to obtain the required crossover frequency with sufficient phase margin. The general guideline is to design the crossover frequency as between 1/10 to 1/5 of the switching frequency. The phase margin is preferred to be greater than 45° to ensure stability. Because RT8105A utilizes internal compensation for the control loop, the location of FZ, FP and the gain at midfrequency provided by the internal compensator are fixed. Therefore the inductance, output capacitance and the ESR of the output capacitor should be carefully selected to avoid instability. DS8105A-02 April 2011 RT8105A The location of the double pole FLC and the ESR zero FESR can be calculated as follows : 1 1 FLC = ; FESR = 2π × L × C 2π × ESR × C For an given L and C, if the ESR is too small, the location of the zero contributed by ESR is far away from that of the LC double pole, the system will not have sufficient phase margin. If the ESR is too large, the location of the ESR zero moves towards low-frequency, the crossover frequency may go beyond 1/5 switching frequency, resulting in higher jitter and unstable operation. Manipulate the Bode plot according to the chosen L, C and ESR value to check the stability before circuit implementation. If the phase margin is insufficient or the bandwidth is far beyond the general guideline, the inductor, output capacitor and ESR values should be reselected, and the stability should be checked again. To meet the stability criteria, two or more capacitors in parallel is a common practice. where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications of the RT8105A, the maximum junction temperature is 125°C and TA is the ambient temperature. The junction to ambient thermal resistance, θJA, is layout dependent. For SOP-8 packages, the thermal resistance, θJA, is 160°C/W on a standard JEDEC 51-3 single-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula : PD(MAX) = (125°C − 25°C) / (160°C/W) = 0.625W for SOP-8 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. For the RT8105A package, the derating curve in Figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. gm•R1• (voltage divider ratio) Compensator FZ FP FCROSS Freq. (log scale) Close Loop FLC FESR Modulator Figure 4. System Bode Plot Thermal Considerations Maximum Power Dissipation (W) Gain (dB) 0.70 0.65 0.60 0.55 0.50 0.45 0.40 0.35 0.30 0.25 0.20 0.15 0.10 0.05 0.00 Single-Layer PCB 0 25 50 75 100 125 Ambient Temperature (°C) Figure 5. Derating Curve for RT8105A Package For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA DS8105A-02 April 2011 www.richtek.com 11 RT8105A reduce the trace inductance. This is especially important for low side MOSFET, because this can reduce the possibility of shoot-through. Make the width of gate driving path (include the trace to the bootstrap capacitor and diode) as wide as possible to reduce the trace resistance. Layout Considerations PCB layout is critical to high current high frequency switching converter design. A good layout can help the controller to function properly and obtain better performance. In reverse, the circuit may have more power loss, pool performance and even malfunction without a carefully layout. The general guidelines of PCB layout are listed as follows for reference. ` ` ` ` Power stage components should be placed first. Place the input bulk capacitors close to the high-side power MOSFETs, and then locate the output inductor. Finally, place the output capacitors. Place the ceramic capacitors physically close to the drain of the high-side MOSFET. This can reduce the input voltage drop when high side MOSFET is turned on. Keep the high current loops as short as possible. The current transition between MOSFETs usually causes di/dt voltage spike due to the parasitic components of PCB trace and component lead. Therefore, making the trace length between power MOSFETs and inductors wide and short can reduce the voltage spike and also reduce EMI. Make MOSFET gate driver path as short as possible. Since the gate driver uses high current pulses to switch on/off power MOSFET, the driver path must be short to ` The output capacitors should be placed physically close to the load. This can minimize the trace parasitic components and improve transient response. ` Voltage feedback path must be kept away from switching nodes. The switching nodes, such as the interconnection between high-side MOSFET, low side MOSFET and inductor, are extremely noisy. Feedback path must be kept away from this kind of noisy node to avoid noise pick-up. ` The feedback voltage divider resistor must be placed close to FB pin because it is noise-sensitive. ` OCP threshold setting resistor, ROCSET, should be placed close to the controller. ` The BJT used for enable/disable control should be placed close to the controller to minimize the trace parasitic components. ` A multi-layer PCB design is recommended. Use one single layer as the solid ground plane. Place bootstrap circuit close to IC pins. Enough copper area to carry load current. Via to inner layer. MOSFET driver trace : wide and short. Place CIN close to MOSFET. VOUT1 Place ROCSET and BJT close to IC. VIN BOOT 8 PHASE UGATE 2 7 OPS GND 3 6 FB LGATE 4 5 VCC EN Place voltage divider resistors close to IC. LOAD 5V/12V Via to inner ground layer. Place COUT Place snubber close close to load. to low-side MOSFET. Enough via around MOSFET lead to inner ground layer. Via to inner layer. Place noise decoupling MLCC close to VCC pin. Keep voltage feedback trace away from noisy node. Figure 6. PCB Layout Guide www.richtek.com 12 DS8105A-02 April 2011 RT8105A Outline Dimension H A M J B F C I D Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 4.801 5.004 0.189 0.197 B 3.810 3.988 0.150 0.157 C 1.346 1.753 0.053 0.069 D 0.330 0.508 0.013 0.020 F 1.194 1.346 0.047 0.053 H 0.170 0.254 0.007 0.010 I 0.050 0.254 0.002 0.010 J 5.791 6.200 0.228 0.244 M 0.400 1.270 0.016 0.050 8-Lead SOP Plastic Package Richtek Technology Corporation Richtek Technology Corporation Headquarter Taipei Office (Marketing) 5F, No. 20, Taiyuen Street, Chupei City 5F, No. 95, Minchiuan Road, Hsintien City Hsinchu, Taiwan, R.O.C. Taipei County, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611 Tel: (8862)86672399 Fax: (8862)86672377 Email: [email protected] Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek. DS8105A-02 April 2011 www.richtek.com 13