RICHTEK RT8869A

RT8869A
Advanced 2/1-Phase PWM Controller for CPU Core Power
General Description
Features
The RT8869A is an advanced 2/1-phase synchronous buck
controller with 2 integrated MOSFET drivers. It integrates
an 8-bit DAC that supports Intel VR11.x CPUs power
application.
z
12V Power Supply Voltage
z
2/1-Phase Power Conversion
Integrated 2 MOSFET Drivers with Internal
Bootstrap Diode
Dynamic Phase Control Capability
8-bit DAC Supports Intel VR11.x CPUs
Lossless RDS(ON) Current Sensing for Current Balance
Adjustable Frequency : 50kHz to 1MHz
Adjustable Over Current Protection
Adjustable Soft-Start
VR_RDY, VR_HOT and VR_SHDN Indications
Small 40-Lead WQFN Package
RoHS Compliant and Halogen Free
z
z
z
z
z
z
z
z
The RT8869A is available in a small footprint with WQFN40L 5x5 package.
Ordering Information
RT8869A
Applications
z
z
z
Package Type
QW : WQFN-40L 5x5 (W-Type)
Lead Plating System
Z : ECO (Ecological Element with
Halogen Free and Pb free))
Desktop CPU Core Power
Middle/High End Graphic Cards
Low Voltage, High Current DC/ DC Converters
Pin Configurations
(TOP VIEW)
FBRTN
VID0
VID1
VID2
VID3
VID4
VID5
VID6
VID7
BOOT1
to achieve phase current balance. Other features include
adjustable operating frequency, adjustable soft-start, short
circuit protection, adjustable over current protection, over
voltage protection, under voltage protection, power good
indication, VR_HOT indication and VR_SHDN indication.
z
Note :
Richtek products are :
`
RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020.
`
Suitable for use in SnPb or Pb-free soldering processes.
Marking Information
RT8869AZQW : Product Number
RT8869A
ZQW
YMDNN
YMDNN : Date Code
40 39 38 37 36 35 34 33 32 31
VRSEL
VR_RDY
SS
EN
DAC
EAP
FB
COMP
CSP
CSN
1
30
2
29
3
28
4
27
5
6
26
GND
25
24
7
8
9
41
23
22
21
10
UGATE1
PHASE1
LGATE1
VCC12A
VCC12B
LGATE2
PHASE2
UGATE2
BOOT2
VR_HOT
11 12 13 14 15 16 17 18 19 20
IMAX
VR_SHDN
PS1
ISEN2
ISEN1
RT
VCC5
TB
VOUT
TM
The IC adopts state-of-the-art dynamic phase control
capability by PS1 pin and achieves high efficiency over a
wide load range. It uses lossless RDS(ON) current sensing
z
WQFN-40L 5x5
DS8869A-00 May 2011
www.richtek.com
1
www.richtek.com
2
PH2
PH1
VVR_SHDN
VSHDN
Q9
R31
R30
R18
VCC5
R17
C5
12V
VCC_SNS
VVR_HOT
VTT
R21
R15
VR_SHDN
TM
VR_HOT
TB
41 (Exposed Pad)
GND
26 VCC12B
C16
27 VCC12A
C15
18
16 RT
21
4 EN
9 CSP
10 CSN
13 PS1
12
20
IMAX
11
40
SS 3
FBRTN
COMP 8
VOUT 19
FB 7
ISEN2 14
UGATE2 23
PHASE2 24
LGATE2 25
BOOT2 22
R5
R3
R2
R6
R4
C9
C5
C11 R12
Q4
Q3
L1
L2
C8
R37
C6
C7
R38
C3
C14
C33
VIN
4.5V to 13.2V
Q2
Q1
VIN
4.5V to 13.2V
R11
C4
C2
C13
R10
R8
C10
R9
R7
VVR_RDY
VTT
R35
32 to 39
1
VRSEL
VR_RDY 2
VID[7:0]
EAP 6
PHASE1 29
28
LGATE1
15
ISEN1
DAC 5
BOOT1 31
UGATE1 30
RT8869A
17 VCC5
R1
C26
RRT
C17
RPS1
NTC2
R16
R29
R24
CSN+
R23
NTC1
R20
Chip Enable
R19
C23
C1
C12
C30
CSN+
R40
CSN+
R41
C29
R13
VCC_SNS
LOAD
VSS_SNS
R14
C34
VCORE
RT8869A
Typical Application Circuit
DS8869A-00 May 2011
RT8869A
Table 1. VR11.1 VID Code Table
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
0
0
0
0
0
0
0
OFF
0
0
1
0
0
0
1
1
1.39375
0
0
0
0
0
0
0
1
OFF
0
0
1
0
0
1
0
0
1.38750
0
0
0
0
0
0
1
0
1.60000
0
0
1
0
0
1
0
1
1.38125
0
0
0
0
0
0
1
1
1.59375
0
0
1
0
0
1
1
0
1.37500
0
0
0
0
0
1
0
0
1.58750
0
0
1
0
0
1
1
1
1.36875
0
0
0
0
0
1
0
1
1.58125
0
0
1
0
1
0
0
0
1.36250
0
0
0
0
0
1
1
0
1.57500
0
0
1
0
1
0
0
1
1.35625
0
0
0
0
0
1
1
1
1.56875
0
0
1
0
1
0
1
0
1.35000
0
0
0
0
1
0
0
0
1.56250
0
0
1
0
1
0
1
1
1.34375
0
0
0
0
1
0
0
1
1.55625
0
0
1
0
1
1
0
0
1.33750
0
0
0
0
1
0
1
0
1.55000
0
0
1
0
1
1
0
1
1.33125
0
0
0
0
1
0
1
1
1.54375
0
0
1
0
1
1
1
0
1.32500
0
0
0
0
1
1
0
0
1.53750
0
0
1
0
1
1
1
1
1.31875
0
0
0
0
1
1
0
1
1.53125
0
0
1
1
0
0
0
0
1.31250
0
0
0
0
1
1
1
0
1.52500
0
0
1
1
0
0
0
1
1.30625
0
0
0
0
1
1
1
1
1.51875
0
0
1
1
0
0
1
0
1.30000
0
0
0
1
0
0
0
0
1.51250
0
0
1
1
0
0
1
1
1.29375
0
0
0
1
0
0
0
1
1.50625
0
0
1
1
0
1
0
0
1.28750
0
0
0
1
0
0
1
0
1.50000
0
0
1
1
0
1
0
1
1.28125
0
0
0
1
0
0
1
1
1.49375
0
0
1
1
0
1
1
0
1.27500
0
0
0
1
0
1
0
0
1.48750
0
0
1
1
0
1
1
1
1.26875
0
0
0
1
0
1
0
1
1.48125
0
0
1
1
1
0
0
0
1.26250
0
0
0
1
0
1
1
0
1.47500
0
0
1
1
1
0
0
1
1.25625
0
0
0
1
0
1
1
1
1.46875
0
0
1
1
1
0
1
0
1.25000
0
0
0
1
1
0
0
0
1.46250
0
0
1
1
1
0
1
1
1.24375
0
0
0
1
1
0
0
1
1.45625
0
0
1
1
1
1
0
0
1.23750
0
0
0
1
1
0
1
0
1.45000
0
0
1
1
1
1
0
1
1.23125
0
0
0
1
1
0
1
1
1.44375
0
0
1
1
1
1
1
0
1.22500
0
0
0
1
1
1
0
0
1.43750
0
0
1
1
1
1
1
1
1.21875
0
0
0
1
1
1
0
1
1.43125
0
1
0
0
0
0
0
0
1.21250
0
0
0
1
1
1
1
0
1.42500
0
1
0
0
0
0
0
1
1.20625
0
0
0
1
1
1
1
1
1.41875
0
1
0
0
0
0
1
0
1.20000
0
0
1
0
0
0
0
0
1.41250
0
1
0
0
0
0
1
1
1.19375
0
0
1
0
0
0
0
1
1.40625
0
1
0
0
0
1
0
0
1.18750
0
0
1
0
0
0
1
0
1.40000
0
1
0
0
0
1
0
1
1.18125
To be continued
DS8869A-00 May 2011
www.richtek.com
3
RT8869A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
0
1
0
0
0
1
1
0
1.17500
0
1
1
0
1
0
1
0
0.95000
0
1
0
0
0
1
1
1
1.16875
0
1
1
0
1
0
1
1
0.94375
0
1
0
0
1
0
0
0
1.16250
0
1
1
0
1
1
0
0
0.93750
0
1
0
0
1
0
0
1
1.15625
0
1
1
0
1
1
0
1
0.93125
0
1
0
0
1
0
1
0
1.15000
0
1
1
0
1
1
1
0
0.92500
0
1
0
0
1
0
1
1
1.14375
0
1
1
0
1
1
1
1
0.91875
0
1
0
0
1
1
0
0
1.13750
0
1
1
1
0
0
0
0
0.91250
0
1
0
0
1
1
0
1
1.13125
0
1
1
1
0
0
0
1
0.90625
0
1
0
0
1
1
1
0
1.12500
0
1
1
1
0
0
1
0
0.90000
0
1
0
0
1
1
1
1
1.11875
0
1
1
1
0
0
1
1
0.89375
0
1
0
1
0
0
0
0
1.11250
0
1
1
1
0
1
0
0
0.88750
0
1
0
1
0
0
0
1
1.10625
0
1
1
1
0
1
0
1
0.88125
0
1
0
1
0
0
1
0
1.10000
0
1
1
1
0
1
1
0
0.87500
0
1
0
1
0
0
1
1
1.09375
0
1
1
1
0
1
1
1
0.86875
0
1
0
1
0
1
0
0
1.08750
0
1
1
1
1
0
0
0
0.86250
0
1
0
1
0
1
0
1
1.08125
0
1
1
1
1
0
0
1
0.85625
0
1
0
1
0
1
1
0
1.07500
0
1
1
1
1
0
1
0
0.85000
0
1
0
1
0
1
1
1
1.06875
0
1
1
1
1
0
1
1
0.84375
0
1
0
1
1
0
0
0
1.06250
0
1
1
1
1
1
0
0
0.83750
0
1
0
1
1
0
0
1
1.05625
0
1
1
1
1
1
0
1
0.83125
0
1
0
1
1
0
1
0
1.05000
0
1
1
1
1
1
1
0
0.82500
0
1
0
1
1
0
1
1
1.04375
0
1
1
1
1
1
1
1
0.81875
0
1
0
1
1
1
0
0
1.03750
1
0
0
0
0
0
0
0
0.81250
0
1
0
1
1
1
0
1
1.03125
1
0
0
0
0
0
0
1
0.80625
0
1
0
1
1
1
1
0
1.02500
1
0
0
0
0
0
1
0
0.80000
0
1
0
1
1
1
1
1
1.01875
0
1
1
0
0
0
0
0
1.01250
1
0
0
0
0
0
1
1
0.79375
1
0
0
0
0
1
0
0
0.78750
0
1
1
0
0
0
0
1
1.00625
1
0
0
0
0
1
0
1
0.78125
0
1
1
0
0
0
1
0
1.00000
0
1
1
0
0
0
1
1
0.99375
1
0
0
0
0
1
1
0
0.77500
0
1
1
0
0
1
0
0
0.98750
1
0
0
0
0
1
1
1
0.76875
0
1
1
0
0
1
0
1
0.98125
1
0
0
0
1
0
0
0
0.76250
0
1
1
0
0
1
1
0
0.97500
1
0
0
0
1
0
0
1
0.75625
0
1
1
0
0
1
1
1
0.96875
1
0
0
0
1
0
1
0
0.75000
0
1
1
0
1
0
0
0
0.96250
1
0
0
0
1
0
1
1
0.74375
0
1
1
0
1
0
0
1
0.95625
1
0
0
0
1
1
0
0
0.73750
1
0
0
0
1
1
0
1
0.73125
To be continued
www.richtek.com
4
DS8869A-00 May 2011
RT8869A
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 Voltage
1
0
0
0
1
1
1
0
0.72500
1
0
1
1
0
0
1
0
0.50000
1
0
0
0
1
1
1
1
0.71875
1
1
1
1
1
1
1
0
OFF
1
0
0
1
0
0
0
0
0.71250
1
1
1
1
1
1
1
1
OFF
1
0
0
1
0
0
0
1
0.70625
1
0
0
1
0
0
1
0
0.70000
1
0
0
1
0
0
1
1
0.69375
1
0
0
1
0
1
0
0
0.68750
1
0
0
1
0
1
0
1
0.68125
1
0
0
1
0
1
1
0
0.67500
1
0
0
1
0
1
1
1
0.66875
1
0
0
1
1
0
0
0
0.66250
1
0
0
1
1
0
0
1
0.65625
1
0
0
1
1
0
1
0
0.65000
1
0
0
1
1
0
1
1
0.64375
1
0
0
1
1
1
0
0
0.63750
1
0
0
1
1
1
0
1
0.63125
1
0
0
1
1
1
1
0
0.62500
1
0
0
1
1
1
1
1
0.61875
1
0
1
0
0
0
0
0
0.61250
1
0
1
0
0
0
0
1
0.60625
1
0
1
0
0
0
1
0
0.60000
1
0
1
0
0
0
1
1
0.59375
1
0
1
0
0
1
0
0
0.58750
1
0
1
0
0
1
0
1
0.58125
1
0
1
0
0
1
1
0
0.57500
1
0
1
0
0
1
1
1
0.56875
1
0
1
0
1
0
0
0
0.56250
1
0
1
0
1
0
0
1
0.55625
1
0
1
0
1
0
1
0
0.55000
1
0
1
0
1
0
1
1
0.54375
1
0
1
0
1
1
0
0
0.53750
1
0
1
0
1
1
0
1
0.53125
1
0
1
0
1
1
1
0
0.52500
1
0
1
0
1
1
1
1
0.51875
1
0
1
1
0
0
0
0
0.51250
1
0
1
1
0
0
0
1
0.50625
DS8869A-00 May 2011
www.richtek.com
5
RT8869A
Functional Pin Description
Pin No.
Pin Name
1
VRSEL
2
VR_RDY
3
SS
4
EN
5
DAC
6
EAP
7
FB
8
COMP
9, 10
CSP, CSN
Pin Function
Load Line Adjustment Enable Pin. Connect this pin to VTT and GND to
disable and enable load line adjustment function respectively.
VR Ready Indication.
Soft-Start Ramp Slope Set Pin. Connect this pin to FBRTN by a
capacitor to adjust soft-start slew rate.
Chip Enable Pin. Pull this pin higher than 0.8V to enable the PWM
controller.
DAC Output Pin. Connect a resistor from this pin to EAP pin for setting
the load line slope.
Non-inverting Input of Error-Amplifier Pin. Connect a resistor from this
pin to DAC pin to set the load line slope.
Inverting Input of Error Amplifier Pin.
Compensation Pin. Output of error amplifier and input of PWM
comparator.
Input of Current Sensing Amplifier. The sensed current is for droop
control and over current protection.
Output Current Indication. Connect a resistor from this pin to GND to set
the over current protection threshold.
11
IMAX
12
VR_SHDN
VR_SHDN Indication.
13
PS1
Dynamic Phase Control Threshold Input 1. Connect this pin to GND by a
resistor to set dynamic phase control threshold.
ISEN2, ISEN1
Phase Current Sense Pins for Phase 2 and Phase 1. Per phase current
signal is sensed via the voltage across low side MOSFETs R DS(ON) for
current balance.
16
RT
Switching Frequency Set Pin. Connect this pin to GND via a resistor to
adjust switching frequency.
17
VCC5
18
TB
19
VOUT
20
TM
21
VR_HOT
14, 15
22, 31
BOOT2, BOOT1
23, 30
UGATE2, UGATE1
24, 29
PHASE2, PHASE1
25, 28
LGATE2, LGATE1
Internal 5V Regulator Output.
Transient Boost Pin. This pin along with the VOUT pin sets the transient
boost function.
Positive Voltage Sensing Pin. This pin is the positive node of the
differential voltage sensing and along with TB pin sets the transient boost
function.
Thermal Monitoring Input Pin. Connect a resistive voltage divider with
NTC to detect temperature.
Thermal Monitoring Output Pin. Connect a resistor to VTT for VR_HOT
signal assertion.
Bootstrap Power Pins for Phase 2 and Phase 1. This pin powers the high
side MOSFETs drivers. Connect this pin to the junction of the bootstrap
capacitor with the cathode of the bootstrap diode.
Upper Gate Drivers for Phase 2 and Phase 1. This pin drives the gate of
the high side MOSFETs.
Switch Nodes of High Side Driver 2 and Driver 1. Connect this pin to high
side MOSFETs sources together with the low side MOSFETs drains and
inductor.
Lower Gate Drivers for Phase 2 and Phase 1. This pin drives the gate of
low side MOSFETs.
To be continued
www.richtek.com
6
DS8869A-00 May 2011
RT8869A
Pin No.
Pin Name
26
27
32 to 39
40
41
(Exposed pad)
Pin Function
VCC12B
Supply Input Pin. This pin supplies current for phase 2 gate driver.
VCC12A
Supply Input Pin. This pin supplies current for phase 1 gate driver and
control circuits.
VID7 to VID0
Voltage Identification Input for DAC.
FBRTN
Return Ground Pin. This pin is negative node of the differential remote
voltage sending.
GND
Ground. The exposed pad must be soldered to a large PCB and
connected to GND for maximum power dissipation.
SS
SoftStart
VR_RDY
Table Generator
VCC12A
VCC5
VID0
VID1
VID2
VID3
VID4
VID5
VID6
EN
FBRTN
VID7
Function Block Diagram
POR
5V
Regulator
DAC
COMP
EAP
FB
PWM1
+
+
EA
-
VEAP + 160mV
-
BOOT1
MOSFET
Driver
OVP
-
VEAP - 300mV
IMAX
VRSEL
UVP
+
+
Load Line
Adjustment
CSN
-
CSP
+
IX
1.2V
OCP
-
PWM2
+
-
BOOT2
MOSFET
Driver
TB
+
- ISEN1
+
ISEN1
VDC
DS8869A-00 May 2011
+
-
PHASE2
VCC12B
Transient
Response
Enhancement
- ISEN2
UGATE2
LGATE2
VOUT
ISEN2
PHASE1
LGATE1
+
IX
UGATE1
VR_SHDN
Thermal
Monitor
VR_HOT
S/H
S/H
TM
GND
Current
Balance
Modulator
Waveform
Generator
RT
PS1
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7
RT8869A
Absolute Maximum Ratings
z
z
z
z
z
z
z
z
z
z
z
(Note 1)
Supply Input Voltage (VCC12A, VCC12B) --------------------------------------------------- −0.3V to 15V
BOOTx to PHASEx -------------------------------------------------------------------------------- −0.3V to 15V
PHASEx to GND
DC ------------------------------------------------------------------------------------------------------ −2V to 15V
< 20ns ------------------------------------------------------------------------------------------------- −5V to 30V
UGATEx to GND ------------------------------------------------------------------------------------ (VPHASEx − 0.3V) to (VBOOTx + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------ (VPHASEx − 5V) to (VBOOTx + 5V)
LGATEx to GND ------------------------------------------------------------------------------------ (GND − 0.3V) to (VCC12x + 0.3V)
< 20ns ------------------------------------------------------------------------------------------------ (GND − 5V) to (VCC12x + 5V)
Power Dissipation, PD @ TA = 25°C
WQFN−40L 5x5 ------------------------------------------------------------------------------------Package Thermal Resistance (Note 2)
WQFN−40L 5x5, θJA ------------------------------------------------------------------------------WQFN−40L 5x5, θJC ------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------ESD Susceptibility (Note 3)
HBM (Human Body Mode) ----------------------------------------------------------------------MM (Machine Mode) -------------------------------------------------------------------------------
Recommended Operating Conditions
z
z
z
2.778W
36°C/W
6°C/W
150°C
260°C
−65°C to 150°C
2kV
200V
(Note 4)
Supply Input Voltage (VCC12A, VCC12B) --------------------------------------------------- 10.8V to 13.2V
Junction Temperature Range --------------------------------------------------------------------- −40°C to 125°C
Ambient Temperature Range --------------------------------------------------------------------- −40°C to 85°C
Electrical Characteristics
(VCC12x = 12V, TA = 25°C, unless otherwise specified)
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
--
6
--
mA
4.9
5
5.1
V
10
--
--
mA
Supply Input
Supply Current
ICC12
VCC5 Supply Voltage
VCC5
VCC5 Output Sourcing
IVCC5
Soft-Start Current
ISS1
VR_RDY = Low
68
80
92
μA
VID Change Current
ISS2
VR_RDY = High
135
160
185
μA
Transient Boost Sinking
Current
ITB
9
10
11
μA
VR_HOT Threshold Level
41
43
48
%VCC5
VR_HOT Hysteresis
--
7
--
%VCC5
VR_SHDN Threshold Level
30
32
34
%VCC5
ILOAD = 10mA
Thermal Management
To be continued
www.richtek.com
8
DS8869A-00 May 2011
RT8869A
Parameter
Symbol
Test Conditions
Min
Typ
Max
Unit
Power On Reset
VCC12 Rising Threshold
VCC12RTH
VCC12 Rising
9.2
9.6
10
V
VCC12 Hysteresis
VCC12HYS
VCC12 Falling
--
0.9
--
V
VCC5 Rising Threshold
VCC5RTH
VCC5 Rising
4.4
4.6
4.8
V
VCC5 Hysteresis
VCC5HYS
VCC5 Falling
--
0.4
--
V
VIH
0.8
--
--
VIL
--
--
0.4
270
300
330
kHz
50
--
1000
kHz
Enable Control
EN Input
Logic-High
Threshold
Logic-Low
Voltage
Oscillator
Switching Frequency
fOSC
RRT = 24kΩ, for 2 Phase Operation
Adjustable Frequency Range
V
Ramp Amplitude
(Note 5)
3.5
4
4.5
V
Maximum Duty
(Note 5)
61
66
71
%
1.55
1.6
1.65
V
RT Pin Voltage
VRT
Reference Voltage and DAC
1V to 1.6V
−0.5
--
0.5
%
0.8V to 1V
−8
--
8
mV
−10
--
10
mV
VIH
0.8
--
--
VIL
--
--
0.4
DAC Accuracy
0.5V to 0.8V
DAC Input
Logic-High
Threshold
Voltage (VID0 to
Logic-Low
VID7, VRSEL)
Error Amplifier
V
DC Gain
ADC
No Load
--
80
--
dB
Gain Bandwidth
GBW
CLOAD = 10pF
--
10
--
MHz
Slew Rate
SR
CLOAD = 10pF
10
--
--
V/μs
Output Voltage Range
VCOMP
0.5
3.6
V
Maximum Current
IEA_SLEW
300
--
--
μA
Maximum Current
IGMMAX
100
--
--
μA
Input Offset Voltage
VOSCS
−1
0
1
mV
Current Sense
IMAX Current Mirror Accuracy
IMAX / IAVG, 2 Phase Operation
368
400
432
%
Droop Current Mirror Accuracy
IDRP / I AVG, 2 Phase Operation
368
400
432
%
--
2
4
Ω
Gate Driver
--
1
2
Ω
RLGATEsr
VBOOT − VPHASE = 8V
250mA Source Current
VBOOT − VPHASE = 8V
250mA Sink Current
VLGATE = 8V
--
2
4
Ω
RLGATEsk
250mA Sink Current
--
0.8
1.6
Ω
UGATE Drive Source
RUGATEsr
UGATE Drive Sink
RUGATEsk
LGATE Drive Source
LGATE Drive Sink
To be continued
DS8869A-00 May 2011
www.richtek.com
9
RT8869A
Parameter
Protection
Total Current Protection
Threshold
Over Voltage Threshold
Under Voltage Threshold
Over Temperature
Protection Threshold
Over Temperature
Protection Hysteresis
Output Pin Capability
Symbol
Test Conditions
VIMA X
Min
Typ
Max
Unit
1.1
1.2
1.3
V
VOVP
VFB − V EAP
350
390
430
mV
VUVP
VFB − V EAP
−380
−300
−250
mV
(Note 5)
145
150
175
°C
--
20
--
°C
VR_HOT Sinking
Capability
VVR_HOT
IVR_HOT = 4mA
--
0.05
0.2
V
VR_RDY Sinking
Capability
VVR_RDY
IVR_RDY = 4mA
--
0.05
0.2
V
VR_SHDN Sinking
Capability
VVR_SHDN IVR_SHDN = 4mA
--
0.05
0.2
V
Note 1. Stresses listed as the above “Absolute Maximum Ratings” may cause permanent damage to the device. These are for
stress ratings. Functional operation of the device at these or any other conditions beyond those indicated in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended
periods may remain possibility to affect device reliability.
Note 2. θJA is measured in natural convection at TA = 25°C on a high-effective thermal conductivity four-layer test board of
JEDEC 51-7 thermal measurement standard. The measurement case position of θJC is on the exposed pad of the
package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.
Note 5. Guaranteed by Design.
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10
DS8869A-00 May 2011
RT8869A
Typical Operating Characteristics
Frequency vs. Temperature
308
5.01
306
5.00
Frequency (kHz)1
VCC5 Supply Voltage (V)
VCC5 Supply Voltage vs. Temperature
5.02
4.99
4.98
4.97
4.96
304
302
300
298
296
4.95
4.94
294
-50
-25
0
25
50
75
100
125
-50
-25
0
25
50
75
Temperature (°C)
Temperature (°C)
Inductor Current vs. Load Current
Power On from EN
100
125
30
Inductor Current (A) 1
25
20
VOUT
(1V/Div)
EN
(2V/Div)
Phase 1
Phase 2
15
VR_RDY
(1V/Div)
10
UGATE1
(20V/Div)
5
0
20
25
30
35
40
45
50
55
VIN = 12V, IOUT = 30A
Time (400μs/Div)
60
Load Current (A)
Power Off from EN
Dynamic Output Voltage Control
VOUT
(1V/Div)
EN
(2V/Div)
VOUT
(500mV/Div)
VID5
(2V/Div)
VR_RDY
(1V/Div)
UTATE1
(20V/Div)
UGATE1
(20V/Div)
UTATE2
(20V/Div)
VIN = 12V, IOUT = 30A
Time (40μs/Div)
DS8869A-00 May 2011
VIN = 12V, IOUT = 0A, VID = 1V to 1.2V
Time (20μs/Div)
www.richtek.com
11
RT8869A
Load Step Up
Dynamic Output Voltage Control
VOUT
(100mV/Div)
VOUT
(500mV/Div)
VID5
(2V/Div)
IOUT
(50A/Div)
UTATE1
(20V/Div)
UTATE1
(20V/Div)
UTATE2
(20V/Div)
UTATE2
(20V/Div)
VIN = 12V, IOUT = 0A, VID = 1.2V to 1V
VIN = 12V, RLL = 1mΩ
Time (20μs/Div)
Time (10μs/Div)
Load Step Down
OVP
VOUT
(100mV/Div)
VFB
(1V/Div)
IOUT
(50A/Div)
EAP
(1V/Div)
UTATE1
(20V/Div)
UTATE2
(20V/Div)
VIN = 12V, RLL = 1mΩ
Time (400μs/Div)
UVP
OCP
VOUT
(1V/Div)
IOUT
(50A/Div)
EAP
(1V/Div)
UTATE1
(20V/Div)
VDAC = 1V, VFB = 1V to 0.5V, IOUT = 0A
Time (400μs/Div)
www.richtek.com
12
VDAC = 1V, VFB = 1V to 1.5V, IOUT = 0A
Time (10μs/Div)
VFB
(1V/Div)
UTATE1
(20V/Div)
LTATE2
(20V/Div)
UTATE1
(20V/Div)
LTATE2
(20V/Div)
LTATE2
(20V/Div)
RIMAX = 36kΩ
Time (400μs/Div)
DS8869A-00 May 2011
RT8869A
Application Information
The RT8869A is an advanced 2/1 phase synchronous buck
controller with 2 integrated MOSFET drivers. It integrates
an 8-bit DAC that supports Intel VR11.x VID tables.
Supply Voltage and POR
+
9.6V
CMP
-
POR
VCC5
+
4.6V
CMP
POR : Power On Reset
-
Figure 1. Circuit for Power Ready Detection
DS8869A-00 May 2011
The switching frequency of the RT8869A is set by an
external resistor connected from the RT pin to GND. The
frequency follows the graph in Figure 2.
Switching Frequency (kHz)1
1200
There are three supply voltage pins built in the RT8869A:
VCC12A/VCC12B and VCC5. VCC12A/VCC12B are
power input pins that receive an external 12V voltage for
the embedded driver logic operation. VCC5 is a power
output pin which is the output of an internal 5V LDO
regulator. The 5V LDO regulator regulates VCC12A to
generate a 5V voltage source for internal gate logic and
external circuit biasing, e.g., OCP biasing. Since the VCC5
voltage is regulated, the variation of VCC5 (2%) will be
much smaller than Platform ATX + 5V (5% to 7%). The
maximum supply current of VCC5 is 10mA, which is
designed only for controller circuit biasing. The
recommended configuration of the RT8869A supply
voltages is as follows: Platform ATX + 12V to the VCC12A/
VCC12B pins, and decoupling capacitors on the VCC12A/
VCC12B and VCC5 pins (minimum 0.1μF). The
initialization of the RT8869A requires all the voltage on
VCC12A/VCC12B and VCC5 to be ready. Since VCC5 is
regulated internally from VCC12A, the VCC5 voltage will
be ready (>4.6V) after VCC12A reaches about 7V, so there
is no power sequence problem between VCC12A/VCC12B
and VCC5. After VCC5 > 4.6V and VCC12A/VCC12B >
9.6V, the internal power-on-reset (POR) signal goes high.
This POR signal indicates the power supply voltages are
all ready. When POR = high and EN = high, the RT8869A
initiates soft-start sequence. When POR = low, the
RT8869A will try to turn off both high side and low side
MOSFETs to prevent catastrophic failure.
VCC12A/
VCC12B
Switching Frequency
1000
800
600
400
200
0
0
20
40
60
80
Ω
RRT (kΩ)
Figure 2. Switching Frequency vs. RRT Resistance
Soft-Start
The VOUT soft-start slew rate is set by a capacitor from
the SS pin to FBRTN. Before power on reset (POR =
low), the SS pin is held at GND. After power on reset
(POR = high, EN = high) and an extra delay of 1600μs
(T1), the controller initiates ramping up. VOUT will always
trace VEAP during normal operation of the RT8869A, where
VEAP is the positive input of the error amplifier, which can
be described as VEAP = VDAC − VDROOP. (The definition of
VDROOP will be described later in the Load Line section).
The first ramping up duration of VOUT (T2) ramps VOUT to
VBOOT.
After VOUT ramps to VBOOT, the RT8869A stays in this
state for 800μs (T3), waiting for a valid VID code sent by
the CPU. After receiving the valid VID code, VOUT continues
ramping up or down to the voltage specified by VID code.
After VOUT ramps to VEAP = VDAC − VDROOP, the RT8869A
stays in this state for 1600μs (T5) and then asserts
VR_RDY = high. The ramping slew rate of T2 and T4 is
controlled by the external capacitor connected to SS pin.
The voltage of the SS pin will always be VEAP+0.7V,
where the mentioned 0.7V is the typical turn-on threshold
of an internal power switch. Before VR_RDY = high, the
slew rate of VEAP is limited to 80μA/CSS. When VR_RDY
www.richtek.com
13
RT8869A
= high, the slew rate of VEAP is limited to 160μA/CSS,
which is 2 times faster than the soft-start slew rate for
dynamic VID feature. The soft start waveform is shown in
Figure 2.
C2
C3
R3
R2
R1
VOUT
FB
Soft- Start Current (ISS)
is Limited and Variant
Soft-Start
Circuit
C1
COMP
EA
+
DAC
ISS
EAP
(Error AMP Positive Input)
CSS
IX
(Output Current Sensed Signal)
DAC
EAP
Figure 3. Circuit for Soft-Start and Voltage Control Loop
VCC12
The RT8869A can accept VID input changing while the
controller is running. This allows the output voltage (VOUT)
to change while the DC/DC converter is running and
supplying current to the load. This is commonly referred
to as VID On-The-Fly (OTF). A VID OTF can occur under
either light or heavy load conditions. The CPU changes
the VID inputs in multiple steps from the start code to the
finish code. This change can be positive or negative.
Theoretically, VOUT should follow VDAC which is a staircase
waveform, but in real application, the bandwidth of the
converter is finite while the staircase waveform needs
infinite bandwidth to follow. Thus, undesired VOUT overshoot
(when VDAC changes up) or undershoot (when VDAC
changes down) is often observed in this type of design.
However, for the RT8869A, as mentioned before in the
soft-start section, VDAC slew rate is limited by ISS2/CSS
RDROOP
VCC5
Dynamic VID
4.6V
9.6V
VEN
when VR_RDY = high. This slew rate limiter works as a
low-pass filter of VDAC and makes the bandwidth of VDAC
waveform finite. By smoothening the VDAC staircase
waveform, VOUT will no longer overshoot or undershoot.
On the other hand, CSS will increase the settling time of
VOUT during VID OTF. In most cases, a 5nF to 30nF
ceramic capacitor will be suitable for CSS.
SS
VOUT
VBOOT
VR_RDY
T1
T2
T3
T4
T5
Figure 4. Soft-Start Waveforms
T1 is the delay time from power on reset state to the
beginning of VOUT rising. T2 is the soft-start time from
VOUT = 0 to VOUT = VBOOT. T3 is the dwelling time for VOUT
= VBOOT. T4 is the soft-start time form VOUT = VBOOT to
VOUT = VDAC.
T5 is the VR_RDY delay time.
T1 = 1600μs + 0.7V x CSS /80μA.
T2 = VBOOT x CSS/80μA.
T3 ≈ 800μs.
T4 ≈ |VDAC − VBOOT| x CSS/80μA.
T5 ≈ 1600μs.
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14
Output Voltage Differential Sensing
The RT8869A uses a high gain low offset error amplifier
for differential sensing. The CPU voltage is sensed between
the FB and FBRTN pins. A resistor (RFB) connects FB pin
with the positive remote sense pin of the CPU (VCC_SNS),
while the FBRTN pin connects directly to the negative
remote sense pin of the CPU (VSS_SNS). The error amplifier
compares VEAP (= VDAC − VDROOP) with the VFB to regulate
the output voltage.
Transient Boost
In steady state, the voltage of VOUT is controlled to be
very close to VEAP, however a load step transient from
light load to heavy load could cause VOUT to be lower than
VEAP by several tens of mV. In conventional buck converter
design (without non-linear control) for CPU VR application,
due to limited control bandwidth, it is hard for the VR to
prevent VOUT undershoot during quick load transient from
light load to heavy load. Hence, the RT8869A builds in a
DS8869A-00 May 2011
RT8869A
state-of-the-art transient boost function which detects load
transient by monitoring VOUT. If VOUT suddenly DROOPs
below “VTB” the transient boost signal rises up and the
RT8869A turns on all high side MOSFETs and turns off all
low side MOSFETs. The voltage difference “VOUT − VTB”
is set by following equation :
IX =
IOUT × DCR
N × RCSN
Figure 6 is the current sense circuit.
PH1
PH2
VOUT − VTB = 10μA x RTB.
Sensitivity of the transient boost can be adjusted by varying
the values of CFB and RFB. Smaller RFB and/or larger CFB
will make transient boost easier to be triggered. Figure 5
shows the circuit and typical waveforms.
VOUT
VOUT
RTB
-
TB
Transient
Boost
+
L
DCR
L
DCR
RS
CS
IOUT
VCORE
COUT
RL
RS
RX
(Current Sense
Amplifier)
CSA
+
Load Line
Adjustment
NTC
CSP
CSN
IX
RCSN
Figure 6. Circuit for Current Sensing
CTB
10µA
Figure 5. (a) Transient Boost Circuit
IOUT
VOUT
Transient
Boost
Figure 5. (b) Typical Waveforms
Output Current Sensing
The RT8869A provides a low input offset current-sense
amplifier (CSA) to monitor the output current. The output
current of CSA (IX) is used for load line control, dynamic
phase control and over current protection. In this average
inductor current sensing topology, RS and CS must be set
according to the equation below :
Requ = R X //RNTC
L = RS × CS
DCR
R
N+ S
Requ
Where the constant N is a set maximum operation phase
number, not affected by the dynamic phase control
machine. Then, the output current of CSA will follow the
equation below :
DS8869A-00 May 2011
Load Line
The RT8869A utilizes inductor DCR current sense
technique for load line control function. The sensed output
current is proportionally mirrored from the IX signal to the
RDROOP resistor to establish the voltage of VDROOP. VDROOP
subtracted from VDAC generates VEAP. The voltage control
loop is shown in Figure 3. Because IX is a PTC (Positive
Temperature Coefficient) current, an NTC (Negative
Temperature Coefficient) resistor is needed to connect in
parallel with the capacitor CS. If the NTC resistor is properly
selected to compensate the temperature coefficient of IX,
the VDROOP voltage will be proportional to IOUT without
temperature effect. In the RT8869A, the positive input of
error amplifier is VEAP and VOUT will follow “VDAC −
VDROOP”. Thus, the output voltage which decreases
linearly with IOUT is obtained. The load line is defined as :
LL(Load Line) =
ΔVOUT ΔVDROOP DCR × RDROOP × 4
=
=
ΔIOUT
ΔIOUT
N × RCSN
Basically, the resistance of RDROOP sets the resistance of
the load line. The temperature coefficient of RDROOP
compensates the temperature effect of the load line.
Connecting VRSET pin to GND can enable load line
adjustment function. Meanwhile, the current IX is decreased
by 10mV/RCSN, and the minimum output current sensing
range is also reduced by 10mV/RCSN.
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15
RT8869A
Current Balance
Table 2. Dynamic Phase Control
The RT8869A sensed per phase current signal ISENx via
the voltages on the low side MOSFETs switch on
resistance (RDS(ON)) for current balance as shown in Figure
7, in which ISENx is defined as :
I
× RDSON + VDC
ISENx = PHASEx
RSENx
Where VDC is the offset voltage for the current balance
circuit.
In Figure 7, the phase current sense signals ISENx are
used to raise or lower the internal sawtooth waveforms
(RAMP [1] and RAMP [2]) which are compared with error
amplifier output (COMP) to generate a PWM signal. The
raised sawtooth waveform will decrease the PWM duty of
the corresponding phase current and the lowered sawtooth
waveform will increase the PWM duty of the corresponding
phase current. Eventually, current flowing through each
phase will be balanced.
Current
Balance
ISEN1
RSEN1
ISEN2
RSEN2
< VPS1
1
Forced 1
Forced 2
2
After setting the voltage at the PS1 pin, the RT8869A will
continuously compare VIMAX and VPS1 after POR. Once
the VIMAX enters each voltage state mentioned in Table 2,
the RT8869A will automatically change its operation phase
number. See Table 2 for the dynamic phase control
mechanism. For Example, if VPS1 = 0.3V, the RT8869A
will operate in 2 phase operation when VIMAX = 0.9V, and
1 phase operation when VIMAX = 0.1V. There are two states
mentioned in Table 2 that the RT8869A will be forced not
to change its operating phase number, and the VIMAX voltage
is meaningless for dynamic phase control circuit under
these conditions.
Over Current Protection (OCP)
PH2
Dynamic Phase Control Capability
The RT8869A has the ability to automatically control its
phase number according to the total load current. Connect
a resistor to ground at PS1 pin to set the 1-2 phase
transition threshold, VPS1.
The voltage at IMAX pin (VIMAX) represents total current
information, and the RT8869A will compare VIMAX with VPS1
to determine the number of operating phases. Figure 8
shows the typical connections of PS1 pin for setting the
dynamic phase control thresholds.
10µA
-
VIMAX
Phase Number
PH1
Figure 7. Circuit for Current Balance
PS1
VIMAX
VPS1 > 1.6V
VIMAX = Don’t Care
0.8V < VPS1 < 1.6V
VIMAX = Don’t Care
> VPS1
+
Dynamic
Phase
Control
When VIMAX is higher than 1.2V, the over current protection
is triggered with 100μs delay to prevent false trigger, and
the short circuit OCP level is designed at 1.6V with 10μs
delay. The controller will turn off all high side / low side
MOSFETs to protect CPU. Note that, the OCP level does
not change according to different operating phase numbers.
Over Voltage Protection (OVP)
The over voltage protection monitors the output voltage
via the FB pin. Once VFB exceeds “VEAP + 390mV”, OVP
is triggered and latched. The RT8869A will turn on low
side MOSFET and turn off high side MOSFET to protect
CPU.
Under Voltage Protection (UVP)
The under-voltage protection monitors the output voltage
via the FB pin. Once VFB is lower than “VEAP − 300mV”,
UVP is triggered and latched. The RT8869A will turn off
all high side / low side MOSFETs to protect CPU.
Figure 8. Circuit for Dynamic Phase Control and VR
Shutdown
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16
DS8869A-00 May 2011
RT8869A
Loop Compensation
The RT8869A is a voltage mode controller and requires
external compensation. To compensate a typical voltage
mode buck converter, there are two ordinary compensation
schemes, commonly known as type-II compensator and
type-III compensator. The choice of using type-II or typeIII compensator lies with the platform designers, and the
main concern deals with the position of the capacitor ESR
zero and mid-frequency to high frequency gain boost.
Typically, the ESR zero of output capacitor will tend to
stabilize the effect of output LC double poles. Hence, the
position of the output capacitor ESR zero in frequency
domain may influence the design of voltage loop
compensation. Figure 9 shows a typical control loop using
type-III compensator. Below is the compensator design
procedure.
VIN
OSC
The ESR zero is contributed by the ESR associated with
the output capacitance. Note that this requires the output
capacitor to have enough ESR to satisfy stability
requirements. The ESR zero of the output capacitor is
expressed as the following equation :
1
fESR =
2π × COUT × ESR
Driver
fZ1 fZ2
L
-
VOUT
fP2
fP3
Modulator Gain
Compensation Gain
Closed Loop Gain
Gain
PWM
Comparator
ΔVOSC
amplifier output). This transfer function is dominated by a
DC gain, a double pole, and an ESR zero as shown in
Figure 10. The DC gain of the modulator is the input
voltage (VIN) divided by the peak-to-peak oscillator voltage
VOSC. The output LC filter introduces a double pole, 40dB/
decade gain slope above its corner resonant frequency,
and a total phase lag of 180 degrees. The resonant
frequency of the LC filter is expressed as:
1
fLC =
2π × LOUT × COUT
Driver
+
COUT
ESR
ZFB
COMP
0
ZIN
EA
+
ZFB
C2
C1
C3
R2
VOUT
LOG
fLC
R3
fESR
fC
Frequency
Figure 10. Bode Plot of Loop Gain
R1
COMP
EA
+
ZIN
LOG
REF
FB
2) Design of the Compensator
REF
Figure 9. Compensation Circuit
1) Modulator Characteristic
The modulator consists of the PWM comparator and power
stage. The PWM comparator compares the error amplifier
output (COMP) with oscillator (OSC) sawtooth wave to
provide a pulse-width modulated (PWM) gate-driving
signal. The PWM wave is smoothed out by the output
filter, LOUT and COUT. The output voltage (VOUT) is sensed
and fed to the inverting input of the error amplifier. The
modulator transfer function is the small-signal transfer
function of VOUT/VCOMP (output voltage over the error
DS8869A-00 May 2011
A well-designed compensator regulates the output voltage
to the reference voltage VREF with fast transient response
and good stability. In order to achieve fast transient
response and accurate output regulation, an adequate
compensator design is necessary. The goal of the
compensation network is to provide adequate phase
margin (usually greater than 45°) and the highest bandwidth
(0dB crossing frequency, f C ) possible. It is also
recommended to manipulate the loop frequency response
such that its gain crosses over 0dB at a slope of −20dB/
dec. According to Figure 10, the location of poles and
zeros are :
fZ1 =
1
2π × R2 × C1
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17
RT8869A
For a given bandwidth, R2, fZ1, fZ2, fP2, fP3, then
1
C1 =
2π × R2 × fZ1
GMOD@BW
C3 =
2π × fC × R2
1
R1 =
2π × fZ2 × C3
1
R3 =
2π × fP2 × C3
1
C2 =
2π × fP3 × C1× R2 − 1
Thermal Monitoring (VR_HOT&VR_SHDN)
The RT8869A provides thermal monitoring function via
sensing the TM pin voltage, and which can set 2 thresholds
to indicate ambient temperatures through the voltage
divider R1 and RNTC. The voltage of TM is typically set to
be higher than 0.5 x VCC5 when ambient temperature is
lower than VR_HOT & VR_SHDN assertion target.
However, when ambient temperature rises, TM voltage will
fall, and the VR_HOT signal will be set to high if TM voltage
DROOPs below 0.43 x VCC5. Furthermore, if the
temperature continues to rise and the TM voltage is lower
than 0.32 x VCC5, the controller will shutdown and pull
the VR_SHDN signal to low. Accordingly, VR_HOT will be
reset when TM voltage rises above 0.5 x VCC5, but the
controller will not reboot once thermal shutdown occurs.
maximum power dissipation can be calculated by the
following formula :
PD(MAX) = (TJ(MAX) − TA) / θJA
where TJ(MAX) is the maximum junction temperature, TA is
the ambient temperature, and θJA is the junction to ambient
thermal resistance.
For recommended operating condition specifications of
the RT8869A, the maximum junction temperature is 125°C
and TA is the ambient temperature. The junction to ambient
thermal resistance, θJA, is layout dependent. For WQFN40L 5x5 packages, the thermal resistance, θJA, is 36°C/
W on a standard JEDEC 51-7 four-layer thermal test board.
The maximum power dissipation at TA = 25°C can be
calculated by the following formula :
PD(MAX) = (125°C − 25°C) / (36°C/W) = 2.778W for
WQFN-40L 5x5 package
The maximum power dissipation depends on the operating
ambient temperature for fixed T J(MAX) and thermal
resistance, θJA. For the RT8869A package, the derating
curve in Figure 11 allows the designer to see the effect of
rising ambient temperature on the maximum power
dissipation.
3.2
Maximum Power Dissipation (W)1
1
2π × R2 × C1
fP1 = 0
1
fP2 =
2π × C3 × R3
1
fP3 =
C1
×
C2 × R2
2π ×
C1+ C2
Generally, fZ1 and fZ2 are designed to cancel the double
pole of the modulator. Usually, place fZ1 at a fraction of
fLC, and place fZ2 at fLC. fP2 is usually placed at fESR to
cancel the ESR zero, and fP3 is placed below the switching
frequency to cancel high frequency noise.
fZ2 =
Four-Layer PCB
2.8
2.4
2.0
1.6
1.2
0.8
0.4
0.0
0
25
50
75
100
125
Ambient Temperature (°C)
Figure 11. Derating Curve for RT8869A Package
Thermal Considerations
For continuous operation, do not exceed absolute
maximum junction temperature. The maximum power
dissipation depends on the thermal resistance of the IC
package, PCB layout, rate of surrounding airflow, and
difference between junction and ambient temperature. The
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18
DS8869A-00 May 2011
RT8869A
Outline Dimension
D
SEE DETAIL A
D2
L
1
E2
E
e
b
1
1
2
2
DETAIL A
Pin #1 ID and Tie Bar Mark Options
A
A3
Note : The configuration of the Pin #1 identifier is optional,
but must be located within the zone indicated.
A1
Dimensions In Millimeters
Dimensions In Inches
Symbol
Min
Max
Min
Max
A
0.700
0.800
0.028
0.031
A1
0.000
0.050
0.000
0.002
A3
0.175
0.250
0.007
0.010
b
0.150
0.250
0.006
0.010
D
4.950
5.050
0.195
0.199
D2
3.250
3.500
0.128
0.138
E
4.950
5.050
0.195
0.199
E2
3.250
3.500
0.128
0.138
e
L
0.400
0.350
0.016
0.450
0.014
0.018
W-Type 40L QFN 5x5 Package
Richtek Technology Corporation
Richtek Technology Corporation
Headquarter
Taipei Office (Marketing)
5F, No. 20, Taiyuen Street, Chupei City
5F, No. 95, Minchiuan Road, Hsintien City
Hsinchu, Taiwan, R.O.C.
Taipei County, Taiwan, R.O.C.
Tel: (8863)5526789 Fax: (8863)5526611
Tel: (8862)86672399 Fax: (8862)86672377
Email: [email protected]
Information that is provided by Richtek Technology Corporation is believed to be accurate and reliable. Richtek reserves the right to make any change in circuit
design, specification or other related things if necessary without notice at any time. No third party intellectual property infringement of the applications should be
guaranteed by users when integrating Richtek products into any application. No legal responsibility for any said applications is assumed by Richtek.
DS8869A-00 May 2011
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19