® RT5006 Single Output LNB Power Supply Controller with I2C Interface General Description Features The RT5006 is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite Set-Top Box (STB) modules to the Low Noise Block (LNB) down converter in the antenna dish or to the multi-switch box. Wide Input Supply Voltage Range : 8V to 16V Output Current Up to 700mA Output Current Limit of 800mA with 5ms Timer LNB Voltages (16 Programmable Levels) ±4.5% High Accuracy of LNB Voltage for 0mA to 500mA Current Output Fault Latch for OTP, OCP, UVLO Built-in 22kHz Tone Generator One-Way DiSEqCTM Communication Four Methods of 22kHz Tone Generation, via I2C Data Bits and/or External Pin Adjustable Rising/Falling Time via External Capacitor 2-Wire Serial I2C Compatible Interface RoHS Compliant and Halogen Free The device consists of an independent current-mode Boost controller and a low dropout linear regulator and the circuitry required for 22kHz tone generation and integrates tone detection capability, to support full one-way DiSEqCTM communications. All the functions and the LNB output voltages (16 programmable levels) can be controlled via the I2C bus. The RT5006 has fault signal to serve as an interrupt for the processor when any condition turns off the LNB controller (over current, over temperature and under voltage lockout). The states of these flags to the faults can be thoroughly examined through the I2C registers. Applications LNB Power Supply and Control for Satellite Set-Top Box Analog and Digital Satellite Receivers/ Satellite TV, Satellite PC cards Simplified Application Circuit D1 L1 L2 VIN C4 C1 LX VIN VDD VA From MCU R2 November 2013 LNB Power LNB ADD R3 D2 EXTM SDA SCL IRQ PGND Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 D3 C5 RT5006 C3 R1 BOOST VREG C2 C7 D4 TCAP C6 GND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT5006 Ordering Information Pin Configurations RT5006 (TOP VIEW) LNB PGND LX VIN NC Package Type QW : WQFN-20L 4x4 (W-Type) (Exposed Pad-Option 2) QWA : WQFN-28L 5x5 (W-Type) 20 19 18 17 16 Note : Richtek products are : 15 2 14 4 13 12 21 5 11 6 RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. 7 8 9 Suitable for use in SnPb or Pb-free soldering processes. 10 WQFN-20L 4x4 LNB PGND LX VIN NC GND 3 NC GND NC SCL IRQ NC GND VREG SDA ADD 1 Marking Information NC NC Lead Plating System G : Green (Halogen Free and Pb Free) BOOST NC TCAP NC EXTM RT5006GQW 28 27 26 25 24 23 22 0E= : Product Code YMDNN : Date Code RT5006GQWA RT5006GQWA : Product Number NC 16 NC NC GND NC NC NC 15 NC 1 21 2 20 3 19 GND 4 18 5 17 6 29 7 YMDNN : Date Code 8 9 10 11 12 13 14 GND VREG SDA ADD SCL RT5006 GQWA YMDNN BOOST NC TCAP NC NC EXTM NC IRQ 0E=YM DNN WQFN-28L 5x5 Functional Pin Description Pin No. WQFN-20L 4x4 WQFN-28L 5x5 1 1 2, 4, 6, 13, 15, 18 2, 4, 5, 7, 13, 15 to 18, 20 to 24 3 3 5 6 Pin Name BOOST Track Supply Voltage to Linear Regulator. Connect to the converter output. Use a low ESR capacitor to ensure low voltage ripple. NC No Internal Connection. TCAP Capacitor (typ. 39nF) for Setting the Rise and Fall Time of the LNB Output. The capacitor should not be too small to avoid inrush current. EXTM External Modulation Input. Used for Tone generation control. TM Supply (by MCU) high level to apply a DiSEqC modulation envelope that modulates an internal tone and then transfers it symmetrically. It can also supply clock as an input for TM externally modulated DiSEqC tone signal that is transferred symmetrically onto output. Control the TGATE and TMODE status for tone generation option. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 Pin Function is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 Pin No. WQFN-20L 4x4 WQFN-28L 5x5 Pin Name 7, 14, 8, 19, GND 21 (Exposed Pad) 29 (Exposed Pad) 8 9 VREG 9 10 SDA 10 11 ADD 11 14 Pin Function Analog Ground. The Exposed pad should be soldered to a large PCB and connected to GND for maximum thermal dissipation. Internal Reference Output Typically. Connecting a capacitor (typ. 0.22F) from this pin to GND. Serial Interface Data Input/Output. Connect to VDD (typ. 3.3V to 5V) via a pull high resistor (typ. 4.7k). Connect to 2 2 MCU for I C communication. Support I C fast mode (typ. 400kHz) communication. Address Select. Supply by VA for different slave address 2 selection. Several devices can connect to the same I C bus by different VA and slave address. Slave address is 0x10 for VA = 0 to 0.7V, Slave address is 0x12 for VA = 1.3V to 1.7V, 0x14 for VA = 2.3V to 2.7V, 0x16 for VA = 3.3V to 5V. IRQ Interrupt Request (Active High). IRQ is an open drain output that connects to VDD (typ. 3.3V to 5V) via a pull high resistor (typ. 4.7k). The voltage level would be pulled low and latched when the faults (UVLO, OCP, TSD) occur. The 2 release condition is fault removing, as I C enables reading the status register. 12 12 SCL Serial Interface Clock Input. Connect to VDD (typ. 3.3V to 5V) via a pull high resistor (typ. 4.7k). Connect to MCU for 2 2 I C communication. Support I C fast mode (typ. 400kHz) communication. 17 25 VIN Power Supply Input. A capacitor (typ. 0.1F) should be connected to this pin. The operating voltage is 8V to 16V. Under Voltage Lockout (UVLO) is 7.35V. 18 26 LX Switch Node. Connect an inductor (typ. 33H) to input and a schottky diode to output. A RC snubber should be connected to this pin to reduce the voltage spike. 19 27 PGND Power Ground. LNB Linear Regulator Output Provides the LNB Power. It can supply a 13V to 18V, 700mA and transmit a 600mVpp Tone signal to LNB. It can diagnose the OCP, PNG, CAD and DIS 2 status by I C. 20 28 Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT5006 Function Block Diagram LX UVLO 5V LDO VR1 VFB1 VREG RF1 SDA SCL ADD IRQ Error Amp + - GND PGND PWM Controller RF2 16-step Voltage Setting 2 I C Compatible Interface OSC Clock Divider 22kHz Tone Circuit VD2 Linear Regulator Dynamic Dropout Control VUD VFB2 OCP2 Oscillator EXTM OCP1 VFB2 Latch Fault OCP OTP UVLO Un-Latch Fault DIS PNG LNB DAC VIN BOOST VD1 Bandage Reference OTP TCAP VR1 Operation The RT5006 integrates the functions of a current mode Boost converter and a linear regulator. Use the I2C to control the LNB voltage and the Boost converter is at least 800mV greater than LNB voltage. The Boost converter is the high efficiency PWM architecture with 352kHz operation frequency. The linear regulator has the capability to source current up to 700mA during continuous operation. All the loop compensation, current sensing, and slope compensation functions are provided internally. in the status register. The RT5006 latches all conditions in the status register until the completion of the data read. OCP This circuit is used for tone generation. Use the EXTM pin to control internal 22kHz oscillator output from LNB. Both the Boost converter and the linear regulator have independent current limit. In the Boost converter (OCP1), this is achieved through cycle-by-cycle internal current limit (typ. 3.8A). In the linear regulator (OCP2), when the linear regulator exceeds OCP more than 5ms, the LNB output will be disabled and the OCP bit of the status register will be set to high. Bandage Reference The RT5006 provides the slew rate control during either start-up, or output voltage is transitioning. The rising and falling times of the output voltage can be set by the external capacitor connected from TCAP pin to GND. Tone Circuit OTP When the junction temperature reaches the OTP threshold temperature (typically 150°C), the Boost converter and the linear regulator are immediately disabled. UVLO User can communicate with RT5006 by microcontroller via the two wires I2C. The two lines SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-high resistor (typically 4.7kΩ). The UVLO circuit compares the VIN with the UVLO threshold (7.7V rising typically) to ensure that the input voltage is high enough for reliable operation. The 350mV (typ.) hysteresis prevents supply transients from causing a shutdown. Fault PWM Controller The IRQ output becomes logic low when the RT5006 recognizes a latch fault condition. Latch fault conditions are indicated by the TSD, UVLO and OCP, and are latched The loop compensation, current sensing, and slope compensation functions are provided internally. I2C Interface Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 Absolute Maximum Ratings (Note 1) Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- −0.3V to 28V Output Voltage LNB, LX and BOOST Pins -------------------------------------------------------------------------- −0.3V to 28V Other Pins ------------------------------------------------------------------------------------------------------------------ −0.3V to 6V Power Dissipation, PD @ TA = 25°C WQFN-20L 4x4 -----------------------------------------------------------------------------------------------------------WQFN-28L 5x5 -----------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-20L 4x4, θJA ------------------------------------------------------------------------------------------------------WQFN-20L 4x4, θJC -----------------------------------------------------------------------------------------------------WQFN-28L 5x5, θJA ------------------------------------------------------------------------------------------------------WQFN-28L 5x5, θJC -----------------------------------------------------------------------------------------------------Junction Temperature ----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) ------------------------------------------------------------------------------Storage Temperature Range -------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ---------------------------------------------------------------------------------------------MM (Machine Model) ----------------------------------------------------------------------------------------------------- Recommended Operating Conditions 3.46W 3.57W 28.8°C/W 7.2°C/W 28°C/W 7°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage (Note 5) ---------------------------------------------------------------------------------------- 8V to 16V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, VLOAD, ILOAD is the output of LNB power, TA = 25°C, unless otherwise specified) Parameter LNB Output Accuracy, Load and Line Regulation Supply Current Symbol Test Conditions Min Typ Max Unit 4.5 -- 4.5 % ERR Relative to selected V LNB target level, ILOAD = 0 to 500mA IIN_OFF ENB bit = 0, LNB output disabled -- -- 10 IIN_ON ENB bit = 1, LNB output enabled, ILOAD = 0mA -- -- 19 -- 300 600 m 320 352 384 kHz -- 3.8 -- A 600 800 1000 mV -- 5 -- V Boost Switch On Resistance RDSON Switching Frequency fSW Switch Current Limit ILIMSW VIN = 10V, VBOOST = 20.4V Linear Regulator Voltage Drop VDROP VBOOST V LNB , no tone signal, ILOAD = 500mA VREG output VREG ICHG VTCAP = 0V 12.5 10 7.5 IDISCHG VTCAP = 4V 7.5 10 12.5 Ripple and Noise on LNB Output VRIP_PP 20MHz Bandwidth Limit -- 30 -- Load Regulation VOUT_LOAD VLNB = 13.709V, ILNB = 50mA to 450mA -- 38 76 VLNB = 19.042V, ILNB = 50mA to 450mA -- 45 90 TCAP Pin Current Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 mA A mVPP mV is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT5006 Parameter Line Regulation Symbol VOUT_LINE Test Conditions Min Typ Max VIN = 10V to 16V, VLNB = 13.709V, ILNB = 50mA VIN = 10V to 16V, VLNB = 19.042V, ILNB = 50mA 10 -- 10 Unit mV 10 -- 10 700 850 1000 mA -- 5 -- ms 7.4 7.7 8 V VUVLO_HYS -- 350 -- mV TOTP -- 150 -- °C -- 30 -- °C 88 91 94 % -- 4 -- % 106 109 112 % -- 4 -- % 20 22 24 kHz Protection Output Over Current Limit Output Over Current Disable Time VIN Turn On Threshold VIN Under Voltage Lockout Hysteresis OTP Threshold OTP Hysteresis ILIM_LNB tDIS VIN_TH VIN Rising TOTPHYS With respect to VLNB setting; VLNB low, PNG set to 1 Power Not Good (Low) PNGLOSET Power Not Good (Low) Hysteresis PNGLO_HYS With respect to VLNB setting Power Not Good (High) PNGHISET With respect to VLNB setting; VLNB high, PNG set to 1 Power Not Good (High) Hysteresis PNGHIHYS With respect to VLNB setting Tone Tone Frequency fTONE Tone Amplitude, Peak to Peak VTONE_PP Tone Duty Cycle DCTONE ILOAD = 0 to 500mA, CLOAD = 750nF 550 720 900 mV ILOAD = 0 to 500mA, CLOAD = 750nF 40 50 60 % Tone Rise Time tRTONE ILOAD = 0 to 500mA, CLOAD = 750nF 5 10 15 s Tone Fall Time tFTONE ILOAD = 0 to 500mA, CLOAD = 750nF 5 10 15 s VEXTM_H 2 -- -- VEXTM_L -- -- 0.6 IEXTMLKG -- -- 5 I C Compatible Interface High Level Logic Input (SDA, SCL) Low Level VSCL_H 2 -- -- VSCL_L -- -- 0.6 Logic Input Hysteresis VI2CIHYS Logic Input Current Logic Output Voltage SDA and IRQ Logic Output Leakage SDA and IRQ SCL Clock Frequency II2CI EXTM Logic Input EXTM Input Leakage V A 2 -- 150 -- mV 10 ±1 10 A VT2COUT_L -- -- 0.4 V IT2CLKG -- -- 10 A fCLK -- -- 400 kHz Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 V is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 Parameter Min Typ Max Unit -- -- 250 ns tBUF 1.3 -- -- s Hold Time Start Condition Setup Time for Start Condition tHD_STA 0.6 -- -- s tSU_STA 0.6 -- -- s SCL Low Time tLOW 1.3 -- -- s SCL High Time THIGH 0.6 -- -- s Data Setup Time tSU_DAT 100 -- -- ns Data Hold Time tHD_DAT 0 -- 900 ns Setup Time for Stop Condition tSU_STO 0.6 -- -- s Address1 0 -- 0.7 V Address2 1.3 -- 1.7 V Address3 2.3 -- 2.7 V Address4 3.3 -- 5 V Output Fall Time Bus Free Time Between Stop/Start Symbol Test Conditions tFL2COUT I2C Address Setting ADD Voltage 0001, 000 ADD Voltage 0001, 001 ADD Voltage 0001, 010 ADD Voltage 0001, 011 for Address for Address for Address for Address Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Operation at VIN = 16V may be limited by power loss in the linear regulator. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT5006 Typical Application Circuit VIN L2 1µH D1 SS14 L1 33µH C4 100µF C1 100µF LX VIN C2 0.1µF VDD BOOST VREG C3 0.22µF C5 1µF RT5006 VA ADD LNB D2 SS14 R1 R3 R2 4.7k 4.7k 4.7k EXTM SDA SCL IRQ PGND From MCU D3 SS14 TCAP C7 0.1µF D4 SMDJ20A LNB Power C6 39nF GND Note : (1) C5 and L2 are used for filter to reduce the voltage ripple into BOOST pin. (2) D2, D3, D4, are used for surge protection. The clamping voltage of D4 is 30V, the break down voltage must be higher than 24V as recommended. (3) IRQ, SDA and SCL are connected to VDD via a pull high resistor (typ. 4.7kΩ). (4) EXTM, SDA, SCL and IRQ are connected to microcontroller directly. (5) Use a low ESR capacitor for C4 (typ. 100μF) to reduce the voltage ripple. (6) The capacitor C6 of TCAP should not be less than 39nF to avoid inrush current. (7) The capacitor C3 should not be less than 0.1μF for the power stability. Timing Diagram I2C Interface Timing Diagram SDA VIH(MIN) VIL(MAX) tSU_DAT tLOW tHD_DAT tSU_STO tBUF tHIGH SCL VIH(MIN) VIL(MAX) tHD_STA S tF Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 P S is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 Typical Operating Characteristics Boost + LNB Efficiency vs. Load Current 100 95 95 90 90 Efficiency (%) Efficiency (%) Boost Efficiency vs. Load Current 100 85 80 75 70 85 80 75 70 65 65 VIN = 12V, VBOOST = 13.3V 60 0.05 0.18 0.31 0.44 0.57 VIN = 12V, VBOOST = 13.3V, VLNB = 12.7V 60 0.05 0.7 0.18 0.31 Load Current (A) Tone Frequency vs. Temperature 0.7 Tone Amplitude vs. Temperature 700 22.8 600 22.6 Tone Amplitude (mV) Tone Frequency (kHz)1 0.57 Load Current (A) 23.0 22.4 22.2 22.0 21.8 21.6 21.4 500 400 300 200 100 21.2 VIN = 12V, TGATE = TMODE = 1, EXTM = 5V VIN = 12V, TGATE = TMODE = 1, EXTM = 5V 21.0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) Tone Duty Cycle vs. Temperature Under Voltage Lockout vs. Temperature 60 8.00 50 7.80 UVLO Voltage (V) Tone Duty Cycle(%) 0.44 40 30 20 UVLO_H 7.60 7.40 7.20 UVLO_L 7.00 10 VIN = 12V, TGATE = TMODE = 1, EXTM = 5V 6.80 0 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT5006 VLNB Transition from 13V to 18V LNB Rising Time VLNB (5V/Div) VIN = 12V, ENB = 1, VSEL = [0,0,0,0], TCAP = 39nF VLNB (5V/Div) VIN = 12V, ENB = 1 VSEL = [0,0,0,1] to [1,0,0,0], TCAP = 39nF Time (1ms/Div) Time (2.5ms/Div) VLNB Transition from 18V to 13V 22kHz Tone VLNB_ac (200mV/Div) VLNB (5V/Div) VIN = 12V, ENB = 1 VSEL = [1,0,0,0] to [0,0,0,1], TCAP = 39nF VIN = 12V, TGATE = TMODE = 1, EXTM = 5V Time (2.5ms/Div) Time (25μs/Div) Option 1 Internal Tone Control by TGATE VLNB 13V (0.2V/Div) EXTM (5V/Div) SDA (5V/Div) VLNB_ac (200mV/Div) VIN = 12V, TMODE = 1, 2 TGATE is Switching, TGATE is Controlled by I C Time (100μs/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 Option 2 Internal Tone Control by EXTM EXTM (2V/Div) VIN = 12V, TGATE = TMODE = 1 Time (100μs/Div) is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 Option 3 External Tone Control by TGATE Option 4 External Tone Control by TGATE VLNB 13V (0.2V/Div) VLNB 13V (0.2V/Div) EXTM (5V/Div) SDA (5V/Div) VIN = 12V, TMODE = 0, TGATE is Controlled by I2C Time (100μs/Div) Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 EXTM (2V/Div) VIN = 12V, TGATE = 1, TMODE = 0 Time (100μs/Div) is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT5006 Application Information Boost Converter/Linear Regulator The RT5006 integrates a current mode Boost converter and linear regulator. Use the I2C to control the LNB voltage and the Boost converter track is at least greater 800mV than LNB voltage. The Boost converter is the high efficiency PWM architecture with 352kHz operation frequency. The linear regulator has the capability to source current up to 700mA during continuous operation. All the loop compensation, current sensing, and slope compensation functions are provided internally. where η is the efficiency of the converter, IIN(MAX) is the maximum input current, and IRIPPLE is the inductor ripple current. The input peak current can then be obtained by adding the maximum input current with half of the inductor ripple current as shown in the following equation : IPEAK = 1.2 x IIN(MAX) Note that the saturated current of the inductor must be greater than IPEAK. The inductance can eventually be determined according to the following equation : VIN VOUT VIN 2 The RT5006 has current limiting on the Boost converter and the LNB output to protect the IC against short circuits. The internal MOSFET will turn off when the LX current is higher than 3.8A cycle-by-cycle. If the LNB output in heavy load, output current is limited to typically 800mA , IRQ latch to low and the LNB output will be disabled if the over current condition is more than 5ms. The RT5006 must be enabled by reading the status register to release the IRQ. Input Capacitor Selection The input capacitor reduces voltage spikes from the input supply and minimizes noise injection to the converter. A 100μF capacitance is sufficient for most applications. Nevertheless, a higher or lower value may be used depending on the noise level from the input supply and the input current to the converter. Note that the voltage rating of the input capacitor must be greater than the maximum input voltage. Inductor Selection The inductance depends on the maximum input current. As a general rule, the inductor ripple current range is 20% to 40% of the maximum input current. If 40% is selected as an example, the inductor ripple current can be calculated according to the following equations : IIN(MAX) VOUT IOUT(MAX) VIN L 0.4 VOUT IOUT(MAX) fOSC 2 where fOSC is the switching frequency. For better system performance, a shielded inductor is preferred to avoid EMI problems. Boost Output Capacitor Selection The RT5006 Boost regulator is internally compensated and relies on the inductor and output capacitor value for overall loop stability. The output capacitor is in the 50μF to 200μF range with a low ESR, as strongly recommended. The voltage rating on this capacitor should be in the 25V to 35V range since it is connected to the Boost VOUT rail. The output ripple voltage is an important index for estimating chip performance. This portion consists of two parts. One is the product of the inductor current with the ESR of the output capacitor, while the other part is formed by the charging and discharging process of the output capacitor. As shown in Figure 1, ΔVOUT1 can be evaluated based on the ideal energy equalization. According to the definition of Q, the Q value can be calculated as the following equation : Q= 1 1 1 IIN IL IOUT IIN IL IOUT 2 2 2 VIN 1 = COUT VOUT1 VOUT fOSC IRIPPLE 0.4 IIN(MAX) Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 where fOSC is the switching frequency and ΔIL is the inductor ripple current. Bring COUT to the left side to estimate the value of ΔVOUT1 according to the following equation : D IOUT VOUT1 COUT fOSC where D is the duty cycle and η is the Boost converter efficiency. Finally, take ESR into consideration, the overall output ripple voltage can be determined by the following equation : D IOUT VOUT1 IIN ESR + COUT fOSC ΔIL Input Current Inductor Current Output Current Time (1-D)TS Output Ripple Voltage (ac) Time ΔVOUT1 Figure 1. The Output Ripple Voltage without the Contribution of ESR Schottky Diode Selection Schottky diodes are chosen for their low forward voltage drop and fast switching speed. However, when making a selection, important parameters such as power dissipation, reverse voltage rating, and pulsating peak current should all be taken into consideration. A suitable Schottky diode's reverse voltage rating must be greater than the maximum output voltage and its average current rating must exceed the average output current. The chosen diode should also have a sufficiently low leakage current level, since it increases with temperature. Under Voltage Lockout (UVLO) The UVLO circuit compares the input voltage at VIN with the UVLO threshold (7.7V Rising typ.) to ensure that the input voltage is high enough for reliable operation. The 350mV (typ.) hysteresis prevents supply transients from causing a shutdown. Once the input voltage exceeds the UVLO rising threshold, start-up begins. When the input voltage falls below the UVLO falling threshold, all IC internal functions will be turned off by the controller. Over-Current Protection The RT5006 features an over-current protection function to prevent chip damage from high peak currents. Both the Boost converter and the linear regulator have independent current limit. In the Boost converter, this is achieved through cycle-by-cycle internal current limit. During the ON-period, the chip senses the inductor current that is flowing into the LX pin. The internal N-MOSFET will be turned off if the peak inductor current reaches the currentlimit value of 3.8A (typ.).When the linear regulator exceeds 800mA (typ.) more than 5ms, the LNB output will be disabled and the OCP bit of the status register will be set to high. The IRQ voltage will be set to low and latched. OCP bit non-affected by current limit occurs through the Boost converter. During this period of time, if the current limit condition disappears, the OCP bit will be cleared and the part restarts. If the part is still in current limit after this time period, the linear regulator and Boost converter will automatically disable to prevent the part from overheating. Short Circuit Protection If the LNB output is shorted to ground, and more than 5ms, the RT5006 will be disabled. Slew Rate Control The RT5006 provides the slew rate control during either start-up, or output voltage is transitioning. The output voltage rise and fall times can be set by the capacitor connected from TCAP pin to GND. The value of CTCAP can be calculated using the following formula : CTCAP = 6 ITCAP / SR SR = VLNB / t Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT5006 Where CTCAP is the TCAP value in nF, ITCAP is the TCAP pin charge/discharge current (typ. 10μA), SR is the LNB output voltage slew rate, ΔVLNB is the differential transition voltage and the Δt is the required transition time in ms. The typical value of CTCAP is 39nF for most applications. However, it is necessary to increase the value of CTCAP to avoid inrush current of the LNB output but too large value will probably cause the voltage transition specifications to be exceeded. The output linear regulator provides approximately 40mA of pull-down capability to ensure that the output volts are ramped from 20V to 13V in a reasonable amount of time. Over Temperature Protection When the junction temperature reaches the critical temperature (typ. 150°C), the Boost converter and the linear regulator are immediately disabled, the TSD bit set to high and the IRQ voltage goes low. When the junction temperature cools down to a lower temperature threshold I2C Write/Read Writing and reading to the RT5006 register is shown in Figure 2. The slave address is controlled by ADD voltage, please refer to the Table 1. In writing mode, the slave address is proportional to ADD voltage. It requires transmission of total 18 bits-two 8-bit bytes of data and an acknowledge bit after each byte. The slave device (RT5006) pulls down the SDA for an acknowledgement (ACK) if the slave address is correct. Otherwise, the 9th bit of SDA keeps to high, it is a not-acknowledge (NACK) condition. In reading mode, the R/W bit of the slave address is 1, RT5006 outputs data after receiving the right slave address. The master (microcontroller) should make an ACK to slave for continuous transmission. The RT5006 stops the data outputs if the master feedbacks a NACK before stop condition. I2C Write Timing of LNB Output Control Slave Address S 0 0 0 1 R/W 0 A1 A0 0 A RT5006 Control Data 1 A RT5006 Control Data 2 ACK from Slave ACK from Slave specified, this bit will be cleared and the RT5006 will be allowed to restart by normal start operation. A P ACK from Slave I2C Read Timing of LNB Status Slave Address S 0 0 0 1 R/W 0 A1 A0 1 A RT5006 Status Data 1 ACK from Slave ACK from Master A A RT5006 Status Data 2 P NACK from Master Figure 2. I2C Write and Read Timing Control Table 1. RT5006 ADD Voltage and Slave Address RT5006 Slave Address Address1 [A1,A0] = [0,0] Write 0x10 Read 0x11 Min 0 Typ -- Max 0.7 Address2 Address3 Address4 0x12 0x14 0x16 0x13 0x15 0x17 1.3 2.3 3.3 ---- 1.7 2.7 5 [A1,A0] = [0,1] [A1,A0] = [1,0] [A1,A0] = [1,1] Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 and OCP bits, and are latched in the status register (see the Table 2). Interrupt Request (IRQ) The RT5006 provides an interrupt pin (IRQ), which is an open-drain, active high output. This output may be connected to a common IRQ line with a suitable external pull-up resistor and can be used with other I2C compatible devices to request attention from the master controller. The DIS, PNG status bits do not cause an interrupt. All these bits are continually updated, apart from the DIS bit, which changes when the LNB is either disabled, intentionally or due to a fault, or is enabled. When the master recognizes an interrupt, reference the Figure3, it addresses all slaves connected to the interrupt line in sequence, and then reads the status register to determine which device is requesting attention. The RT5006 latches all conditions in the status register until the completion of the data read. The IRQ output becomes logic low when the RT5006 recognizes a fault condition, or at power on, when the main supply, VIN, and the internal logic supply, VREG, reach the correct operating conditions. It is only reset to inactive when the I2C master addresses the RT5006 with the read/write bit set (reading mode enabled), shown as below. Fault conditions are indicated by the TSD, UVLO Slave ID S VDD 0 0 0 1 R/W 0 A1 A0 1 ACK from Slave IRQ A RT5006 Status Data A P NACK from Master GND Fault Event Reload Status Register Figure 3. IRQ Latch and Release Control Table 2. Fault Detect Function and IRQ Status Bit 0 1 Bit Name DIS 2 OCP 3 Description LNB output disable Not used Over current Latched or Not Reset Condition No LNB enabled and no latched faults Yes IRQ Status None None LNB output current less than OCP 2 current and I C Read the status register. Not used IRQ set low None 4 5 PNG Power not good Not used No LNB Voltage within setting range 6 TSD Thermal shutdown Yes Junction temperature less than TSD limit IRQ set low 2 and I C read the status register. 7 UVLO VIN under voltage Yes VIN voltage higher than the UVLO 2 voltage and I C read the status register. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 None None IRQ set low is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT5006 LNB Output Voltage and Control Registers The RT5006 control register 1 is shown in Table 3. VSEL [3:0] provides voltage control on the LNB output. This function provides the necessary levels for all the common standards. The function of line-adding compensation is enabled if the cable line has voltage drop. The voltage levels are defined in Table 4. Bit 3 VSEL3 switches between the low level and high level output voltages on the LNB output. The low level, set to 0, is 12.709V nominal and the high level, set to 1, is 18.042V nominal. ENB bit controls the LNB output. When set to 1, the LNB output is switched on. When set to 0, the LNB output is disabled. Bit 6 and Bit 7 are the address register setting bits. Set to [0,0] for control register 1. Table 3. RT5006 Control Register 1 Control Address (I1, I0) : (0, 0) Bit 3:0 Bit Name VSEL <3 : 0> 4 RT5006 Control Register 1 Default 0000 Access W 1 W 5 ENB 0 W 7:6 I1, I0 00 W Table 4. Output Voltage Amplitude Selection Description 16 steps output voltage selection Not used Enables or disables the LNB output 0 : Disable LNB output 1 : Enable LNB output Address bit I1, I0 = (0, 0) Bit 6 to7, I0, I1 : Control register address. Register setting VSEL3 0 VSEL2 0 VSEL1 0 VSEL0 0 LNB (V) 12.709 bits. Set to [1,0] for control register 2. 0 0 0 1 13.042 Tone Generation Control Registers 0 0 1 0 13.375 0 0 0 1 1 0 1 0 13.709 14.042 0 1 0 1 14.375 0 0 1 1 1 1 0 1 14.709 15.042 1 0 0 0 18.042 1 1 0 0 0 1 1 0 18.375 18.709 1 0 1 1 19.042 1 1 0 0 19.375 1 1 1 1 0 1 1 0 19.709 20.042 The RT5006 control register 2 is shown in Table 5. That provides tone output control for control purpose. TMODE and TGATE are used for tone output control. The RT5006 provides four options for tone generation, please refer to the Figure 4. TMODE selects between the external 22kHz logic signal, select 0, on EXTM pin or the internal 22kHz oscillator, select 1, to control the tone generation on the LNB output. TGATE bit allows either the internal or external 22kHz tone signals to be gated. The selected tone is off when TGATE set to 0 and the selected tone is on when set to 1. Bit 6 and bit 7 are the control register setting bits. Set to [1,0] for control register 2. 1 1 1 1 20.375 Bit 0 to3, VSEL <3:0> : These four bits provide 16-level LNB output voltage. Bit 5, ENB : Enable the LNB output. When set to 1 the LNB output is switched on. When set to 0, the LNB output is disabled. Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 Option 1 : Use internal tone, gated by the TGATE bit. EXTM Option 3 : Use external tone, gated by the TGATE bit. EXTM TMODE TMODE TGATE TGATE Tone Tone LNB (V) (LNB) Ref (LNB) Ref Option 2 : Use internal tone, gated by the EXTM pin. EXTM LNB (V) Option 4 : Use external tone. EXTM TMODE TMODE TGATE TGATE Tone Tone LNB (V) (LNB) Ref (LNB) Ref LNB (V) Figure 4. Tone Generation Options Table 5. RT5006 Control Register 2 Control Address (I1, I0) : (1, 0) Bit Bit Name Default 0 TMODE 0 1 TGATE 0 5:2 7:6 I1, I0 00 00 Bit 0, TMODE : This bit controls the output tone origin. Following the internal 22kHz tone generator or the external signal on EXTM pin. Bit 1, TGATE : This bit is used for enable/disable tone output. Bit 6 to 7, I0, I1 : Control register address. Status Registers The RT5006 status register table is shown in Table 6 and Table 7. The status register is used for diagnosing the main fault conditions : Over Current Protection (OCP), Under Voltage Lockout (UVLO) and Thermal Shutdown (TSD). When these three faults occur, the LNB output is disabled and the bit is latched to 1 until the RT5006 is read by the master, assuming the fault has been resolved. The status register is updated on the rising edge of the 9th clock pulse in the data read sequence. Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 RT5006 Control Register 2 Access Description 0 : External tone W 1 : Internal tone 0 : Tone gated off W 1 : Tone gated on W Not used W Address bit I1, I0 = (1, 0) The Disable bit (DIS) is used to indicate the current condition of the LNB output. It is set when either a fault occurs or if the LNB is disabled intentionally by the I2CTM master. This bit isn't latched if the LNB is commanded on again. The OCP bit is set to 1 if the LNB output detects an over current condition (typ. 800mA) over 5ms. Where the OCP bit is reset in all cases, allowing the master to enable the LNB output. If this bit has been set, please check that the output loading is short or too heavy before re-enable again. The Power Not Good (PNG) is used for over voltage (typ. 109%) or under voltage (typ. 91%) detection of the LNB output voltage. If the LNB disabled or the output voltage is abnormal, PNG reports a logic 1 until the LNB output is enabled. The TSD bit indicates 1 when the RT5006 has detected is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT5006 the over-temperature condition. The disable bit, DIS, will also be set. If the condition is no longer present, then the TSD bit will be reset, allowing the master to enable the LNB output if required. If the condition is still present, then the TSD bit will remain at 1. The UVLO bit, 1 is indicated that the RT5006 has detected that the input supply is below the minimum level. The disable bit, DIS, will also be set and the RT5006 will not re-enable the output until the condition is no longer present, then the UVLO bit will be reset allowing the master to reenable the LNB output if required. If the condition is still present, then the UVLO bit will remain at 1. The Cable Disconnected (CAD) is used for detecting the cable between LNB and the LNB head is disconnected or not. If the CADT bit of the control register 2 is set to 1, LNB linear regulator is disabled and the VSEL set to highest level an 1mA current source is applied between the BOOST and LNB output. If the BOOST voltage rises above 21V, CAD will be set to 1, reset if the LNB volts drop below typically 19.95V. The DIS, PNG bits are reset without an I2CTM read sequence. The power on sequence of the master in a fault condition is to check the fault status by reading the Status registers then removing the fault condition until the status bit is reset. The fault may be detected either by continuously polling status registers or by responding to an interrupt request (IRQ). Table 6. RT5006 Status Register 1 Bit Status Address Bit Name 0 1 2 DIS OCP 3 4 5 6 7 PNG TSD UVLO Default RT5006 Status Register 1 Access Description 0 0 0 R R R LNB output disable Not used Over current 0 0 0 0 0 R R R R R Not used Power not good Not used Thermal shutdown VIN under voltage Table 7. RT5006 Status Register 2 Status Address Bit 7:0 Bit Name RT5006 Status Register 2 Default Access 0 R Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 Description Not used is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 I2C Interface Acknowledge User can communicate with RT5006 by microcontroller via the two wires I2C. The two lines SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-high resistor (typ. 4.7kΩ). The level of logic “0” and logic “1” is defined in the “Electrical Specifications” table. The output stages of RT5006 will have an open drain/ open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100kbps in the standard mode or up to 400kbps in the fast mode. One clock pulse is generated for each data bit transferred. The master puts a resistive high level on the SDA line during the acknowledge clock pulse. The slave has to pulllow the SDA line during the acknowledge clock pulse. This behavior is called acknowledge, ACK. If the slave doesn't pull the SDA low, that is NACK (NotAcknowledged) behavior. The RT5006 will not generate the ACK if the input voltage is under UVLO. SCL 1 SDA SCL S P START Condition STOP Condition Data Validity The high or low level of the data line can only change when the SCL is low level. The data on the SDA line must be stable during the high period of the clock. SDA SCL Change of Data Allowed Byte Format Every part the SDA and SCL line must be 9 bits long. There are 8 bits for a data byte and the 9 th is the acknowledged bit. The number of bytes that can be transmitted per transfer is unrestricted. Each byte is transferred with the most significant bit first (MSB). Copyright © 2013 Richtek Technology Corporation. All rights reserved. November 2013 9 MSB START condition is the SDA line level transition from high to low while SCL is high level. The STOP is the SDA line level transition from low to high while SCL is high level. Each command has to begin with a START condition and finish by a STOP condition. DS5006-00 8 SDA START and STOP Conditions Data Line Stable Data Valid 2 START Acknowledge from Slave Transmitted Data (I2C Bus Write Mode) In writing mode, the master (microcontroller) transmits the 8 bits data (MSB transmitted first) after START condition. Then the slave (RT5006) has to feedback an ACK condition during the acknowledge clock pulse if the data receiving is OK. The master transmitter can generate the STOP condition to end the transfer. Received Data (I2C Bus Read Mode) In reading mode, after the user transmits the slave address and data address, the master changes to RT5006 and the slave becomes the microcontroller. As for the following master generated clock bits, the RT5006 issues a byte on the SDA data bus line (MSB transmitted first) and the ACK condition is generated by microcontroller. After receiving the last data, the microcontroller enables a NACK condition to issue the data from master and the STOP condition to end the transfer. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT5006 where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-20L 4x4 package, the thermal resistance, θJA, is 28.8°C/W on a standard JEDEC 51-7 four-layer thermal test board. For WQFN-28L 5x5 package, the thermal resistance, θJA, is 28°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula: Layout Considerations For high frequency switching power supplies, the PCB layout is important to get good regulation, high efficiency and stability. The following descriptions are the guidelines for better PCB layout. For good regulation, place the power components as close as possible. The traces should be wide and short enough especially for the high current loop. Minimize the size of the LX node and keep it wide and shorter. The exposed pad of the chip should be connected to a strong ground plane for maximum thermal consideration. PD(MAX) = (125°C − 25°C) / (28.8°C/W) = 3.46W for WQFN-20L 4x4 package P D(MAX) = (125°C − 25°C) / (28°C/W) = 3.57W for WQFN-28L 5x5 package The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 5 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 4.0 Four-Layer PCB 3.6 WQFN-28L 5x5 3.2 2.8 2.4 2.0 WQFN-20L 4x4 1.6 1.2 0.8 0.4 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 5. Derating Curve of Maximum Power Dissipation Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 20 is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 The inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. LX node copper area should be minimized for reducing EMI Place the power components as close as possible. The traces should be wide and short especially for the high-current loop. The C4 should be connected directly from the output schottky diode to ground . VIN PGND C1 C5 D2 should be placed as closed as possible to RT5006 for surge protection. C4 C2 AGND L1 D1 D3 L2 LNB C7 D2 VOUT LNB D4 D3 and D4 should be placed as closed as possible to VOUT for surge protection. 19 18 17 16 PGND LX VIN NC NC 15 GND 14 NC 13 NC SCL 12 EXTM IRQ 11 1 BOOST 2 NC 3 TCAP 4 5 ADD The exposed pad of the chip should be connected to analog ground plane for thermal consideration. VDD 10 SDA 9 VREG 8 7 6 GND GND NC AGND 20 C2, C3, C5 and C6 should be placed as closed as possible to RT5006 for good filter. C6 LNB AGND R1 C3 R2 VA AGND From MCU R3 Separate power ground (PGND) and analog ground (AGND). Connect AGND and PGND islands at a single end. Make sure there are no other connections between these separate ground planes. The PGND should be wide and short enough to connect ground plane. Figure 6. PCB Layout Guide for WQFN-20L 4x4 Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 21 RT5006 The inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. LX node copper area should be minimized for reducing EMI Place the power components as close as possible. The traces should be wide and short especially for the high-current loop. The C4 should be connected directly from the output schottky diode to ground . VIN PGND C1 C5 D2 should be placed as closed as possible to RT5006 for surge protection. C4 L2 C2 AGND L1 D1 D3 LNB LNB C7 D2 D4 28 27 26 25 24 23 22 LNB PGND LX VIN NC NC NC AGND D3 and D4 should be placed as closed as possible to VOUT for surge protection. NC 21 1 BOOST 2 NC 3 TCAP 4 NC 5 NC NC 17 6 EXTM NC 16 7 NC NC 15 NC 20 C6 NC 18 VREG SDA ADD SCL NC IRQ 9 10 11 12 13 14 GND GND AGND GND 19 8 C2, C3 and C6 should be placed as closed as possible to RT5005 for good filter. VOUT The exposed pad of the chip should be connected to analog ground plane for thermal consideration. VDD C3 R1 VA R2 AGND From MCU R3 Separate power ground (PGND) and analog ground (AGND). Connect AGND and PGND islands at a single end. Make sure there are no other connections between these separate ground planes. The PGND should be wide and short enough to connect ground plane. Figure 7. PCB Layout Guide for WQFN-28L 5x5 Copyright © 2013 Richtek Technology Corporation. All rights reserved. www.richtek.com 22 is a registered trademark of Richtek Technology Corporation. DS5006-00 November 2013 RT5006 Outline Dimension 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol D2 E2 Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.150 0.300 0.006 0.012 D 3.900 4.100 0.154 0.161 Option 1 2.650 2.750 0.104 0.108 Option 2 2.100 2.200 0.083 0.087 E 3.900 4.100 0.154 0.161 Option 1 2.650 2.750 0.104 0.108 Option 2 2.100 2.200 0.083 0.087 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 20L QFN 4x4 Package Copyright © 2013 Richtek Technology Corporation. All rights reserved. DS5006-00 November 2013 is a registered trademark of Richtek Technology Corporation. www.richtek.com 23 RT5006 D2 D SEE DETAIL A L 1 E E2 e A3 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options b A A1 1 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 4.950 5.050 0.195 0.199 D2 3.000 3.300 0.118 0.130 E 4.950 5.050 0.195 0.199 E2 3.000 3.300 0.118 0.130 e L 0.500 0.450 0.020 0.650 0.018 0.026 W-Type 28L QFN 5x5 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 24 DS5006-00 November 2013