® RT5007 Single Output LNB Power Supply Controller with I2C Interface General Description Features The RT5007 is a highly integrated voltage regulator and interface IC, specifically designed for supplying power and control signals from advanced satellite Set-Top Box (STB) modules to the Low Noise Block (LNB) down converter in the antenna dish or to the multi-switch box. Wide Input Supply Voltage Range : 8V to 16V Wide Output Supply Current Range : 0mA to 500mA Adjustable Output Current Limit Up to 500mA with 5ms Timer LNB Voltages (8 Programmable Levels) ±4.5% High Accuracy of LNB Voltage for 0mA to 500mA Current Output Fault Latch for OTP, OCP, UVLO Built-in 22kHz Tone Generator One-Way DiSEqCTM Communication Adjustable Rising/Falling Time via External Capacitor 2-Wire Serial I2C Compatible Interface RoHS Compliant and Halogen Free The device consists of an independent current-mode Boost controller and low a dropout linear regulator and the circuitry required for 22kHz tone generation to support one-way DiSEqCTM communications. All the functions and the LNB output voltages (8 programmable levels) can be controlled via the I2C bus. The RT5007 has fault signal to serve as an interrupt for the processor when any condition turns off the LNB controller (over current, over temperature and under voltage lockout). The states of these flags to the faults can be thoroughly examined through the I2C registers. Applications LNB Power Supply and Control for Satellite Set-Top Box Analog and Digital Satellite Receivers/ Satellite TV, Satellite PC cards Simplified Application Circuit L1 D1 L2 VIN C4 C1 LX VIN C2 C3 From MCU R2 C5 R4 ADD LNB Power LNB R3 D2 EXTM SDA SCL IRQ PGND Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 D3 ISET RT5007 VA VDD R1 BOOST VREG C7 D4 TCAP C6 GND is a registered trademark of Richtek Technology Corporation. www.richtek.com 1 RT5007 Ordering Information Pin Configurations RT5007 (TOP VIEW) BOOST PGND LX VIN Package Type QW : WQFN-16L 3x3 (W-Type) Lead Plating System G : Green (Halogen Free and Pb Free) Richtek products are : RoHS compliant and compatible with the current requirements of IPC/JEDEC J-STD-020. Suitable for use in SnPb or Pb-free soldering processes. Marking Information 1 12 2 11 GND 3 10 17 4 9 5 6 7 GND VREG ISET TCAP 8 SCL SDA ADD EXTM Note : 16 15 14 13 NC NC LNB IRQ WQFN-16L 3x3 0M= : Product Code 0M=YM DNN YMDNN : Date Code Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 2 is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 Functional Pin Description Pin No. Pin Name Pin Function 1, 2 NC No Internal Connection. 3 LNB Linear Regulator Output Provides the LNB Power. It can supply a 13V to 18V, 500mA and transmit a 600mVpp Tone signal to LNB. It can diagnose the OCP, 2 PNG, CAD and DIS status by I C. 4 IRQ 5 SCL Interrupt Request (Active High). IRQ is an open drain output that connects to VDD (typ. 3.3V to 5V) via a pull high resistor (typ. 4.7k). The voltage level would be pulled low and latched when the faults (UVLO, OCP, TSD) occur. 2 The release condition is fault removing, as I C enables reading the status register. Serial Interface Clock Input. Connect to VDD (typ. 3.3V to 5V) via a pull high 2 2 resistor (typ. 4.7k). Connect to MCU for I C communication. Support I C fast mode (typ. 400kHz) communication. SDA Serial Interface Data Input/Output. Connect to VDD (typ. 3.3V to 5V) via a pull 2 2 high resistor (typ. 4.7k). Connect to MCU for I C communication. Support I C fast mode (typ. 400kHz) communication. ADD Address Select. Supply by VA for different slave address selection. Several 2 devices can connect to the same I C bus by different VA and slave address. Slave address is 0x10 for VA = 0 to 0.7V, Slave address is 0x12 for VA = 1.3V to 1.7V, 0x14 for VA = 2.3V to 2.7V, 0x16 for VA = 3.3V to 5V. 8 EXTM External Modulation Input. Used for Tone generation control. Supply (by MCU) TM high level to apply a DiSEqC modulation envelope that modulates an internal tone and then transfers it symmetrically. 9 TCAP Capacitor (typ. 39nF) for Setting the Rise and Fall Time of the LNB Output. The capacitor should not be too small to avoid inrush current. 10 ISET Output Current Limit set Via External Resister. Minimum is 50k for the 500mA OCP setting. 11 VREG Internal Reference Output Typically. Connecting a capacitor (typ. 0.22F) from this pin to GND. 12, 17 (Exposed Pad) GND 13 VIN 14 LX 15 PGND 16 BOOST 6 7 Analog Ground. The Exposed pad should be soldered to a large PCB and connected to GND for maximum thermal dissipation. Power Supply Input. A capacitor (typ. 0.1F) should be connected to this pin. The operating voltage is 8V to 16V. Under Voltage Lockout (UVLO) is 7.35V. Switch Node. Connect an inductor (typ. 33H) to input and a schottky diode to output. A RC snubber should be connected to this pin to reduce the voltage spike. Power Ground. Track Supply Voltage to Linear Regulator. Connect to the converter output. Use a low ESR capacitor to ensure low voltage ripple. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 3 RT5007 Function Block Diagram LX UVLO 5V LDO VR1 VFB1 VREG RF1 SDA SCL ADD IRQ Error Amp + - 8-step Voltage Setting 2 I C Compatible Interface OSC 22kHz Tone Circuit VD2 VFB2 Linear Regulator Dynamic Dropout Control VUD VFB2 ISET Clock Divider EXTM GND PGND PWM Controller RF2 Oscillator ISET OCP1 OCP2 Latch Fault OCP OTP UVLO Un-Latch Fault DIS PNG LNB DAC VIN BOOST VD1 Bandage Reference TCAP VR1 Operation The RT5007 integrates the functions of a current mode Boost converter and a linear regulator. Use the I2C to control the LNB voltage and the Boost converter is at least 800mV greater than LNB voltage. The Boost converter is the high efficiency PWM architecture with 352kHz operation frequency. The linear regulator has the capability to source current up to 500mA during continuous operation. All the loop compensation, current sensing, and slope compensation functions are provided internally. are indicated by the TSD, UVLO and OCP, and are latched in the status register. The RT5007 latches all conditions in the status register until the completion of the data read. OCP Tone Circuit Both the Boost converter and the linear regulator have independent current limit. In the Boost converter (OCP1), this is achieved through cycle-by-cycle internal current limit (typ. 3.8A). In the linear regulator (OCP2), when the linear regulator exceeds OCP more than 5ms, the LNB output will be disabled and the OCP bit of the status register will be set to high. This circuit is used for tone generation. Use the EXTM pin to control internal 22kHz oscillator output from LNB. I2C UVLO User can communicate with RT5007 by microcontroller via the two wires I2C. The two lines SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-high resistor (typically 4.7kΩ). The UVLO circuit compares the VIN with the UVLO threshold (7.7V rising typically) to ensure that the input voltage is high enough for reliable operation. The 350mV (typ.) hysteresis prevents supply transients from causing a shutdown. Bandage Reference The RT5007 provides the slew rate control during either start-up, or output voltage is transitioning. The rising and falling times of the output voltage can be set by the external capacitor connected from TCAP pin to GND. OTP When the junction temperature reaches the critical temperature (typically 150°C), the Boost converter and the linear regulator are immediately disabled. Fault The IRQ output becomes logic low when the RT5007 recognizes a latch fault condition. Latch fault conditions Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 4 PWM Controller The loop compensation, current sensing, and slope compensation functions are provided internally. is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 Absolute Maximum Ratings (Note 1) Supply Input Voltage, VIN ----------------------------------------------------------------------------------------------- −0.3V to 28V Output Voltage LNB, LX, BOOST ------------------------------------------------------------------------------------- −0.3V to 28V Other Pins ------------------------------------------------------------------------------------------------------------------ −0.3V to 6V Power Dissipation, PD @ TA = 25°C WQFN-16L 3x3 ------------------------------------------------------------------------------------------------------------Package Thermal Resistance (Note 2) WQFN-16L 3x3, θJA -------------------------------------------------------------------------------------------------------WQFN-16L 3x3, θJC ------------------------------------------------------------------------------------------------------Junction Temperature -----------------------------------------------------------------------------------------------------Lead Temperature (Soldering, 10 sec.) -------------------------------------------------------------------------------Storage Temperature Range --------------------------------------------------------------------------------------------ESD Susceptibility (Note 3) HBM (Human Body Model) ----------------------------------------------------------------------------------------------MM (Machine Model) ------------------------------------------------------------------------------------------------------ Recommended Operating Conditions 3.33W 30°C/W 7.5°C/W 150°C 260°C −65°C to 150°C 2kV 200V (Note 4) Supply Input Voltage (Note 5) ---------------------------------------------------------------------------------------- 8V to 16V Junction Temperature Range -------------------------------------------------------------------------------------------- −40°C to 125°C Ambient Temperature Range -------------------------------------------------------------------------------------------- −40°C to 85°C Electrical Characteristics (VIN = 12V, VLOAD, ILOAD is the output of LNB power, TA = 25°C, unless otherwise specified) Parameter LNB Output Accuracy, Load and Line Regulation Supply Current Symbol Min Typ Max Unit 4.5 -- 4.5 % ERR Relative to selected VLNB target level, ILOAD = 0 to 500mA IIN_OFF ENB bit = 0, LNB output disabled -- -- 10 IIN_ON ENB bit = 1, LNB output enabled, ILOAD = 0mA -- -- 19 -- 300 600 m 320 352 384 kHz -- 3.8 -- A 600 800 1000 mV -- 5 -- V Boost Switch On Resistance Switching Frequency fSW Switch Current Limit ILIMSW Linear Regulator Voltage Drop VREG output Test Conditions RDSON VDROP VIN = 10V, VBOOST = 19.84V VBOOST VLNB, no tone signal, ILOAD = 500mA VREG ICHG VTCAP = 0V 12.5 10 7.5 IDISCHG VTCAP = 4V 7.5 10 12.5 Ripple and Noise on LNB Output VRIP_PP 20MHz Bandwidth Limit -- 30 -- Load Regulation VOUT_LOAD VLNB = 13.667V, ILNB = 50mA to 450mA -- 38 76 VLNB = 19.667V, ILNB = 50mA to 450mA -- 45 90 ISET Voltage VISET -- 1 -- TCAP Pin Current Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 mA A mVPP mV V is a registered trademark of Richtek Technology Corporation. www.richtek.com 5 RT5007 Parameter Line Regulation Symbol VOUT_LINE Test Conditions Min Typ Max Unit VIN = 10V to 16V, VLNB = 13.667V, ILNB = 50mA VIN = 10V to 16V, VLNB = 19.667V, ILNB = 50mA 10 -- 10 10 -- 10 RISET = 50k 450 550 650 mA -- 5 -- ms 7.4 7.7 8 V mV Protection Output Over Current Limit ILIM_LNB Output Over Current Disable Time VIN Turn On Threshold VIN Under Voltage Lockout Hysteresis OTP Threshold VUVLO_HYS -- 350 -- mV TOTP -- 150 -- °C OTP Hysteresis TOTPHYS -- 30 -- °C 88 91 94 % -- 4 -- % 106 109 112 % -- 4 -- % 20 22 24 kHz tDIS VIN_TH VIN Rising With respect to VLNB setting; VLNB low, PNG set to 1 Power Not Good (Low) PNGLOSET Power Not Good (Low) Hysteresis PNGLO_HYS With respect to VLNB setting Power Not Good (High) PNGHISET With respect to VLNB setting; VLNB high, PNG set to 1 Power Not Good (High) Hysteresis PNGHIHYS With respect to VLNB setting Tone Tone Frequency fTONE Tone Amplitude, Peak to Peak VTONE_PP ILOAD = 0 to 500mA, CLOAD = 750nF 550 720 900 mV Tone Duty Cycle DCTONE ILOAD = 0 to 500mA, CLOAD = 750nF 40 50 60 % Tone Rise Time tRTONE ILOAD = 0 to 500mA, CLOAD = 750nF 5 10 15 s Tone Fall Time tFTONE ILOAD = 0 to 500mA, CLOAD = 750nF 5 10 15 s VEXTM_H 2 -- -- VEXTM_L -- -- 0.6 IEXTMLKG -- -- 5 High Level VSCL_H 2 -- -- Low Level VSCL_L -- -- 0.6 Logic Input Hysteresis VI2CIHYS -- 150 -- mV Logic Input Current Logic Output Voltage SDA and IRQ Logic Output Leakage SDA and IRQ SCL Clock Frequency II2CI 10 ±1 10 A VT2COUT_L -- -- 0.4 V IT2CLKG -- -- 10 A fCLK -- -- 400 kHz EXTM Logic Input EXTM Input Leakage V A 2 I C Compatible Interface Logic Input (SDA, SCL) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 6 V is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 Parameter Symbol Test Conditions Min Typ Max Unit -- -- 250 ns tBUF 1.3 -- -- s tHD_STA 0.6 -- -- s tSU_STA 0.6 -- -- s Output Fall Time Bus Free Time Between Stop/Start Hold Time Start Condition Setup Time for Start Condition SCL Low Time tFL2COUT tLOW 1.3 -- -- s SCL High Time tHIGH 0.6 -- -- s Data Setup Time tSU_DAT 100 -- -- ns Data Hold Time Setup Time for Stop Condition tHD_DAT 0 -- 900 ns tSU_STO 0.6 -- -- s Address1 0 -- 0.7 V Address2 1.3 -- 1.7 V Address3 2.3 -- 2.7 V Address4 3.3 -- 5 V 2 I C Address Setting ADD Voltage for Address 0001, 000 ADD Voltage for Address 0001, 001 ADD Voltage for Address 0001, 010 ADD Voltage for Address 0001, 011 Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is measured at the exposed pad of the package. Note 3. Devices are ESD sensitive. Handling precaution is recommended. Note 4. The device is not guaranteed to function outside its operating conditions. Note 5. Operation at VIN = 16V may be limited by power loss in the linear regulator. Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 7 RT5007 Typical Application Circuit D1 SS14 L1 33µH VIN C1 100µF C2 0.1µF C4 100µF 14 LX C3 0.22µF VA VDD L2 1µH 13 VIN 11 VREG BOOST 16 10 ISET RT5007 7 ADD D3 SS14 C5 1µF R4 50k LNB Power LNB 3 R2 R1 R3 4.7k 4.7k 4.7k 8 6 5 4 From MCU EXTM SDA SCL IRQ PGND 15 C7 0.1µF D2 SS14 TCAP D4 SMDJ20A 9 C6 39nF GND 12, 17 (Exposed Pad) Note : (1) C5 and L2 are used for filter to reduce the voltage ripple into BOOST pin. (2) D2, D3, D4, are used for surge protection. The clamping voltage of D4 is 30V, the break down voltage must higher be than 24V as recommended. (3) IRQ, SDA and SCL are connected to VDD via a pull high resistor (typ. 4.7kΩ). (4) EXTM, SDA, SCL and IRQ are connected to microcontroller directly. (5) Use a low ESR capacitor for C4 (typ. 100μF) to reduce the voltage ripple. (6) The capacitor C6 of TCAP should not be less than 39nF to avoid inrush current. (7) The capacitor C3 should not be less than 0.1μF for the power stability. (8) The Over Current Protection Resister R4 shouldn't be less than 50kΩ. Timing Diagram I2C Interface Timing Diagram SDA VIH(MIN) VIL(MAX) tSU_DAT tLOW tHD_DAT tSU_STO tBUF tHIGH SCL VIH(MIN) VIL(MAX) tHD_STA S tF Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 8 P S is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 Typical Operating Characteristics Boost + LNB Efficiency vs. Load Current 100 95 95 90 90 Efficiency (%) Efficiency (%) Boost Efficiency vs. Load Current 100 85 80 75 70 85 80 75 70 65 65 VIN = 12V, VBOOST = 13.3V 60 0.05 0.18 0.31 0.44 0.57 VIN = 12V, VBOOST = 13.3V, VLNB = 12.7V 60 0.05 0.7 0.18 0.31 Load Current (A) Tone Frequency vs. Temperature 0.7 Tone Amplitude vs. Temperature 700 22.8 600 22.6 Tone Amplitude (mV) Tone Frequency (kHz)1 0.57 Load Current (A) 23.0 22.4 22.2 22.0 21.8 21.6 21.4 500 400 300 200 100 21.2 VIN = 12V, TGATE = TMODE = 1, EXTM = 5V VIN = 12V, TGATE = TMODE = 1, EXTM = 5V 21.0 0 -50 -25 0 25 50 75 100 125 -50 -25 0 Temperature (°C) 25 50 75 100 125 Temperature (°C) Tone Duty Cycle vs. Temperature Under Voltage Lockout vs. Temperature 60 8.0 50 7.8 UVLO Voltage (V) Tone Duty Cycle(%) 0.44 40 30 20 UVLO_H 7.6 7.4 7.2 UVLO_L 7.0 10 VIN = 12V, TGATE = TMODE = 1, EXTM = 5V 6.8 0 -50 -25 0 25 50 75 100 Temperature (°C) Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 125 -50 -25 0 25 50 75 100 125 Temperature (°C) is a registered trademark of Richtek Technology Corporation. www.richtek.com 9 RT5007 VLNB Transition from 13V to 18V LNB Rising Time VLNB (5V/Div) VIN = 12V, ENB = 1, VSEL = [0,0,0,0], TCAP = 39nF VLNB (5V/Div) VIN = 12V, ENB = 1 VSEL = [0,0,0,1] to [1,0,0,0], TCAP = 39nF Time (1ms/Div) Time (2.5ms/Div) VLNB Transition from 18V to 13V 22kHz Tone VLNB_ac (200mV/Div) VLNB (5V/Div) VIN = 12V, ENB = 1 VSEL = [1,0,0,0] to [0,0,0,1], TCAP = 39nF Time (2.5ms/Div) VIN = 12V, TGATE = TMODE = 1, EXTM = 5V Time (25μs/Div) Tone Control by EXTM VLNB_ac (200mV/Div) EXTM (2V/Div) VIN = 12V, TGATE = TMODE = 1 Time (100μs/Div) Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 10 is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 Application Information Boost Converter/Linear Regulator The RT5007 integrates a current mode Boost converter and linear regulator. Use the I2C to control the LNB voltage current. The input peak current can then be obtained by adding the maximum input current with half of the inductor ripple current as shown in the following equation : and the Boost converter track is at least greater 800mV than LNB voltage. The Boost converter is the high efficiency PWM architecture with 352kHz operation frequency. The linear regulator has the capability to source current up to 500mA during continuous operation. All the loop compensation, current sensing, and slope compensation functions are provided internally. IPEAK = 1.2 x IIN(MAX) The RT5007 has current limiting on the Boost converter and the LNB output to protect the IC against short circuits. The internal MOSFET will turn off when the LX current is higher than 3.8A cycle-by-cycle. If the LNB output in heavy load, output current is limited to typically 500mA, IRQ latch to low and the LNB output will be disabled if the over current condition is more than 5ms. The RT5007 must be enabled by reading the status register to release the IRQ. where fOSC is the switching frequency. For better system performance, a shielded inductor is preferred to avoid EMI problems. Input Capacitor Selection The input capacitor reduces voltage spikes from the input supply and minimizes noise injection to the converter. A 100μF capacitance is sufficient for most applications. Nevertheless, a higher or lower value may be used depending on the noise level from the input supply and the input current to the converter. Note that the voltage rating of the input capacitor must be greater than the maximum input voltage. Inductor Selection The inductance depends on the maximum input current. As a general rule, the inductor ripple current range is 20% to 40% of the maximum input current. If 40% is selected as an example, the inductor ripple current can be calculated according to the following equations : IIN(MAX) VOUT IOUT(MAX) VIN IRIPPLE 0.4 IIN(MAX) where η is the efficiency of the converter, IIN(MAX) is the maximum input current, and IRIPPLE is the inductor ripple Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 Note that the saturated current of the inductor must be greater than IPEAK. The inductance can eventually be determined according to the following equation : VIN VOUT VIN 2 L 0.4 VOUT IOUT(MAX) fOSC 2 Boost Output Capacitor Selection The RT5007 Boost regulator is internally compensated and relies on the inductor and output capacitor value for overall loop stability. The output capacitor is in the 50μF to 200μF range with a low ESR, as strongly recommended. The voltage rating on this capacitor should be in the 25V to 35V range since it is connected to the Boost VOUT rail. The output ripple voltage is an important index for estimating chip performance. This portion consists of two parts. One is the product of the inductor current with the ESR of the output capacitor, while the other part is formed by the charging and discharging process of the output capacitor. As shown in Figure 1, ΔVOUT1 can be evaluated based on the ideal energy equalization. According to the definition of Q, the Q value can be calculated as the following equation : Q= 1 1 1 IIN IL IOUT IIN IL IOUT 2 2 2 VIN 1 = COUT VOUT1 VOUT fOSC where fOSC is the switching frequency and ΔIL is the inductor ripple current. Bring COUT to the left side to estimate the value of ΔVOUT1 according to the following equation : D IOUT VOUT1 COUT fOSC is a registered trademark of Richtek Technology Corporation. www.richtek.com 11 RT5007 where D is the duty cycle and η is the Boost converter efficiency. Finally, take ESR into consideration, the overall output ripple voltage can be determined by the following equation : D IOUT VOUT1 IIN ESR + COUT fOSC ΔIL Input Current Inductor Current Output Current Time (1-D)TS Output Ripple Voltage (ac) voltage falls below the UVLO falling threshold, all IC internal functions will be turned off by the controller. Over Current Protection The RT5007 features an over-current protection function to prevent chip damage from high peak currents. Both the Boost converter and the LNB output have independent current limit. In the Boost converter, this is achieved through cycle-by-cycle internal current limit. During the ON-period, the chip senses the inductor current that is flowing into the LX pin. The internal N-MOSFET will be turned off if the peak inductor current reaches the current limit value of 3.8A(typ.). The LNB output current limit can be set by the resistor from the ISET pin. This current can be set from 300mA to 500mA by setting the resistor from 75kΩ to 50kΩ. The typical LNB output current limit can be set by the following equation: IOCP (mA) = 23000 / RISET (kΩ) Time ΔVOUT1 Figure 1. The Output Ripple Voltage without the Contribution of ESR Schottky Diode Selection Schottky diodes are chosen for their low forward voltage drop and fast switching speed. However, when making a selection, important parameters such as power dissipation, reverse voltage rating, and pulsating peak current should all be taken into consideration. A suitable Schottky diode's reverse voltage rating must be greater than the maximum output voltage and its average current rating must exceed the average output current. The chosen diode should also have a sufficiently low leakage current level, since it increases with temperature. When the output current exceeds the current limit for 5ms, the LNB output will be disabled and the OCP bit of the status register will be set to high. The minimum value of the RISET is 50kΩ. Be aware that the ISET pin can not be inadvertently grounded. Short Circuit Protection If the LNB output is shorted to ground, and more than 5ms, the RT5007 will be disabled. Slew Rate Control The RT5007 provides the slew rate control during either start-up, or output voltage is transitioning. The output voltage rise and fall times can be set by the capacitor connected from TCAP pin to GND. The value of CTCAP can be calculated using the following formula : CTCAP = 6 ITCAP / SR Under Voltage Lockout (UVLO) SR = VLNB / t The UVLO circuit compares the input voltage at VIN with the UVLO threshold (7.7V Rising typ.) to ensure that the input voltage is high enough for reliable operation. The 350mV (typ.) hysteresis prevents supply transients from causing a shutdown. Once the input voltage exceeds the UVLO rising threshold, start-up begins. When the input Where CTCAP is the TCAP value in nF, ITCAP is the TCAP pin charge/discharge current (typ. 10μA), SR is the LNB output voltage slew rate, ΔVLNB is the differential transition voltage and the Δt is the required transition time in ms. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 12 The typical value of CTCAP is 39nF for most applications. However, it is necessary to increase the value of CTCAP to is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 I2C Write/Read avoid inrush current of the LNB output but too large value will probably cause the voltage transition specifications to be exceeded. The output linear regulator provides approximately 40mA of pull-down capability to ensure that the output volts are ramped from 20V to 13V in a reasonable amount of time. Writing and reading to the RT5007 register is shown in Figure 2. The slave address is controlled by ADD voltage, please refer to the Table 1. In writing mode, the slave address is proportional to ADD voltage. It requires transmission of total three bytes, slave address, control register address and control data. Address of RT5007 is 0x00. In reading mode, the R/W bit of the slave address is 1, RT5007 outputs data after receiving the right slave address and status register address (0x00). The master (microcontroller) should make an ACK to slave for continuous transmission. The RT5007 stops the data outputs if the master feedbacks a NACK before stop condition. Over Temperature Protection When the junction temperature reaches the critical temperature (typ. 150°C), the Boost converter and the linear regulator are immediately disabled, the TSD bit set to high and the IRQ voltage goes low. When the junction temperature cools down to a lower temperature threshold specified, this bit will be cleared and the RT5007 will be allowed to restart by normal start operation. I2C Write Timing of LNB Output Control Slave ID S 0 0 0 1 Control Register Address R/W 0 A1 A0 0 A 0 0 0 0 ACK from Slave 0 0 0 0 A RT5007 Control Data ACK from Slave A P ACK from Slave I2C Read Timing of LNB Status Slave ID S 0 0 0 1 Status Register Address R/W 0 A1 A0 0 A 0 0 0 ACK from Slave Slave ID S 0 0 0 1 0 0 0 0 0 A P A P ACK from Slave R/W 0 A1 A0 1 A RT5007 Status Data ACK from Slave ACK from Slave Figure 2. I2C Write and Read Timing Control Table 1. RT5007 ADD Voltage and Slave Address RT5007 Slave Address Write Read Min Typ Max Address1 Address2 Address3 [A1,A0] = [0,0] [A1,A0] = [0,1] [A1,A0] = [1,0] 0x10 0x12 0x14 0x11 0x13 0x15 0 1.3 2.3 ---- 0.7 1.7 2.7 Address4 [A1,A0] = [1,1] 0x16 0x17 3.3 -- 5 Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 13 RT5007 and OCP bits, and are latched in the status register (see the Table 2). Interrupt Request (IRQ) The RT5007 provides an interrupt pin (IRQ), which is an open-drain, active high output. This output may be connected to a common IRQ line with a suitable external pull-up resistor and can be used with other I2C compatible devices to request attention from the master controller. The DIS, PNG status bits do not cause an interrupt. All these bits are continually updated, apart from the DIS bit, which changes when the LNB is either disabled, intentionally or due to a fault, or is enabled. When the master recognizes an interrupt, reference the Figure3, it addresses all slaves connected to the interrupt line in sequence, and then reads the status register to determine which device is requesting attention. The RT5007 latches all conditions in the status register until the completion of the data read. The IRQ output becomes logic low when the RT5007 recognizes a fault condition, or at power on, when the main supply, VIN, and the internal logic supply, VREG, reach the correct operating conditions. It is only reset to inactive when the I2C master addresses the RT5007 with the read/write bit set (reading mode enabled), shown as below. Fault conditions are indicated by the TSD, UVLO Slave ID S 0 0 0 1 A 0 0 0 0 ACK from Slave IRQ Slave ID Status Register Address R/W 0 A1 A0 0 0 0 0 0 ACK from Slave A P S 0 0 0 1 R/W 0 A1 A0 1 A A RT5007 Status Data ACK from Slave P NAK from Master Fault Event Reload Status Register Figure 3. IRQ Latch and Release Control Table 2. Fault Detect Function and IRQ Status Bit 0 1 Bit Name DIS 2 OCP 3 Description LNB output disable Not used Over current Latched or Not Reset Condition No LNB enabled and no latched faults Yes LNB output current less than OCP 2 current and I C Read the status register. Not used IRQ Status None None IRQ set low None 4 5 PNG Power not good Not used No LNB Voltage within setting range 6 TSD Thermal shutdown Yes Junction temperature less than TSD limit IRQ set low 2 and I C read the status register. 7 UVLO VIN under voltage Yes VIN voltage higher than the UVLO 2 voltage and I C read the status register. Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 14 None None IRQ set low is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 LNB Output Voltage and Control Registers The RT5007 control register 1 is shown in Table 3. VSEL [2:0] provides voltage control on the LNB output. This function provides the necessary levels for all the common standards. The function of line-adding compensation is enabled if the cable line has voltage drop. The voltage levels are defined in Table 4. Bit 3 VSEL2 switches between the low level and high level output voltages on the LNB output. The low level, set to 0, is 13.333V nominal and the high level, set to 1, is 18.667V nominal. ENB bit controls the LNB output. When set to 1, the LNB output is switched on. When set to 0, the LNB output is disabled. Table 3. RT5007 Control Register 1 RT5007 Control Register Bit 2:0 Bit Name VSEL <2 : 0> Default 000 Access W 3 ENB 0 W 0000 W 7:4 Table 4. Output Voltage Amplitude Selection VSEL2 0 0 0 VSEL1 0 0 1 VSEL0 0 1 0 LNB (V) 13.333 13.667 14.000 0 1 1 14.333 1 1 0 0 0 1 18.667 19.000 1 1 1 1 0 1 19.667 20.000 Description 8 steps output voltage selection Enables or disables the LNB output 0 : Disable LNB output 1 : Enable LNB output Not used Tone Generation The RT5007 only provides one tone generation function. By external EXTM pin. When EXTM pin set to high control the tone generation on the LNB output by the internal 22kHz oscillator. EXTM TMODE TGATE Tone (LNB) Ref LNB (V) RT5007 control signal : Bit 0 to 3, VSEL<2:0> : These four bits provide 8-level LNB output voltage. Figure 4. Tone Generation Bit 3, ENB : Enable the LNB output. When set to 1 the LNB output is switched on. When set to 0, the LNB output is disabled. Bit 4 to 7, set to 0 (unused). Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 15 RT5007 Status Registers The RT5007 status register table is shown in Table 6 and Table 7. The status register is used for diagnosing the main fault conditions : Over Current Protection (OCP), Under Voltage Lockout (UVLO) and Thermal Shutdown (TSD). When these three faults occur, the LNB output is disabled and the bit is latch to 1 until the RT5007 is read by the master, assuming the fault has been resolved. The status register is updated on the rising edge of the 9th clock pulse in the data read sequence. The Disable bit (DIS) is used to indicate the current condition of the LNB output. It is set when either a fault occurs or if the LNB is disabled intentionally by the I2CTM master. This bit isn't latched if the LNB is commanded on again. The OCP bit is set to 1 if the LNB output detects an over current condition (typ. 500mA) over than 5ms. Where the OCP bit is reset in all cases, allowing the master to enable the LNB output. If this bit has been set, please check that the output loading is short or too heavy before re-enable again. The Power Not Good (PNG) is used for over voltage (typ. 109%) or under voltage (typ. 91%) detection of the LNB output voltage. If the LNB disabled or the output voltage is abnormal, PNG reports a logic 1 until the LNB output is enabled. The TSD bit indicates 1 when the RT5007 has detected the over-temperature condition. The disable bit, DIS, will also be set. If the condition is no longer present, then the TSD bit will be reset, allowing the master to enable the LNB output if required. If the condition is still present, then the TSD bit will remain at 1. The UVLO bit, 1 is indicated that the RT5007 has detected that the input supply is below the minimum level. The disable bit, DIS, will also be set and the RT5007 will not re-enable the output until the condition is no longer present, then the UVLO bit will be reset allowing the master to reenable the LNB output if required. If the condition is still present, then the UVLO bit will remain at 1. The DIS, PNG bits are reset without an I2CTM read sequence. The power on sequence of the master in a fault condition is to check the fault status by reading the Status registers then removing the fault condition until the status bit is reset. The fault may be detected either by continuously polling status registers or by responding to an interrupt request (IRQ). Table 6. RT5007 Status Register 1 Status Address RT5007 Status Register 1 Bit Bit Name Default Access 0 1 DIS 0 0 R R LNB output disable Not used 2 OCP 0 R Over current PNG 0 0 R R Not used Power not good 0 R Not used TSD UVLO 0 0 R R Thermal shutdown VIN under voltage 3 4 5 6 7 Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 16 Description is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 I2C Interface Acknowledge User can communicate with RT5007 by microcontroller via the two wires I2C. The two lines SDA and SCL are bidirectional lines, connected to a positive supply voltage via a pull-high resistor (typ. 4.7kΩ). The level of logic “0” and logic “1” is defined in the “Electrical Specifications” table. The output stages of RT5007 will have an open drain/ open collector in order to perform the wired-AND function. Data on the I2C bus can be transferred up to 100kbps in the standard mode or up to 400kbps in the fast mode. One clock pulse is generated for each data bit transferred. The master puts a resistive high level on the SDA line during the acknowledge clock pulse. The slave has to pulllow the SDA line during the acknowledge clock pulse. This behavior is called acknowledge, ACK. If the slave doesn't pull the SDA low, that is NACK (NotAcknowledged) behavior. The RT5007 will not generate the ACK if the input voltage is under UVLO. SCL 1 9 MSB START condition is the SDA line level transition from high to low while SCL is high level. The STOP is the SDA line level transition from low to high while SCL is high level. Each command has to begin with a START condition and finish by a STOP condition. SDA SCL S P START Condition STOP Condition Data Validity The high or low level of the data line can only change when the SCL is low level. The data on the SDA line must be stable during the high period of the clock. SDA SCL Change of Data Allowed Byte Format Every part the SDA and SCL line must be 9 bits long. There are 8 bits for a data byte and the 9 th is the acknowledged bit. The number of bytes that can be transmitted per transfer is unrestricted. Each byte is transferred with the most significant bit first (MSB). Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 8 SDA START and STOP Conditions Data Line Stable Data Valid 2 START Acknowledge from Slave Transmitted Data (I2C Bus Write Mode) In writing mode, the master (microcontroller) transmits the 8 bits data (MSB transmitted first) after START condition. Then the slave (RT5007) has to feedback an ACK condition during the acknowledge clock pulse if the data receiving is OK. The master transmitter can generate the STOP condition to end the transfer. Received Data (I2C Bus Read Mode) In reading mode, after the user transmits the slave address and data address, the master changes to RT5007 and the slave becomes the microcontroller. As for the following master generated clock bits, the RT5007 issues a byte on the SDA data bus line (MSB transmitted first) and the ACK condition is generated by microcontroller. After receiving the last data, the microcontroller enables a NACK condition to issue the data from master and the STOP condition to end the transfer. Thermal Considerations For continuous operation, do not exceed absolute maximum junction temperature. The maximum power dissipation depends on the thermal resistance of the IC package, PCB layout, rate of surrounding airflow, and difference between junction and ambient temperature. The maximum power dissipation can be calculated by the following formula : PD(MAX) = (TJ(MAX) − TA) / θJA is a registered trademark of Richtek Technology Corporation. www.richtek.com 17 RT5007 where TJ(MAX) is the maximum junction temperature, TA is the ambient temperature, and θJA is the junction to ambient thermal resistance. For recommended operating condition specifications, the maximum junction temperature is 125°C. The junction to ambient thermal resistance, θJA, is layout dependent. For WQFN-16L 3x3 package, the thermal resistance, θJA, is 30°C/W on a standard JEDEC 51-7 four-layer thermal test board. The maximum power dissipation at TA = 25°C can be calculated by the following formula: PD(MAX) = (125°C − 25°C) / (30°C/W) = 3.33W for WQFN-16L 3x3 package Layout Considerations For high frequency switching power supplies, the PCB layout is important to get good regulation, high efficiency and stability. The following descriptions are the guidelines for better PCB layout. For good regulation, place the power components as close as possible. The traces should be wide and short enough especially for the high current loop. Minimize the size of the LX node and keep it wide and shorter. The exposed pad of the chip should be connected to a strong ground plane for maximum thermal consideration. The maximum power dissipation depends on the operating ambient temperature for fixed T J(MAX) and thermal resistance, θJA. The derating curve in Figure 3 allows the designer to see the effect of rising ambient temperature on the maximum power dissipation. Maximum Power Dissipation (W)1 3.6 Four-Layer PCB 3.0 2.4 1.8 1.2 0.6 0.0 0 25 50 75 100 125 Ambient Temperature (°C) Figure 3. Derating Curve of Maximum Power Dissipation Copyright © 2014 Richtek Technology Corporation. All rights reserved. www.richtek.com 18 is a registered trademark of Richtek Technology Corporation. DS5007-00 July 2014 RT5007 The inductor should be placed as close as possible to the LX pin to minimize the noise coupling into other circuits. LX node copper area should be minimized for reducing EMI. Place the power components as close as possible. The traces should be wide and short especially for the high-current loop. The C4 should be connected directly from the output schottky diode to ground . VIN PGND C1 C5 C4 L2 D1 C2,C3,C5 and C6 should be placed as closed as possible to RT5007 for good filter. L1 C2 PGND D3 14 13 LX VIN NC 15 2 PGND NC 16 1 AGND BOOST D3 and D4 should be placed as closed as possible to VOUT for surge protection. GND 12 VREG 11 GND VOUT AGND C3 3 LNB ISET 10 4 IRQ TCAP 9 R4 D2 should be placed as closed as possible to RT5007 for surge protection. ADD EXTM 7 8 SDA PGND 6 D2 SCL C7 5 C6 D4 The exposed pad of the chip should be connected to analog ground plane for thermal consideration. VDD VA R3 From MCU R2 R1 Separate power ground (PGND) and analog ground (AGND). Connect AGND and PGND islands at a single end. Make sure there are no other connections between these separate ground planes. The PGND should be wide and short enough to connect ground plane. Figure 6. PCB Layout Guide Copyright © 2014 Richtek Technology Corporation. All rights reserved. DS5007-00 July 2014 is a registered trademark of Richtek Technology Corporation. www.richtek.com 19 RT5007 Outline Dimension D SEE DETAIL A D2 L 1 E E2 e b A A1 1 1 2 2 DETAIL A Pin #1 ID and Tie Bar Mark Options A3 Note : The configuration of the Pin #1 identifier is optional, but must be located within the zone indicated. Dimensions In Millimeters Dimensions In Inches Symbol Min Max Min Max A 0.700 0.800 0.028 0.031 A1 0.000 0.050 0.000 0.002 A3 0.175 0.250 0.007 0.010 b 0.180 0.300 0.007 0.012 D 2.950 3.050 0.116 0.120 D2 1.300 1.750 0.051 0.069 E 2.950 3.050 0.116 0.120 E2 1.300 1.750 0.051 0.069 e L 0.500 0.350 0.020 0.450 0.014 0.018 W-Type 16L QFN 3x3 Package Richtek Technology Corporation 14F, No. 8, Tai Yuen 1st Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries. www.richtek.com 20 DS5007-00 July 2014