ZL70250 Programmers Manual - MyCMPG

ZL70250 Programmer User’s Guide
ZL70250 Programmer User’s Guide
Table of Contents
1 –Introduction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2 –Power-Up Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
3 –Clock Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1
3.2
Default Clock Frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Maximum and Minimum Divide Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4 –Synthesizer Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.1
4.2
A and M Value Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
SYNTH_CTL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5 –Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
5.1
Interrupt Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
6 –Calibrations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
6.9
6.10
6.11
6.12
Calibration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Tune and Trim Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Tune and Trim Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Current Reference Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power Amplifier Bias Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
LNA Bias Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Crystal Oscillator Tune . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VCO Frequency and Amplitude Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
6.8.1 Tuning Capacitor Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
6.8.2 Frequency Band Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8.3 SAR VCO Frequency Tune TXPAOFF Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
6.8.4 VCO Amplitude Trimming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
6.8.5 VCO Frequency Tune TXPAON Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
6.8.6 SAR VCO Frequency Tune RX Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Blocker Peak Detector Offset Trim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Antenna Tune . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
LNA Load Tune . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Enable Automatic Trimming of the VCO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
7 –ADC/AGC Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
7.1
7.2
7.3
ADC_CTL4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
ADC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
AGC Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
8 –Clear Channel Assessment (CCA). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
8.1
Channel Availability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
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9 –Channel Sniffing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
9.1
9.2
Setup for Sniff and Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Start the Automatic Sniff and Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
10 –MAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.1
10.2
10.3
10.4
10.5
10.6
Power States . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
MAC Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
10.2.1 Notes on MAC Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Timing Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Use of TXRX_CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.4.1 Transmit Startup in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
10.4.2 Transmit Startup in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
10.4.3 Bidirectional Streaming in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.4.4 Bidirectional Streaming in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
10.4.5 Bidirectional Streaming with Mixed Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
10.4.6 Bidirectional Streaming Startup in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
10.4.7 One-Direction Streaming TX-TX Startup in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
10.4.8 One-Direction Streaming TX-TX Startup in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.4.9 One-Direction Streaming RX-RX Startup in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
10.4.10One-Direction Streaming RX-RX Startup in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . 42
Packet Transfer Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.5.1 Transmit Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
10.5.2 Receive Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
10.5.3 Bidirectional Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
10.5.4 Transmit or Receive Operation Abort . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data Formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
11 –System Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
11.1
11.2
11.3
11.4
11.5
11.6
11.7
11.8
11.9
11.10
11.11
11.12
11.13
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Control Interface Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Global Enables Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Enables Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Analog Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trim Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ADC/AGC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
MAC Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Synthesizer Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Clock Generator Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Interrupt Controller Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tune and Trim Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Data Port Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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A –References. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
B –Glossary of Acronyms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
C –List of Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
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D –Product Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
D.1
D.2
Customer Service . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Website . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.2.1 MyCMPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
D.2.2 Outside the U.S. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ZL70250 Programmer User’s Guide
List of Figures
Figure 7-1 • AGC Mode 1 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 7-2 • AGC Mode 2 State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-1 • Transmit Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-2 • Receive Startup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-3 • Start of Transmit in Bit-Count Mode with Pulsed TXRX_CMD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-4 • Start of Transmit in Bit-Count Mode with TXRX_CMD Initialized High . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-5 • Start of Transmit in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-6 • Bidirectional Streaming in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-7 • Bidirectional Streaming in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-8 • Bidirectional Streaming in Mixed Bit-Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-9 • Bidirectional Streaming Startup in Bit-Count Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-10 • Bidirectional Streaming Startup in Bit-Count Mode, with TXRX_CMD High . . . . . . . . . . . . . . . . . . . . .
Figure 10-11 • One Direction Streaming TX-TX Startup in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-12 • One Direction Streaming TX-TX Startup in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-13 • One Direction Streaming TX-TX Startup in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-14 • One Direction Streaming RX-RX Startup in Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figure 10-15 • One Direction Streaming RX-RX Startup in Non-Bit-Count Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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ZL70250 Programmer User’s Guide
List of Tables
Table 3-1 • Minimum, Typical, and Maximum Values for Programmable Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 3-2 • CLK_OUT Frequency Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 6-1 • Trim and Tune Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 6-2 • VCO Tuning Capacitor Array . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table 6-3 • vco_frq[13:11] Depending on Operational Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Table 10-1 • Power Modes and Associated Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 10-2 • ZL70250 Data Signal Cross-Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Table 11-1 • Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Table 11-2 • DEV_ID (Address 0x00). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11-3 • APP_ID (Address 0x01) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11-4 • CLK_ENS (Address 0x04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11-5 • SSI_CTL (Address 0x05) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11-6 • RF_EN1 (Address 0x0B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 11-7 • RF_EN2 (Address 0x0C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11-8 • RF_EN5 (Address 0x0F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11-9 • RF_EN6 (Address 0x10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 11-10 • RF_CTL2 (Address 0x12) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11-11 • RF_CTL3 (Address 0x13) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11-12 • RF_CTL4 (Address 0x14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11-13 • RF_CTL5 (Address 0x15) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table 11-14 • RF_CTL7 (Address 0x17) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11-15 • RF_TRIM_CTL (Address 0x18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 11-16 • IREF_TRIM (Address 0x20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 11-17 • XO_TRIM (Address 0x21) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 11-18 • PRESC_TRIM (Address 0x22). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 11-19 • MOD_DAC_TRIM (Address 0x23) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 11-20 • GAUS_TRIM (Address 0x24) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 11-21 • VCO_AMP_TRIM (Address 0x25) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 11-22 • ANT_TRIM (Address 0x26) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 11-23 • PD_TRIM (Address 0x27) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 11-24 • LNA_TRIM1 (Address 0x28) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 11-25 • LNA_TRIM2 (Address 0x29) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 11-26 • ADC_CTL1 (Address 0x08) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Table 11-27 • ADC_CTL2 (Address 0x2C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Table 11-28 • ADC_CTL3 (Address 0x2D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11-29 • ADC_CTL4 (Address 0x2E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11-30 • LNA_GAIN_INT (Address 0x2F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11-31 • LNA_GAIN_SEARCH (Address 0x31) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11-32 • LNA_GAIN_MAX (Address 0x32) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11-33 • AGC_THRESH_PD (Address 0x33) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11-34 • AGC_THRESH_RSSI (Address 0x34) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11-35 • ADC_RESULT (Address 0x35) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11-36 • AGC_RESULT_PD (Address 0x36) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11-37 • AGC_RESULT_RSSI (Address 0x37) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 11-38 • ADC_PEAK (Address 0x38). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 11-39 • ADC_AVG (Address 0x39). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 11-40 • MAC_CTL1 (Address 0x09) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Revision 3
6
ZL70250 Programmer User’s Guide
Table 11-41 • MAC_CTL2 (Address 0x0A). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-42 • PCM_CTL (Address 0x3C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-43 • FRM_SIZE (Address 0x3D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-44 • TIME_CNT (Address 0x3E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-45 • PLL_DELAY1 (Address 0x3F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-46 • PLL_DELAY2 (Address 0x40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-47 • IDLE_DELAY (Address 0x41) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-48 • PA_DELAY (Address 0x42) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-49 • TX_DELAY (Address 0x43) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-50 • SLO_DELAY (Address 0x44) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-51 • AGC_DELAY (Address 0x45) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-52 • RX_DELAY (Address 0x46) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-53 • TX_CNT1 (Address 0x47) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-54 • TX_CNT2 (Address 0x48) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-55 • RX_CNT1 (Address 0x49) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-56 • RX_CNT2 (Address 0x4A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-57 • PREAM_CNT1 (Address 0x51) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-58 • PREAM_CNT2 (Address 0x52) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-59 • ADJ_FAST (Address 0x55) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-60 • ADJ_SLOW (Address 0x56) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-61 • MAC_DOUT0 (Address 0x5D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-63 • SYNTH_CH_MDIV (Address 0x5F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-64 • SYNTH_CH_ADIV (Address 0x60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-65 • SYNTH_CTL (Address 0x61) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-62 • MAC_DOUT1 (Address 0x5E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-66 • SYS_CLK_DIV (Address 0x65) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-67 • CLK_OUT_DIV (Address 0x66) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-68 • PLL_CLK_DIV (Address 0x67) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-69 • IRQ_EN1 (Address 0x07) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-70 • IRQ_EN2 (Address 0x06) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-71 • IRQ1 (Address 0x69) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-72 • IRQ2 (Address 0x6B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-73 • RF_STAT (Address 0x6C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-74 • AUTO_TRIM_EN (Address 0x6D) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-75 • CONT_TRIM_EN (Address 0x6E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-76 • VFT_RX_L (Address 0x6F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-77 • VFT_RX_H (Address 0x70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-78 • VFT_PAOFF_L (Address 0x71) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-79 • VFT_PAOFF_H (Address 0x72) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-80 • VFT_PAON_L (Address 0x73). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-81 • VFT_PAON_H (Address 0x74) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-82 • VFT_L (Address 0x75) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-83 • VFT_H (Address 0x76) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-84 • VCO_FRQ_CNT (Address 0x77) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-85 • LNA_BEST_ADC (Address 0x7A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-86 • ANT_BEST_ADC (Address 0x7B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-87 • RF_CTL8 (Address 0x7C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table 11-88 • Data Port Test Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision 3
61
61
61
62
62
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63
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64
64
64
64
64
64
65
65
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66
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70
7
1 – Introduction
The ZL70250 Programmer User’s Guide contains a comprehensive list of typical and required
programming procedures for the various modes of operation and required calibrations of the ZL70250
Ultra-Low-Power Sub-GHz RF Transceiver. Complementing these procedures is a complete memory
map defining all of the application registers, with detailed descriptions of their bit definitions including
reset values and register access types.
For programming examples, example source code written in C is available to all users who complete a
Source Code License Agreement (SCLA) with Microsemi. This source code provides proven examples of
all procedures in this user’s guide and therefore significantly reduces the development time for users.
This source code runs on the ZL70250 Application Development Kit (ADK) boards, which is also
available and recommended for users. The ZL70250 ADK provides users with a platform to observe the
behavior of the procedures in a lab environment. The ZL70250 ADK also provides an example circuit,
allowing users to evaluate the RF performance of the device. Please go to www.microsemi.com/cmpg for
more information.
Revision 3
8
2 – Power-Up Initialization
After power-up, it is assumed that the external controller holds the ZL70250 chip in reset by driving the
RESET_B pin low.
•
All the registers are in their reset state when RESET_B is low (active low).
•
When the reset is released (RESET_B goes high) all the registers stay in reset (except for the two
bits osc_en and clk_out_en, which are in the CLK_ENS register, as stated below). The external
controller has to send write commands to the ZL70250 chip through the control interface in order
to enable its different blocks and functions.
The three internal signals osc_en, sys_clk_en, and clk_out_en are unique in that they are clocked by the
SCL pin, whereas all other registers are clocked by the system clock (sys_clk). This provides limited
control interface access when the system clock is not running while in the ultra-low-power state. Those
three signals are used to enter and exit the different SLEEP states of the ZL70250 chip:
•
•
•
The osc_en output signal controls the XTAL oscillator block:
–
During reset (where RESET_B is low), osc_en is low (disabled).
–
When RESET_B input signal goes high, osc_en goes high, too. That starts the XTAL oscillator
block. This signal is then register controlled by writing to the CLK_ENS register.
The clk_out_en output signal controls the frequency divider that generates the external clock
CLK_OUT (for clocking external controller; optional):
–
During reset (where RESET_B is low), clk_out_en is low (disabled).
–
When RESET_B input signal goes high, clk_out_en goes high, too, generating the CLK_OUT
signal to the external controller. This signal is then register controlled by writing to the
CLK_ENS register.
The sys_clk_en output signal controls the frequency divider that generates the system clock
sys_clk (the default is the crystal frequency divided by 22) going to the ZL70250 MAC:
–
During reset (where RESET_B is low), sys_clk_en is low (disabled).
–
When RESET_B input signal goes high, sys_clk_en stays low. The frequency divider that
generates the sys_clk stays disabled, keeping the system clock sys_clk going to the ZL70250
MAC inactive in order to save power. This signal is then register controlled by writing to the
CLK_ENS register.
Note: When RESET_B signal goes high, the XTAL oscillator block starts. Its start-up time of about 5ms
has to be taken into account before writing to the sys_clk_en bit that activates the ZL70250 MAC
system clock sys_clk.
Recommended Initial Register Settings
The section "11 – System Memory Map" on page 46 summarizes the memory map of the ZL70250.
Recommended initial register settings are provided in the "Recommended Values" column of Table 11-1
on page 47. Write the recommended values to the appropriate registers after every chip reset (RESET_B
pin low).
Revision 3
9
3 – Clock Generator
3.1
Default Clock Frequencies
With a 24.576-MHz crystal, when the clocks are enabled they run at the following frequencies by default:
3.2
•
CLK_OUT = 24.576MHz / 24 = 1.024MHz
•
PLL clock = 24.576MHz / 81 = 303.4kHz
•
bit period = sys_clk / 6 = 186.167kHz
Maximum and Minimum Divide Count Values
CLK_OUT_DIV can be changed within the range mentioned in Table 3-1. The resulting range for
CLK_OUT is shown in Table 3-2.
Table 3-1 • Minimum, Typical, and Maximum Values for Programmable Counter
Register [bits]
CLK_OUT_DIV[4:0] (clk_out_div)
Minimum
Typical
Maximum
4
24
30
Table 3-2 • CLK_OUT Frequency Range
24.576-MHz XTAL
Minimum div: 4
Typical div: 24
Maximum div: 30
6.144MHz
1.024MHz
819.2kHz
Note: Warning: For proper operation, SYS_CLK_DIV must not be changed from its default value (typical
value).
Revision 3
10
4 – Synthesizer Controller
4.1
A and M Value Calculation
The A and M registers must be programmed any time a different channel is desired.
The A value can be programmed through the system bus using ch_a_div in the SYNTH_CH_ADIV
register.
The M value can be programmed through the system bus using SYNTH_CH_MDIV.
LO control (high/low) can be programmed through the system bus using ch_lo_ctl in the
SYNTH_CH_ADIV register.
A and M requirements
A ≥ 5, M ≥ 16
EQ 4-1
A and M calculation
The total number of PLL clock periods to be produced by the VCO in order to run through the PLL divide
cycle is given by Ntot:
Ntot =
int(carrier frequency / PLL clock)
EQ 4-2
In the ZL70250 PLL implementation, the relation between Ntot and A and M is given by EQ 4-3 below:
Ntot =
17 × A + 16 × M
EQ 4-3
EQ 4-3 shows that A is the number of times prescaler needs to count to 17 and M is the number of times
the prescaler needs to count to 16.
To accommodate the phase adjustment hardware implementation, A needs to be greater than 0 by a
constant Q. Therefore:
A
=
((Ntot – Q) mod 16) + Q
EQ 4-4
M
=
(Ntot – A × 17) / 16
EQ 4-5
From EQ 4-4, it is derived that:
Q ≤ A ≤ 15 + Q
EQ 4-6
The valid range for Q is:
5 ≤ Q ≤ 48
EQ 4-7
There are no known advantages or disadvantages in selecting a particular Q. Microsemi uses a value of
5 for Q in all its evaluations. It is therefore recommended to use the same setting to stay on proven
ground.
EQ 4-2, EQ 4-4, and EQ 4-5 can be used for calculating A and M values to program registers
SYNTH_CH_ADIV and SYNTH_CH_MDIV.
The ZL70250 Synthesizer Programming Table.xls spreadsheet implements the above formulas and
can also be used to generate the A and M values for a particular target frequency or as a look-up table
for all the synthesizable frequencies within the ZL70250 range.
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A and M Programming Example
1. Determine the output frequency for the current channel being programmed. Ntot represents the
number of counts that corresponds to the output frequency. From the table, look up the values for
A and M. A is the number of times the prescaler divides by 17 and M is the number of times the
prescaler divides by 16.
2. If Ntot of 2620 is chosen, the values in EQ 4-3 on page 11 are 17 × 12 + 16 × 151 = 2620, that is:
– A is 12, with a binary representation of 7’b0001100.
–
M is 151, with a binary representation of 8’b10010111.
3. Set the LO control bit to above channel; that is, set ch_lo_ctl equal to 1 in the SYNTH_CH_ADIV
register.
4. Program SYNTH_CH_ADIV equal to 8’b10001100 (0x8C).
5. Program ch_m_div bits equal to 8’b10010111 (0x97) in the SYNTH_CH_MDIV register.
4.2
SYNTH_CTL
Below are bit descriptions for the SYNTH_CTL register:
1. tx_mode_en: In order to select between TX/RX channel frequencies, the synthesizer controller
monitors the auto_txrx_en bit in the MAC_CTL1 register. In automatic mode (where auto_txrx_en
is 1), the MAC controls the synthesizer. In manual mode (where auto_txrx_en is 0), tx_mode_en
controls the synthesizer. When tx_mode_en is set to 0 the synthesizer is in RX mode, and when
set to 1 the synthesizer is in TX mode.
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5 – Interrupt Controller
5.1
Interrupt Description
There is only one interrupt pin at the top-level of the ZL70250 chip called IRQ, and the interrupt sources
are determined by writing to the enable registers IRQ_EN1 and IRQ_EN2. More than one interrupt
source per register can be enabled. In this case, when the IRQ pin is set high, it is necessary to read the
interrupt registers IRQ1 and IRQ2 (with a control interface read command) to determine what the
source(s) is.
When the corresponding interrupts are enabled, the outputs of the interrupt registers IRQ1 and IRQ2
create an interrupt on the IRQ pin (level high). If an interrupt is not enabled, the interrupt pulse in the
interrupt registers IRQ1 and IRQ2 can still be latched but that does not generate an interrupt on the IRQ
pin.
If an interrupt is enabled and it is set, the IRQ pin is set high until is lowered either by reading the
respective interrupt register or by the disabling the interrupt by writing to the appropriate enable register.
The RF_STAT returns the status as defined in the memory map when it is read, but a status can never
generate an interrupt on the IRQ pin.
Registers IRQ1, IRQ2, and RF_STAT are read-only and registers IRQ1 and IRQ2 are clear-on-read
(CoR).
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6 – Calibrations
6.1
Calibration1 Summary
Registers (or parameters) that control analog circuit operation may be categorized into three classes:
•
Preset: Registers whose values are defined during IC evaluation and are set to a constant value
(ideally the default value). No calibration is required for such parameters. These registers are
supplied for design flexibility and to reduce risk.
•
Factory: Registers whose values must be determined in production calibration procedures
requiring special equipment. These registers relate to parameters that may vary from device to
device due to process variations, operation range selections, or external component values.
•
Operation: Registers whose values must be determined in production and/or by operational
calibration procedures executed by the chip independent of external equipment. These registers
relate to parameters that may vary from device to device due to process variations, operation
range selections, or external component values.
Parameters are typically stored in external nonvolatile memory and loaded into the transceiver after a
reset. Disabling a block through the control interface (where en is 0) does not reset the registers holding
the trim values or other parameters.
ZL70250 does not perform any trimming or tuning at power-up or at any other time without being
commanded to do so over the control interface.
The calibration sequence should be executed in the order provided in Table 6-1 on page 15. Some of the
trims can be omitted when conducting tests that do not involve a given block, but care should be taken
because some seemingly unrelated blocks actually depend on each other. The crystal oscillator need not
be trimmed for tests that do not involve transmitting, receiving, or clock frequencies. The current
reference should always be trimmed first before any other trim. The safest approach is to follow the
detailed procedures in the paragraphs that follow Table 6-1 on page 15. Only one of the calibrations can
be initiated at the same time by software.
1.
The terms calibration, tuning, and trimming are used interchangeably throughout this document.
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Table 6-1 • Trim and Tune Summary
Order
Parameter Name
P (Preset)
F (Factory)
O (Operating)
Force and Sense
Requirements
Notes
F, O
None. Internal calibration.
1,2
1
Current reference
2
Power amplifier bias
P
Calibrated antenna/LNA
and power meter.
3
3
LNA bias
P
None.
3
4
Crystal oscillator frequency
F
Frequency counter.
5
SAR VCO frequency TXPAOFF
mode
O
None. Internal calibration.
6
VCO amplitude
O
None. Internal calibration.
7
Repeat SAR VCO frequency
TXPAOFF mode
O
None. Internal calibration.
8
VCO frequency TXPAON mode
(with increment/decrement tuning of
the VCO frequency using internal
counter providing adjustment pulse)
O
None. Internal calibration.
9
SAR VCO frequency RX mode
O
None. Internal calibration.
10
Blocker peak detector offset
O
None. Internal calibration.
11
Antenna (with increment/decrement
tuning of the VCO frequency using
internal counter providing
adjustment pulse and in the
TXPAON mode)
O
None. Internal calibration.
12
LNA load
O
None. Internal calibration.
13
Enable automatic trimming of the
VCO
O
None.
Notes:
1. The current reference trim has to be done at the factory (mandatory) and can also optionally be
performed after power-up.
2. Factory calibration must be re-run (at the factory or by software) when changing country.
3. Preset trim values are determined during device characterization and should be the same for all
devices.
6.2
Tune and Trim Sequence
Note: IMPORTANT: In order to optimize the tune and trim procedure on the ZL70250 chip at the factory
or after every power-up, the tune and trim sequence described in the following paragraphs
assumes that the steps are performed in a contiguous manner. If a tune or trim has to be run
independently, the settings performed before this particular tune or trim have to be taken into
account.
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6.3
Tune and Trim Setup
The tune and trim sequence can start only after setting up the basic functionality of the ZL70250 chip
both at the factory and at power-up:
1. Turn on the power supply.
2. Wait for the crystal oscillator start-up time: 5ms.
3. Set the sys_clk_en bit in the CLK_ENS register to 1 to enable the frequency divider that
generates the sys_clk going to the MAC.
4. If the interrupts are intended to be used for the tune and trim procedures, then enable the
trim_done_irq interrupt by writing 0x20 to the IRQ_EN1 register. When the trim_done_irq interrupt
is set, read the IRQ1 register at the end of each tune or trim procedure to see if the trim_fail_irq
status bit has been set (register is cleared on read operation).
6.4
Current Reference Trim
It is very important to trim the current reference before any other trimming or tuning because the current
reference supplies current to almost all the analog circuits on the chip. If the reference is untrimmed then
the other trims are not valid.
The ZL70250 uses an external resistor of 2% or better accuracy to set its internal current reference. The
node attached to the external resistor is sensitive to noise that can be picked up by the exposed pin and
runs. For this reason, internal resistors are used in the current reference and other reference circuits.
Before they can be used, however, an internal resistor of the same type and value is compared with the
external resistor and trimmed to match.
The current reference trimming procedure is:
1. Before the automatic IREF trimming procedure can be done, perform the following setup through
the control interface:
i.
Set the sys_clk_en bit in the CLK_ENS register to 1 to enable the frequency divider that
generates the sys_clk going to the MAC.
ii. Enable the IREF trimming procedure by setting the iref_en_trim bit in the AUTO_TRIM_EN
register (that is, write 0x01 to the AUTO_TRIM_EN register). The AUTO_TRIM_EN register is
cleared internally once the trim procedure is done.
2. Now that the automatic IREF trimming procedure is launched, EITHER:
i.
Wait for the trim_done_irq if enabled.
ii. Wait for time-out approximately 700µs.
iii. Poll the interrupt status register IRQ1 for the trim_done_irq or trim_fail_irq bits.
3. At the end of the IREF trimming procedure:
i.
6.5
If the trim_fail_irq status has been set by the trimming procedure, check whether the external
resistor used for the IREF trimming procedure is appropriate. If the external resistor is
appropriate (and the trim_fail_irq status has been set), the ZL70250 chip may be defective.
Power Amplifier Bias Trim
The power amplifier bias trim settings are available for adjusting the power level. A programmable binary
code selects the output current.
To trim the power amplifier bias current, write the preset value (not necessarily the default value) to the
RF_CTL4 register. It is assumed that the power amplifier bias current does not need to be trimmed on a
part-by-part basis. Instead, a predetermined value can be programmed into every part. If a very accurate
output power level is desired, then individual trimming may be necessary. Trim the current reference
before any individual trimming is performed.
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6.6
LNA Bias Trim
The LNA bias trim settings are available for adjusting the bias current level of the LNA and mixer.
To trim the LNA bias, write the preset value (not necessarily the default value) to lna_bias_trim in the
LNA_TRIM2 register. It is assumed that the LNA bias current does not need to be trimmed on a part-bypart basis. Instead, a predetermined value can be programmed into every part. If a very accurate LNA
gain is desired, then individual trimming may be necessary. Trim the current reference before any
individual trimming is performed.
6.7
Crystal Oscillator Tune
The purpose of the crystal oscillator tuning is to improve the absolute accuracy of the system reference
frequency. This tuning is done once during factory calibration after the device has been installed.
Note: IMPORTANT: The crystal oscillator tuning depends on the selection of the crystal and the loading
that is placed on the crystal pins. To save power, the crystal can be used without external
capacitors. However, a slight frequency pull occurs from the specified crystal frequency and the
crystal can not be trimmed according to the procedure detailed below because there is not enough
trimming capacitance available in the ZL70250 device. The ZL70250 Synthesizer Programming
Table.xls spreadsheet can be used to determine the VCO frequency. The crystal frequency is the
frequency on the CLK_OUT pin multiplied by 24. From there you can calculate the PPM pull of the
crystal frequency, which can then be entered into the spreadsheet to determine the resulting VCO
frequency. Also, as long as the transmitter and receiver devices are trimmed to match crystal
frequencies, no degradation in system performance is noticeable.
The crystal oscillator tuning procedure is:
6.8
•
Measure CLK_OUT using a frequency counter that has better than 1PPM accuracy.
•
Change the six-bit control word in the XO_TRIM register until the desired frequency is reached.
The desired frequency is the crystal frequency divided by CLK_OUT_DIV (see "3.1 Default Clock
Frequencies" on page 10).
•
If the crystal oscillator tune cannot be achieved (where XO_TRIM is 0x00 or XO_TRIM is 0x3F)
then most likely the crystal oscillator does not meet the specifications. Alternatively, the crystal
could be bad or the capacitive load too high.
VCO Frequency and Amplitude Tuning
The terms "tuning" and "trimming" are used interchangeably in this section. Please read all the sections
related to VCO trimming before starting programming.
Trimming the VCO frequency and amplitude keeps the VCO in the proper operating conditions. There
are several steps to accomplish this and they should be done in the order shown:
1. Select the frequency band.
2. Set the VCO amplitude to maximum.
3. Perform the TXPAOFF mode SAR frequency trim (see "6.8.3 SAR VCO Frequency Tune
TXPAOFF Mode" on page 20).
4. Perform the VCO amplitude trim (see "6.8.4 VCO Amplitude Trimming" on page 21).
5. Perform another TXPAOFF mode SAR frequency trim (see "6.8.3 SAR VCO Frequency Tune
TXPAOFF Mode" on page 20).
6. Perform the TXPAON mode frequency trim (see "6.8.5 VCO Frequency Tune TXPAON Mode" on
page 22).
7. Perform the RX mode SAR frequency trim (see "6.8.6 SAR VCO Frequency Tune RX Mode" on
page 23).
Detailed descriptions of the trim steps follow this section.
Note: IMPORTANT: Periodic retrimming of TXPAOFF and TXPAON modes may be required if the
antenna impedance changes or operating conditions change drastically.
Note: IMPORTANT: Trim the VCO with the expected antenna in the nominal application condition.
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The strategy outlined minimizes the spectral content of the TX signal when the power amplifier is turned
on. During normal operation when the ZL70250 device changes from TXPAOFF mode to TXPAON
mode, the power amplifier turns on, which changes the capacitive load on the VCO, thus pulling the
frequency. The capacitance change is compensated, or cancelled out, by changing the VCO trim caps.
This explains the reason for having two trim codes for transmit.
The VCO frequency can be trimmed for every channel and the resulting values stored in a table. When a
channel is selected, the appropriate trim values can be written back to the VCO. It is not, however,
necessary to trim for every channel if the device is being used only within a couple megahertz. In that
case, set the synthesizer to the channel in the middle of the range of interest and trim the VCO frequency
for that channel only.
The VCO amplitude is dependent on frequency but, again, it is necessary to trim only in the center of the
range of channels as long as the device is used within a 10-MHz window. The 10MHz is not a hard-andfast rule but instead depends on how constant the output power should be over the band of operation.
There are two methods for trimming the VCO: the successive approximation method (SAR) and the
continuous tune method. The successive approximation method is normally used in a production
environment to determine nominal values for the frequencies (channels) that the application will be
using. It may also be used in the field to calibrate the VCO when power is first applied to the device. It is
important to note that this method sweeps through many frequencies to get to the target frequency. To
remain compliant with regulatory standards, the successive approximation method must never be used
with the TX PA on since it would randomly transmit radio interference. It is highly recommended that
steps 1–7 above always be followed. Once this calibration is completed, the continuous tuning method is
recommended to allow for minor corrections to the VCO frequency that may occur from ambient
temperature changes.
•
Successive approximation method: The frequency tuning can be accomplished by setting up the
synthesizer to generate a VCO frequency at the center of the range and then monitoring the VCO
control voltage and changing the tuning capacitors until the VCO control voltage matches a
reference voltage. This is done by successive approximation (SAR method) starting with
vco_frq[10]. This method causes the VCO to jump over wide frequency steps and therefore is not
used with the power amplifier turned on.
•
Continuous tune method: Frequency tuning can also be done by a continuous tune method, used
in the TXPAON section. In this method, the trim value is adjusted up or down by 1, depending on
the state of the control voltage comparator. A timer causes this adjustment to occur once every
500µs (a little longer than the PLL settling time). The trim value moves one step at a time to reach
the correct spot and then toggles between the two codes that cause the control voltage
comparator to change state.
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6.8.1
Tuning Capacitor Description
Table 6-2 is a description of the capacitor array that is used in the ZL70250 VCO for tuning. The trim cap
array has 14 bits of control defined in groups.
Table 6-2 • VCO Tuning Capacitor Array
Section
Bits
Description
Upper
vco_frq[13:11]
MSB
vco_frq[10]
Most significant bit of the automatic tuning bit set.
Overlap
vco_frq[9]
Bit generates intentional negative frequency step (that
is, bit [9] capacitance is less than the summed
capacitance of bits [8:0]).
Mid
Transition bit
Upper three bits. These three bits set the frequency
band (see "6.8.2 Frequency Band Selection" on
page 20). These bits are fixed and are not part of
automatic trim; they must be set manually in the
RF_CTL8 register.
vco_frq[8:6]
vco_frq[5]
Low bits
vco_frq[4:2]
LSB bits
vco_frq[1:0]
Note: IMPORTANT: The VCO frequency trim register is interpreted by the chip logic as frequency rather
than capacitance, which means that higher valued trim codes actually select less capacitance, so
the VCO oscillates at a higher frequency. Of course, lower codes mean lower frequency but higher
capacitance. This is important to keep in mind when interpreting the trim codes that are read after
the trimming procedures.
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6.8.2
Frequency Band Selection
Before any automatic frequency tuning is initiated, the frequency range must be selected. The top three
bits vco_frq[13:11] are manual control bits and define one of eight frequency ranges of operation. A
rough range start select setting for these three bits can be found in Table 6-3. The application layout and
substrate parasitics can greatly affect the range settings.
Table 6-3 • vco_frq[13:11] Depending on Operational Frequency
vco_frq[13:11]
Frequency (MHz)
0
795.0 – 795.6
1
795.6 – 819.3
2
819.3 – 843.6
3
843.6 – 871.8
4
872.8 – 900.6
5
900.6 – 933.0
6
933.0 – 965.1
7
Not supported
Note: Warning: Frequency Band Selection for Channels Near the Band Edge
Some difficulties with the trim failing may be encountered when trimming channels that are near
the edge of the frequency band. In some cases a simple change to the next frequency band might
be all that is required. Other cases cannot be solved so simply. This is due to the fact that there
are three frequency trims, each resulting in a different value. The RX trim may work perfectly well
for a channel near the upper edge of the frequency range only to have the TXPAON trim fail
because it cannot reach a high enough trim code (low enough capacitance). If a higher frequency
band is selected then the RX trim fails. The frequency bands were designed to overlap and lab
evaluation indicates that the overlap between the lowest bands is approximately 2.7MHz and the
overlap between the highest bands is approximately 5.86MHz. This is still not quite enough
overlap to allow all channels to be trimmed in a normal way.
This problem can be solved in the following way. One can take advantage of the fact that the
power amplifier is not on during the RX mode and the RX mode never transitions directly to the
TXPAON mode. This means that the RX mode does not need to be trimmed as closely. In the trim
sequence, when finished with the TXPAON mode trim, use the trim code from the TXPAOFF
mode for the RX mode (without trimming the RX mode).
6.8.3
SAR VCO Frequency Tune TXPAOFF Mode
Note: The procedure detailed below is not the entire VCO frequency tune procedure. It is only the
TXPAOFF (transmitter power amplifier off) part of the general VCO frequency tune procedure
described in "6.8 VCO Frequency and Amplitude Tuning" on page 17.
The tuning procedure for the SAR VCO frequency in TXPAOFF mode is:
1. Before initiating the automatic SAR VCO frequency tune TXPAOFF mode procedure, complete
the required setups through the control interface:
–
Set the synthesizer A and M values to the operational frequency bank (for more details, refer
to "4 – Synthesizer Controller" on page 11).
–
Program registers as follows:
a. Enable the PLL by setting man_pll_en bit in the RF_EN1 register to 1 (that is, write 0x04 to
the RF_EN1 register).
b. Program the SYNTH_CTL register to 0x07 to put the synthesizer in transmit mode.
c. Verify that the MAC_CTL1 register is equal to 0x00.
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–
If trimming to a frequency in a new range, program the VCO amplitude to the maximum by
writing 0x3F to the VCO_AMP_TRIM register. After the first frequency trim, perform an
amplitude trim and then repeat the frequency trim without altering the amplitude.
–
Enable the VCO frequency tuning procedure by setting the vco_frq_en_trim bit in the
AUTO_TRIM_EN register (that is, write 0x02 to the AUTO_TRIM_EN register).
2. Then launch the automatic SAR VCO frequency tune TXPAOFF mode procedure and EITHER:
–
Wait for the appropriate interrupts if enabled.
–
Wait for time-out (approximately 25ms).
–
Poll the appropriate interrupt status registers or the appropriate trim registers.
3. At the end of the SAR VCO frequency tune TXPAOFF mode procedure:
–
If the trim_fail_irq status has been set by the tuning procedure, check that the MAC is
disabled, the PLL is enabled, and theman_xmtr_en is disabled. If the trim continues to fail
then the ZL70250 chip may be defective.
–
If the trim_fail_irq status has been set, read the VCO_PAOFF_H and VCO_PAOFF_L
registers. If they are at a minimum/maximum value, then adjust the band accordingly. For
example, if VCO_PAOFF_H is 0x07 and VCO_PAOFF_L is 0xFF, then the VCO ran out of
range during the auto trim and the band edge has to increase by one.
–
If the trim done interrupt does not go high, read the vco_frq_en_trim bit in the
AUTO_TRIM_EN register. If it is still high, either not enough time has been allowed or the
setup is interfering with the trim. This can happen if the MAC is enabled and trying to use the
bus.
6.8.4
VCO Amplitude Trimming
This tuning sets the amplitude for the VCO and should be performed at each startup after a VCO
frequency tune. The power amplifier output level is dependent on the VCO amplitude, so higher VCO
amplitude results in a higher power amplifier output level.
It is important to note that the VCO amplitude changes with frequency. After a VCO frequency trim, trim
the amplitude followed by a full frequency trim since the frequency is somewhat dependent on the
amplitude as well. This order of trims is shown in "6.8 VCO Frequency and Amplitude Tuning" on
page 17.
The VCO amplitude trimming procedure is:
1. Before initiating the automatic VCO amplitude trimming procedure, complete the required setups
through the control interface:
–
Enable the PLL by writing 0x04 to the RF_EN1 register (that is, set man_pll_en equal to 1).
This should already be enabled as part of the frequency trim.
–
Enable the VCO amplitude trimming procedure by setting the vco_amp_en_trim bit in the
AUTO_TRIM_EN register (by writing 0x04 to the AUTO_TRIM_EN register).
2. Then launch the automatic VCO amplitude trimming procedure and EITHER:
–
Wait for the appropriate interrupts if enabled.
–
Wait for time-out (approximately 550µs).
–
Poll the appropriate interrupt status registers or the appropriate trim registers.
3. At the end of the VCO amplitude trimming procedure:
–
If the trim_fail_irq status has been set by the trimming procedure, the setup may be incorrect
or the ZL70250 chip may be defective.
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6.8.5
VCO Frequency Tune TXPAON Mode
Note: The procedure detailed below is not the entire VCO frequency tune procedure. It is only the
TXPAON (transmitter power amplifier on) part of the general VCO frequency tune procedure
described in "6.8 VCO Frequency and Amplitude Tuning" on page 17.
The VCO frequency tuning procedure for TXPAON mode is:
1. Before initiating the VCO frequency tune TXPAON mode procedure, complete the required
setups through the control interface:
–
If this is an initial trimming or if the base frequency has been changed, read the registers
VFT_PAOFF_L and VFT_PAOFF_H and copy their values to VFT_PAON_L and
VFT_PAON_H, respectively. They are used as values to start the tuning procedure.
–
If this trim is being done after a channel change only (base frequency is not changed), then
use the current values in the VFT_PAON_L and VFT_PAON_H as a starting point.
–
Set the value of the internal counter providing the adjustment pulse to approximately 500µs
(that is, write 0x8C to the VCO_FRQ_CNT register).
–
Enable the transmitter by setting the man_xmtr_en bit in the RF_EN1 register to 1 (by writing
0x01 to the RF_EN1 register).
–
Program the SYNTH_CTL register to 0x07 to put the synthesizer in transmit mode.
–
Verify that the MAC_CTL1 register is equal to 0x00.
–
Set a timeout in the processor to 1 second in case the tune procedure goes to the minimum or
maximum trim value.
–
Enable the increment/decrement tuning of the VCO frequency using an internal counter
providing the adjustment pulse (by writing 0x02 to the CONT_TRIM_EN register).
2. Then launch the VCO frequency tune TXPAON mode procedure:
–
The trim_done_irq status does not work in this trim mode. The trim must be monitored and
turned off (write 0x00 to CONT_TRIM_EN) when a criteria is met. The criteria for the trim
completion are when the comparator (vco_frq_cmp_out_stat in the RF_STAT register)
changes state. The trim algorithm adjusts the tuning based on the comparison of the VCO
control voltage to a reference voltage. When the trim has settled, the algorithm causes the
comparator to change states regularly. If a microcontroller is controlling ZL70250, it should
read the comparator after a wait period and then continue monitoring the comparator for the
opposite state. When both 1 and 0 states have been found, the algorithm can be terminated.
–
The tuning should take about 500µs times the number of LSB trim steps needed to reach the
correct trim code.
–
If the timeout is reached, read the IRQ1 register to see if the trim_fail_irq bit has been set. If
the trim_fail_irq bit has been set, then the trim has failed because the trim value has reached
0 (minimum) or 2047 (maximum) value.
3. At the end of the VCO frequency tune TXPAON mode procedure:
–
Disable the increment/decrement tuning of the VCO frequency using an internal counter
providing the adjustment pulse by writing 0x00 to the CONT_TRIM_EN register.
–
Disable the power amplifier by writing 0x00 to the RF_EN1 register.
–
If the trim_fail_irq status bit has been set by the tuning procedure, then verify that
vco_frq[13:11] in the RF_CTL8 register has been set correctly (see "6.8.2 Frequency Band
Selection" under "6.8 VCO Frequency and Amplitude Tuning" on page 17). If the band is not
set correctly or the tuning frequency is on the edge of the band, try going to the next closest
band and re-run trim. If trim still fails, then the ZL70250 chip may be defective.
Note: The TXPAON mode can be tuned using the successive approximation algorithm just as in the
TXPAOFF mode. This method is not recommended because the device radiates power on
channels that are not allocated for it. This trim method can however be used as a manufacturing
trim, test procedure, or debug tool. Write 0x02 to the AUTO_TRIM_EN register.
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6.8.6
SAR VCO Frequency Tune RX Mode
Note: The procedure detailed below is not the entire VCO frequency tune procedure. It is only the RX
mode part of the general VCO frequency tune procedure described in "6.8 VCO Frequency and
Amplitude Tuning" on page 17.
The tuning procedure for the SAR VCO frequency in RX mode is:
1. Before initiating the automatic SAR VCO frequency tune RX mode procedure, complete the
required setups through the control interface:
–
Program registers as follows:
a. Enable the receiver by setting the man_rcvr_en bit in the RF_EN1 register to 1 (write 0x02
to the RF_EN1 register).
b. Program the SYNTH_CTL register to 0x03 to put the synthesizer in receive mode.
c. Verify that the MAC_CTL1 register is equal to 0x00.
–
Enable the VCO frequency tuning procedure by setting the vco_frq_en_trim bit in the
AUTO_TRIM_EN register (that is, write 0x02 to the AUTO_TRIM_EN register).
2. Then launch the automatic SAR VCO frequency tune RX mode procedure and EITHER:
–
Wait for the appropriate interrupts if enabled.
–
Wait for time-out (approximately 25ms).
–
Poll the appropriate interrupt status registers or the appropriate trim registers.
3. At the end of the SAR VCO frequency tune RX mode procedure:
–
6.9
If the trim_fail_irq status has been set by the tuning procedure, it is likely that the frequency
range needs to be adjusted up or down by one count. Adjust the range and try again. If the
trim still fails, the ZL70250 chip may be defective.
Blocker Peak Detector Offset Trim
The trimming procedure for the blocker peak detector offset is:
1. Before initiating the automatic blocker peak detector offset trimming procedure, perform the
following setup:
–
Enable the global PLL man_pll_en by writing 0x04 to the RF_EN1 register.
–
Enable the blocker peak detector block and the ADC analog block by writing 0x82 to the
RF_EN5 register (setting both man_pd_en and man_adc_ana_en equal to 1). (The blocker
peak detector input range has to be 50mV, which is already the default value set in the
RF_TRIM_CTL register, where pd_range is 0.)
–
Set up the ADC digital controller to select the blocker peak detector output as the input to the
ADC analog block by writing 0x40 to the ADC_CTL1 register (that is, program
adc_mux_in_sel to 010).
–
Enable the blocker peak detector procedure by setting the pd_en_trim bit in the
AUTO_TRIM_EN register (that is, write 0x08 to the AUTO_TRIM_EN register).
2. Then launch the blocker peak detector offset trimming procedure and EITHER:
–
Wait for the appropriate interrupts if enabled.
–
Wait for time-out (approximately 3ms).
–
Poll the appropriate interrupt status registers or the appropriate trim registers.
3. At the end of the blocker peak detector offset trimming procedure:
–
If the trim_fail_irq status has been set by the trimming procedure, read the final ADC average
value in the ADC_AVG register. If the ADC average value is not 0x00, the AGC may not work
as expected when converting the blocker peak detector input. Therefore the ZL70250 chip
may be defective.
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6.10 Antenna Tune
Antenna tuning is performed during manufacturing after the device is mated with an antenna, after any
channel bank switch, and possibly after any power-up. The purpose of this trim is to select the
capacitance, which peaks the antenna resonance at the required frequency. A peak detector in the RF
receiver section stores the maximum voltage swing on the receiver input pins. The voltage is measured
by the five-bit ADC block. An algorithm for finding the best capacitor value is implemented in the trim
algorithms.
The antenna tuning procedure is:
1. Before initiating the automatic antenna tune procedure, perform the following setup:
–
Set the blocker peak detector input range to 100mV by writing 0x02 to the RF_TRIM_CTL
register (that is, set pd_range equal to 1).
–
Select the blocker peak detector as the input to the ADC by writing 0x40 to the ADC_CTL1
register.
–
Set the lowest internal LNA gain by writing 0x00 to the LNA_GAIN_INT register.
–
Enable the blocker peak detector block, the ADC analog block, and the LNA by writing 0x83 to
the RF_EN5 register (that is, set man_rf_en, man_pd_en, and man_adc_ana_en equal to 1).
–
Set the power amplifier to the lowest power setting by writing 0x40 to the RF_CTL4 register
(that is, set dac_scale_dwn equal to 1 and write 000000 to pa_pwr_ctl).
–
Enable the power amplifier by writing 0x03 to the RF_EN6 register (that is, set man_pa_en
and man_pa_tx_en equal to 1). Verify that the modulation is off, which is the default behavior
(that is, man_gaus_mod is cleared, or equal to 0, in the RF_CTL2 register).
–
Write 0x2A to the VCO_FRQ_CNT register; this is the default value, approximately 150µs.
–
Enable the increment/decrement tuning of the VCO frequency using an internal counter
providing the adjustment pulse by writing 0x02 to the CONT_TRIM_EN register, which sets
incdec_cnt_en equal to 1.
–
Enable the antenna tune procedure by setting the ant_en_trim bit in the AUTO_TRIM_EN
register (that is, write 0x20 to the AUTO_TRIM_EN register).
2. Then launch the antenna tune procedure and EITHER:
–
Wait for the appropriate interrupts if enabled.
–
Wait for time-out (approximately 25ms).
–
Poll the appropriate interrupt status registers or the appropriate trim registers.
3. At the end of the antenna tune procedure:
–
Wait for 2ms (to allow the VCO frequency trim to settle after the final antenna tune value is
written) and disable the increment/decrement tuning of the VCO frequency using an internal
counter providing the adjustment pulse by writing 0x00 to the CONT_TRIM_EN register (that
is, clear incdec_cnt_en).
–
If the trim_fail_irq status has been set by the tuning procedure because the ANT_TRIM
register is set to 0 (minimum) or 31 (maximum):
a. If the tune frequency is at the high end of what the VCO can reach and the trim value is at
the lowest trim value, then there is no failure.
b. If the tune frequency is at the low end of what the VCO can reach and the trim value is at
the highest trim value, then there is no failure.
c. Check the best average value of the ADC during the trimming (the ANT_BEST_ADC
register). If the value is below 0x05 then an error exists. This indicates a weak signal into
the LNA and that the full range of the ADC is not being used. The antenna may have a
problem (connectivity, value, etc.) or the power amplifier output may need to be increased.
d. Verify that the matching network is configured properly and the antenna impedance is
correct.
e. Otherwise, the ZL70250 chip may be defective.
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6.11 LNA Load Tune
To get enough gain in the front-end amplifier without using much current, an inductive load is tuned to
resonate at the receive frequency. The load tuning capacitance must change when the frequency bank
changes, and the LNA load tune section of the tune and trim block is required to find the optimum tuning
capacitance for a given channel. Once tuned in the center of a bank of channels, it is not necessary to
tune for other channels within the bank. The tuning is accomplished by transmitting on the channel of
interest (channel 3 in a bank of six channels) and then stepping through the LNA load tuning capacitors
while monitoring the LNA peak detector with the ADC. The tune block saves the setting with the largest
peak detector response and restores that setting at the end of the routine.
In a base station this tune requires that enough of the power amplifier output get back through the TX/RX
switch to be in the range of the peak detector.
The LNA load tuning procedure is:
1. Before initiating the automatic LNA load tuning procedure, perform the following setup through
the control interface:
–
Set the blocker peak detector input range to 100mV by writing 0x02 to the RF_TRIM_CTL
register (that is, set pd_range equal to 1).
–
Enable the LNA load tuning procedure by setting the lna_en_trim bit in the AUTO_TRIM_EN
register (that is, write 0x10 to the AUTO_TRIM_EN register). That forces the LNA load to
oscillate with negative resistance.
2. Then launch the LNA load tuning procedure and EITHER:
–
Wait for the appropriate interrupts if enabled.
–
Wait for time-out (approximately 3ms).
–
Poll the appropriate interrupt status registers or the appropriate trim registers.
3. At the end of the LNA load tuning procedure:
–
Disable the power amplifier by writing 0x00 to the RF_EN6 register (that is, clear both
man_pa_en and man_pa_tx_en).
–
Set the internal LNA gain back to the default value by writing 0x07 to the LNA_GAIN_INT
register.
–
Set the power amplifier back to the default power setting by writing 0x08 to the RF_CTL4
register (that is, clear dac_scale_dwn and write 6’b001000 to pa_pwr_ctl).
–
If the trim_fail_irq status has been set by the tuning procedure, read the trim value in the
PD_TRIM register:
a. If the selected frequency range is at the high end of what the VCO can reach and the trim
value is at the lowest trim value, then there is no failure. The trim value is appropriate.
b. If the tune frequency selected is at the low end of what the VCO can reach and the trim
value is at the highest trim value, then there is no failure. The trim value is appropriate.
c. Check the best average value of the ADC during the tuning (the LNA_BEST_ADC register
at address 0x7A). If the value is below 0x05 then an error may exist. The antenna may not
be connected properly, or the power amplifier output or LNA gain may need to be
increased.
d. Otherwise, the ZL70250 chip may be defective.
6.12 Enable Automatic Trimming of the VCO
After all calibrations are completed, set the incdec_modetrans_en bit in the CONT_TRIM_EN register to
enable the automatic trimming of the VCO by one bit after each transmitted or received packet.
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7 – ADC/AGC Controller
7.1
ADC_CTL4
The ADC_CTL4 register contains the value that controls how long the RSSI can be inactive before the
receive state machine terminates the current receive process. The default is set to 20 bit periods, or
about 100µs. If the RSSI falls below the RSSI threshold for a period greater than this delay, then the
receive operation does one of two things. In a bidirectional operation when the rssi_retry_en is false in
the MAC_CTL1 register, loss of RSSI causes the operation to switch to transmit. This is used on the
master timing device (link master). If rssi_retry_en is true, or if in multipacket receive only mode, loss of
RSSI causes the receive operation to restart.
7.2
ADC Modes
•
Select the ADC analog block input signal by writing the three-bit word adc_mux_in_sel in the
ADC_CTL1 register.
•
If the selected input of the ADC analog block is the blocker peak detector or RSSI, then select
whether the threshold interrupt pulse is generated on average value or peak value by writing the
peak_thresh_en bit in the ADC_CTL1 register. If another input is selected, then no threshold
interrupt pulse is generated.
•
If the selected input of the ADC analog block is either the blocker peak detector or the RSSI,
program the threshold value by writing the AGC_THRESH_PD register or the
AGC_THRESH_RSSI, respectively. That defines the level where the threshold interrupt pulse is
generated.
•
Enable the interrupts as appropriate in the IRQ_EN1 register.
•
Start a single conversion mode or a continuous conversions mode by writing the bits single_conv
or cont_conv respectively, in the ADC_CTL2 register. In the same write operation (or before) the
number of conversions can be selected (from 1 to 2048) by writing to the same register
ADC_CTL2.
•
The registers ADC_RESULT, ADC_PEAK, and ADC_AVG can be read at any time. They always
contain their most up-to-date values (until RESET_B is set).
•
The single conversion mode stops automatically after 2pow_n_conv conversions. However, the
continuous conversions mode has to be stopped by resetting the cont_conv bit to 0 in the
ADC_CTL2 register.
•
In either case, single conversion mode or continuous conversions mode, the adc_done_irq is
generated after every 2pow_n_conv conversions (only once at the end of the single conversion
mode). This interrupt is latched in the IRQ1 register and this bit can be read at any time. If
enabled, an interrupt is generated when the adc_done_irq is latched.
•
Also in either case, single conversion mode or continuous conversions mode, the
adc_thresh_pd_irq pulse (if blocker peak detector is selected) or the adc_thresh_rssi pulse (if
RSSI is selected) can be generated after every 2pow_n_conv conversions. The generated pulse is
latched in the IRQ1 register and this bit can be read at any time. If enabled, an interrupt is
generated when either the adc_thresh_pd_irq or adc_thresh_rssi_irq pulse is latched.
Note: The presented ADC modes are interrupt driven but this operation can also be executed with no
interrupts. A read command of the ADC_RESULT or ADC_PEAK or ADC_AVG register can be
executed right after the write command to the single_conv or cont_conv bit that initiates the
conversion. This can be used in the case where no more than 16 conversions are performed
(pow_n_conv ≤ 4’b0100).
Note: In ADC modes, a delay of at least 40µs (typical) has to be taken into account when changing
adc_mux_in_sel or lna_gain_int before starting a conversion.
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7.3
AGC Modes
•
Select the threshold values by writing to the AGC_THRESH_PD register and the
AGC_THRESH_RSSI register. That defines the level where the ADC blocker peak detector
threshold interrupt pulse and the ADC RSSI threshold interrupt pulse, respectively, are generated.
•
Enable the interrupts as appropriate in the IRQ_EN1 register.
•
The LNA_GAIN_INT value is automatically controlled by the AGC finite state machine when an
AGC mode process is ongoing. Otherwise, its value is controlled through the control interface.
•
The LNA_GAIN_INT register can be read at any time, regardless of the mode it is in.
•
Write to the agc_manual_gain_en bit in the ADC_CTL1 to select whether the gain is fixed
manually or automatically adjusted by the AGC process.
•
If the default is not appropriate, define the number of clock cycles (sys_clk) that are necessary for
the LNA/RSSI to settle by writing the agc_wait_prg word in the ADC_CTL3 register.
•
Define the LNA search gain by writing to the lna_gain_search word in the LNA_GAIN_SEARCH
register.
•
Define the maximum LNA gain by writing to the lna_gain_max word in the LNA_GAIN_MAX
register.
•
Define the number of times that the RSSI has to be below the RSSI threshold value before
stopping the RSSI monitoring (used in the RSSI_MONITOR state) by writing to rssi_lost_cnt in
the ADC_CTL4 register. This delay is automatically inserted during the AGC modes.
•
Select the AGC mode (Mode 1 or 2) by writing to the agc_mode word in the ADC_CTL1 register.
•
The registers AGC_RESULT_PD and AGC_RESULT_RSSI can be read at anytime for diagnosis.
•
The ZL70250 interrupt register (IRQ1) and the ZL70250 status register (RF_STAT) can be read at
any time as appropriate:
•
–
The adc_thresh_pd_irq interrupt (the ADC blocker peak detector threshold interrupt) can be
generated after a conversion of the blocker peak detector output, when the
AGC_RESULT_PD register value is equal or greater than the AGC_THRESH_PD register
value.
–
The ADC RSSI threshold interrupt can be generated after a conversion of the RSSI output,
when the AGC_RESULT_RSSI register value is equal or greater than the
AGC_THRESH_RSSI register value.
–
The agc_nosig_irq interrupt (AGC no signal interrupt) can be generated during the
AGC_SEARCH state of the AGC Modes 1 and 3, if neither the ADC RSSI threshold interrupt
nor the ADC blocker peak detector threshold interrupt has been set.
When setting up a conversion mode, a new conversion cannot start while a conversion is already
taking place.
Figure 7-1 and Figure 7-2 (on pages 28 and 29) are state machine diagrams illustrating the behavior of
operation for the AGC modes (the diagram does not exactly represent the actual implementation).
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AGC_IDLE
AGC Mode 1
AND agc_en
AGC_SEARCH
! agc_en
(ADC on blocker and RSSI at
programmed lna_gain_int)
RSSI < RSSI threshold
RSSIRSSI threshold
RUN_AGC
Bypassed – No ADC
! agc_en
RSSI_MONITOR
(ADC on RSSI at
programmed lna_gain_int)
Æ agc_monitoring = 1
RSSIRSSI threshold
RSSI < RSSI threshold for rssi_lost_cnt
0020.265v1207.0
Figure 7-1 • AGC Mode 1 State Machine
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AGC_IDLE
AGC Mode 2
AND agc_en
AGC_SEARCH
Bypassed – No ADC
! agc_en
RUN_AGC
(ADC at all gains on RSSI, up to
lna_gain_max, lowest gain first)
Æ agc_running = 1
! agc_complete
agc_complete
! agc_en
RSSI_MONITOR
(ADC on RSSI at Current Gain)
Æ agc_monitoring = 1
RSSIRSSI threshold
RSSI < RSSI threshold for rssi_lost_cnt
0020.267v1207.0
Figure 7-2 • AGC Mode 2 State Machine
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8 – Clear Channel Assessment (CCA)
A clear channel assessment can be performed manually by executing ADC conversions on the RSSI
signal for the different channels. These ADC conversions can be performed either in single conversion
mode or in continuous conversions mode.
Typically, CCA is executed using the automatic functions of the MAC and the AGC controller. There are
two types of CCA: channel availability for finding an unused channel to start a session, and clear to send
for transmitting a packet on a selected channel.
8.1
Channel Availability
The channel availability function is used to find an unused channel. A channel is selected and listened to
for some period of time. If no activity is detected, the channel can be used for the session.
•
Tune to a potential clear channel.
•
Enable the threshold interrupt for the RSSI, adc_thresh_rssi_irq, by writing 0x02 to the IRQ_EN1
register.
•
Set lna_gain_search to its maximum (that is, write 0x0F to the LNA_GAIN_SEARCH register).
•
Set lna_gain_int to its maximum value (that is, write 0x0F to the LNA_GAIN_INT register).
•
Set up for AGC Mode 1 (that is, write 0x01 to the ADC_CTL1 register).
•
Start receive for multipacket by writing 0x63 to the MAC_CTL1 register.
•
Wait for some period for the interrupt.
–
If a time-out occurs before the interrupt, then use this channel.
–
Else, if there is an RSSI interrupt, go to the next channel. Continue until a channel is found
with no RSSI. Change to this new channel.
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9 – Channel Sniffing
Channel sniffing is used in conjunction with a long preamble. The receiving ZL70250 wakes up from a
power-down mode and listens for preamble. If there is no preamble (RSSI), it goes back to sleep. If the
RSSI level is greater than the RSSI threshold value, it performs AGC, adjusts DC, and receives the
packet.
9.1
Setup for Sniff and Receive Operation
For the receiving ZL70250, set up the registers the same as for a receive in "10.5.2.1 Setup for Receive
Mode" on page 43 or "10.5.3.3 Start Bidirectional Operation, Receive First (link slave)" on page 44. Also,
set up the following registers:
•
Set the value in the AGC_THRESH_RSSI register.
•
Enable the interrupts as desired by writing to the IRQ_EN1 and IRQ_EN2 registers.
•
Select whether the AGC mode is used in the ADC_CTL1 register.
The sniff operation can also be executed without an interrupt. A read command (of the
AGC_RESULT_RSSI or AGC_RESULT_PD register) can be executed after starting the AGC mode.
9.2
Start the Automatic Sniff and Receive Operation
•
Set the synthesizer frequency for the channel used.
•
Set up for receive multipacket ("10.5.2.3 Receive Multiple Packets" on page 43) by enabling the
threshold interrupt for the RSSI (that is, write 0x02 to the IRQ_EN1 register).
•
Use AGC Mode 2, which runs once with gain adjust (that is, write 0x02 to the ADC_CTL1
register).
•
Start receive by writing 0x6B to the MAC_CTL1 register.
•
If there is no RSSI, the ZL70250 automatically commands the MAC to power down. This is done
by the RX controller issuing a synchronous reset to MAC_CTL1.
•
If the RSSI is greater than or equal to the threshold, receive the packet:
–
This causes an RSSI interrupt to inform the processor that RX is in process.
–
If a second packet is expected:
-
Manually change to AGC Mode 1 (that is, write 0x01 to the ADC_CTL1 register).
-
Turn off auto-turn-off by clearing auto_off (that is, write 0x63 to the MAC_CTL1 register).
-
Start/resume receiving the packet.
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10 – MAC
10.1 Power States
Table 10-1 shows the power states of the ZL70250. To enter the SLEEP state, clear the sys_clk_en,
osc_en, and clk_out_en bits by writing 0x00 to the CLK_ENS register.
Table 10-1 • Power Modes and Associated Functions
Registers
XTAL Oscillator
and sys_clk
PLL
TX Blocks
RX Blocks
SLEEP
On
Off
Off
Off
Off
IDLE
On
On
Off
Off
Off
ACTIVE TX
On
On
On
On
Off
ACTIVE RX
On
On
On
Off
On
Power Mode
10.2 MAC Bit Descriptions
1. auto_txrx_en: Set high to allow the MAC to control the RF section for configuring for transmit and
receive. For transmit, setting auto_txrx_en high allows the MAC to enable the power amplifier and
the RF TX section and to set the VCO to the transmit frequency. For receive, setting auto_txrx_en
high allows the MAC to enable the RF RX section and to set the VCO to the receive frequency.
2. port_en: Set high to enable of the MAC. Setting port_en low is an synchronous reset to all MAC
counters and state machines. Setting port_en low does not reset the values in the MAC control
interface registers.
3. receive_en: Set high to enable the receive section of the MAC. It must be high for receive
operation to occur. It is used in conjunction with the TXRX_CMD pin to start a receive operation.
4. transmit_en: Set high to enable the transmit operation. When auto_txrx_en is also high, setting
transmit_en high also allows the MAC to enable the power amplifier, enable the RF modulator,
and control opening the PLL loop when in transmit mode.
5. auto_off: Set high to enable auto shutdown of the ZL70250. When enabled, the RX controller
resets MAC_CTL1 when there is no RSSI level detected at the end of AGC. By clearing
auto_txrx_en and port_en, the MAC is disabled and the analog/RF section is powered down,
including the PLL. Only the clock synthesizer remains active. For the power-down to be effective,
it is required that nothing in the RF/MAC section be manually enabled.
6. tx_first: Determines whether the first operation is transmit or receive in bidirectional operation.
When set high, the first operation is transmit.
7. rssi_retry_en: Set high to allow the MAC to stay in receive mode when the wanted signal goes
below the RSSI threshold during a receive in bidirectional mode, instead of switching to transmit.
8. multi_pkt_en: Set high to allow the MAC to transfer multiple packets in either receive or transmit
mode. This bit is set low for single packet transmit or single packet receive. This bit must be high
for bidirectional operation.
9. tx_cnt_en and rx_cnt_en: Used to enable termination of transmit and receive operations using the
bit-count registers. If these bits are set high, then the termination of transmit or receive occurs
when the correct number of bits is transmitted from or to the external controller. If these bits are
set low, then transmit or receive is terminated with the transmit_en or receive_en controls going
low, or with a change to the TXRX_CMD pin input from the external controller.
10. rx_polarity_inv: Set high to invert the polarity of the received data.
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11. pream_sel: Selects the preamble pattern and the integration period for restoring DC. The
pream_sel bit is set low for the preamble pattern 8’b01010101 and the integration period of
12 sys_clk. The pream_sel bit is set high for the pattern 8’b11001100 and the integration period of
24 sys_clk.
12. white_en: Set high to allow the MAC to whiten data after the sync pattern during transmit, and to
dewhiten the data after the sync pattern during receive.
10.2.1
Notes on MAC Control Registers
When programming the MAC control registers MAC_CTL1 and MAC_CTL2, please note that:
•
The transmit_en bit is used to enable the transmit operation. If receive_en is also true (enabling
receive operation), then the operation switches to receive mode at the completion of the transmit
operation. For bidirectional operation, both transmit_en and receive_en must be high, as well as
multi_pkt_en. In bidirectional mode, set the tx_first signal high to transmit first. For unidirectional
TX-TX operation when receive_en is low, the TXRX_CMD pin input from the external controller is
used to start and stop transmit operations without entering into receive mode. The transmit
operation is always started by 0-to-1 transition on the TXRX_CMD pin after the delay defined by
the TX_DELAY register.
•
There are several ways to end a transmit operation. If tx_cnt_en is set high, then the transmit
operation ends when the TX bit counter has decremented to zero. If tx_cnt_en is low, then the
transmit operation ends when the TXRX_CMD pin goes low. The transmit operation is always
ended when transmit_en or port_en goes low.
•
The receive_en bit is used to enable the receive operation. If transmit_en is set low, then a
receive operation is started by receive_en high. In this case, when the TXRX_CMD pin goes high,
transmit mode is not entered. A receive operation may also be started when both receive_en and
transmit_en go high while tx_first is low. In bidirectional mode, the receive operation is started at
the end of the transmit operation.
•
There are three ways to end a receive operation. If rx_cnt_en is high, then the receive operation
ends when the RX bit count is complete. If rx_cnt_en is low, then the receive operation ends when
the TXRX_CMD pin goes high. The receive operation is always terminated if receive_en or
port_en goes low. Finally, if the RSSI level from the AGC goes low (signal lost) for a defined
period, then the receive process restarts and waits for the RSSI level to return.
•
The bits tx_cnt_en and rx_cnt_en are used to enable termination of transmit and receive
operations using the bit count registers. If these controls are disabled, then transmit and receive
are terminated with the transmit_en and receive_en controls, or with the TXRX_CMD pin input
from the external controller.
•
The auto_txrx_en bit is used to enable the MAC to control the RF/analog section during transmit
and receive operations. When auto_txrx_en is high, the same enables are set as in man_pll_en.
When auto_txrx_en is high, a change from transmit mode to receive mode causes the MAC to
turn off the RF TX section, to change the VCO frequency to RX, and to turn on the RF RX section.
Conversely, a change from receive mode to transmit mode causes the MAC to turn off the RF RX
section, to change the VCO frequency to TX, and to turn on the RF TX section (again, when
auto_txrx_en is high).
10.3 Timing Delays
There are several registers that control the timing in the ZL70250. This timing relates to the sequence of
internal operations required to transmit or receive packets. Microsemi recommends using either the
default values or the values listed in Table 11-1 on page 47, which were tested and chosen for optimal
system performance.
Figure 10-1 on page 34 illustrates the start-up sequence for a single transmit operation. When the
transmit_en bit is set in MAC_CTL1, the pll_delay delays the start of the transmit state machine.
Figure 10-2 on page 34 illustrates the start-up sequence of a single receive operation. Similarly, if the
receive_en bit is set, the pll_delay delays the start of the receive state machine. In a multipacket
operation, this delay is only active on the first packet.
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TXRX_CMD
transmit_en
TX_DELAY ~500 μs
pll_delay ~2000 μs
tx_sm_en
IDLE_DELAY
~300 μs
pwr_amp_en
PA_DELAY
~200 μs
SLO_DELAY
~100 μs
pll_slow
white_en
Active
SPI_CLK
tx_data
No-mod
Preamble
pream_cnt
Correlation
TX Data
0019.288v1207.0
Figure 10-1 • Transmit Startup
TXRX_CMD
receive_en
pll_delay ~2000 μs
rx_sm_en
AGC_DELAY
~300 μs
agc_en
RX_DELAY
~1369 μs
agc_running
AGC
agc_monitoring
auto_dc_res
arm_corr
Wait for Sync
sync_detect_irq
white_en
1200 μs
215 μs
Active
SPI_CLK
Preamble
rx_data
Correlation Pattern
RX Data
0019.268v1207.0
Figure 10-2 • Receive Startup
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10.4 Use of TXRX_CMD
The TXRX_CMD input is used to control packet transfers in the ZL70250. The behavior of the ZL70250
relative to TXRX_CMD depends on the mode of operation. This section describes the use of
TXRX_CMD for various modes of operation.
10.4.1
Transmit Startup in Bit-Count Mode
In bit-count mode, TXRX_CMD is used to control the beginning of the packet transfer with extended or
minimum preamble.
•
To extend the preamble, delay the assertion of TXRX_CMD. See Figure 10-3.
i.
To start a transmit operation, enable transmit as described in "10.5.1 Transmit Mode" on
page 42.
ii. Wait a minimum of 2000µs (pll_delay plus a minimum of 0µs).
iii. Pulse TXRX_CMD high for a minimum of 40µs.
•
To use the minimum preamble length, assert TXRX_CMD high prior to enabling transmit. See
Figure 10-4. The minimum preamble length is the value programmed in pream_cnt.
i.
Set TXRX_CMD high.
ii. To start a transmit operation, enable transmit as described in "10.5.1 Transmit Mode" on
page 42.
iii. Wait a minimum of 2040µs (pll_delay plus a minimum of 40µs).
iv. Set TXRX_CMD low.
Note that TXRX_CMD cannot be brought low until 2040µs after enabling transmit. This delay is
applicable only for the first packet in multiple-packet transfers. The actual start of the packet, as well as
the length of the preamble, can be controlled when TXRX_CMD is pulsed high.
40 μs
TXRX_CMD
transmit_en
auto_txrx_en
tx_en
TX_DELAY ~ 500 μs
pll_delay ~ 2000 μs
PA_DELAY
~ 500 μs
TXRX_STAT
tx_done_irq
TX Packet
SPI_DATA
No-mod Pream pream_cnt Sync
tx_data
TX Data
0018.272v1207.0
Figure 10-3 • Start of Transmit in Bit-Count Mode with Pulsed TXRX_CMD
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Figure 10-4 shows an example of the second case, where TXRX_CMD is initialized high. In this case,
the length of the preamble is controlled solely by pream_cnt, and the start of the packet is determined by
the series of programmable timers that sequence the start of the packet. The TXRX_CMD pin can be
lowered either: any time after 2040µs (the 2000-µs PLL delay plus 40µs), after TXRX_STAT is asserted,
or after tx_done_irq is asserted.
40 μs
TXRX_CMD
transmit_en
auto_txrx_en
pll_delay ~ 2000 μs
tx_en
PA_DELAY
~ 500 μs
TXRX_STAT
tx_done_irq
TX Packet
SPI_DATA
No-mod pream_cnt Sync
tx_data
TX Data
0018.268v1207.0
Figure 10-4 • Start of Transmit in Bit-Count Mode with TXRX_CMD Initialized High
If the ZL70250 is set up in bidirectional mode such that the next operation is a receive operation,
TXRX_CMD must be low before the internal signal agc_en is asserted. If the ZL70250 is not in
bidirectional mode and is set up to transmit only, TXRX_CMD can be left high until another packet needs
to be transmitted (pulsing TXRX_CMD low and then back high).
10.4.2
Transmit Startup in Non-Bit-Count Mode
To start a transmit operation in non-bit-count mode, TXRX_CMD is initialized high and remains high for
the duration of the packet. When TXRX_CMD goes low, the packet is terminated. See Figure 10-5. In this
mode, TXRX_CMD can also be used to delay the start of the packet or increase the length of the
preamble. In this case, TXRX_CMD is initialized low and then raised when sufficient time has elapsed for
the desired preamble length and/or start of packet time.
TXRX_CMD
transmit_en
auto_txrx_en
tx_en
pll_delay ~ 2000 μs
PA_DELAY
~ 500 μs
TXRX_STAT
tx_done_irq
TX Packet
SPI_DATA
No-mod pream_cnt Sync
tx_data
TX Data
0018.269v1207.0
Figure 10-5 • Start of Transmit in Non-Bit-Count Mode
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10.4.3
Bidirectional Streaming in Bit-Count Mode
Figure 10-6 shows the use of TXRX_CMD in bidirectional streaming operation. TXRX_CMD is pulsed
high to start a transmit packet. The rate or interval at which TXRX_CMD is pulsed controls the bit rate of
the session. The major limitation of this mode is that TXRX_CMD cannot be pulsed before rx_done_irq is
asserted at the end of the receive operation. If TXRX_CMD goes high during the receive operation, the
receive packet is terminated early.
For bit-count mode, TXRX_CMD can be pulsed high after the rx_done_irq is asserted. TXRX_CMD can
be pulsed before or after rx_done_irq is cleared, but the time at which it is pulsed determines when the
next transmit packet starts.
40 μs
40 μs
TXRX_CMD
synth_tx
TXRX_STAT
tx_done_irq
agc_en
rx_done_irq
TX Packet
SPI_DATA
Pream-Sync
txrx_data
TX Packet
RX Packet
Pream-Sync
RX Packet
0018.267v1207.0
Figure 10-6 • Bidirectional Streaming in Bit-Count Mode
10.4.4
Bidirectional Streaming in Non-Bit-Count Mode
The use of TXRX_CMD in bidirectional non-bit-count mode is shown in Figure 10-7. In this mode,
TXRX_CMD is set high to transmit a packet, and set low to receive a packet. To control the data rate, the
raising of TXRX_CMD must be delayed, which prolongs the receive packet. In this case, extra receive
data is sent across the SPI and has to be discarded.
TXRX_CMD
synth_tx
TXRX_STAT
tx_done_irq
agc_en
rx_done_irq
TX Packet
SPI_DATA
txrx_data
Pream-Sync
TX Packet
RX Packet
Pream-Sync
RX Packet
0018.264v1207.0
Figure 10-7 • Bidirectional Streaming in Non-Bit-Count Mode
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10.4.5
Bidirectional Streaming with Mixed Bit-Count Mode
In some cases, such as CSMA (aka LBT) on the link master, it may be necessary to have the transmit
side operate in bit-count mode while the receive side operates in non-bit-count mode.
Figure 10-8 shows the use of TXRX_CMD in mixed bit-count mode. In this mode, TXRX_CMD is set high
to terminate the receive packet and to start the transmission of the next packet. Like the non-bit-count
mode, the only way to control the data rate is to delay raising TXRX_CMD, causing the receive operation
across the SPI to increase.
40 μs
TXRX_CMD
synth_tx
TXRX_STAT
tx_done_irq
agc_en
rx_done_irq
TX Packet
SPI_DATA
txrx_data
Pream-Sync
TX Packet
RX Packet
Pream-Sync
RX Packet
0018.263v1207.0
Figure 10-8 • Bidirectional Streaming in Mixed Bit-Count Mode
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10.4.6
Bidirectional Streaming Startup in Bit-Count Mode
Figure 10-9 shows the use of TXRX_CMD for starting a bidirectional streaming session in bit-count
mode, with transmit first. In this case, TXRX_CMD can be pulsed any time after the PLL delay to start the
first transmit packet. To start the next transmit packet, TXRX_CMD can be pulsed high at any time after
the completion of the receive packet.
40 μs
40 μs
TXRX_CMD
transmit_en
auto_txrx_en
pll_delay
~ 2000 μs
tx_en
synth_tx
TXRX_STAT
tx_done_irq
agc_en
rx_done_irq
TX Packet
SPI_DATA
RX Packet
0018.270v1207.0
Figure 10-9 • Bidirectional Streaming Startup in Bit-Count Mode
Figure 10-10 shows the alternative use of TXRX_CMD to start a bidirectional streaming session in bitcount mode. In this case, TXRX_CMD is initialized high and then lowered some time after the PLL delay.
The limit in this case is that TXRX_CMD must go low before the internal signal agc_en is asserted during
the receive operation. AGC_DELAY determines the interval from tx_done_irq to agc_en, which is
defaulted to 300µs. The options for setting TXRX_CMD low after the first packet are: (1) wait for 2040µs
(the 2000-µs PLL delay plus 40µs), (2) wait for TXRX_STAT to go high, or (3) wait for tx_done_irq. If
waiting for tx_done_irq, then the time limitation to set TXRX_CMD low is the 300-µs AGC delay. In this
case, it may be necessary to set TXRX_CMD low before clearing tx_done_irq.
40 μs
40 μs
TXRX_CMD
transmit_en
auto_txrx_en
pll_delay
~ 2000 μs
AGC_DELAY ~ 300 μs
tx_en
synth_tx
TXRX_STAT
tx_done_irq
agc_en
rx_done_irq
SPI_DATA
TX Packet
RX Packet
0018.271v1207.0
Figure 10-10 • Bidirectional Streaming Startup in Bit-Count Mode, with TXRX_CMD High
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10.4.7
One-Direction Streaming TX-TX Startup in Bit-Count Mode
Figure 10-11 and Figure 10-12 show the use of TXRX_CMD for one-direction transmit operation in bitcount mode. Like the other transmit cases, TXRX_CMD can either be pulsed high after the PLL delay on
the first packet or it can be initialized high. Figure 10-11 shows the first case, with TXRX_CMD pulsed
high on the first packet after the PLL delay.
40 μs
40 μs
TXRX_CMD
transmit_en
auto_txrx_en
pll_delay
~ 2000 μs
tx_en
TXRX_STAT
tx_done_irq
TX Packet
SPI_DATA
TX Packet
0018.281v1207.0
Figure 10-11 • One Direction Streaming TX-TX Startup in Bit-Count Mode
Figure 10-12 shows the preferred method of pulsing TXRX_CMD low and back high to start a new
transmit packet. In this case, the pulse can be delayed to lengthen the preamble and/or delay the next
transmit packet for controlling the data rate.
40 μs
TXRX_CMD
transmit_en
auto_txrx_en
pll_delay
~ 2000 μs
tx_en
TXRX_STAT
tx_done_irq
SPI_DATA
TX Packet
TX Packet
0018.285v1207.0
Figure 10-12 • One Direction Streaming TX-TX Startup in Bit-Count Mode
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10.4.8
One-Direction Streaming TX-TX Startup in Non-Bit-Count
Mode
Figure 10-13 shows the use of TXRX_CMD in one-way streaming transmit operation in non-bit-count
mode. TXRX_CMD is set low to terminate the transmit packet, and set high again to start the next
transmit packet. Setting TXRX_CMD high can be delayed to lengthen the preamble and/or delay the next
transmit packet for controlling the data rate.
40 μs
TXRX_CMD
transmit_en
auto_txrx_en
pll_delay
~ 2000 μs
tx_en
TXRX_STAT
tx_done_irq
TX Packet
SPI_DATA
TX Packet
0018.282v1207.0
Figure 10-13 • One Direction Streaming TX-TX Startup in Non-Bit-Count Mode
10.4.9
One-Direction Streaming RX-RX Startup in Bit-Count Mode
Figure 10-14 shows the use of TXRX_CMD for one-direction streaming receive operation in bit-count
mode. In bit-count mode, TXRX_CMD can be initialized low and left low for the entire session.
TXRX_CMD
receive_en
auto_txrx_en
pll_delay
~2000 μs
rx_en
synth_tx
AGC_DELAY ~300 μs
TXRX_STAT
agc_en
rx_done_irq
SPI_DATA
RX Packet
RX Packet
0018.284v1207.0
Figure 10-14 • One Direction Streaming RX-RX Startup in Bit-Count Mode
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10.4.10 One-Direction Streaming RX-RX Startup in Non-Bit-Count
Mode
Figure 10-15 shows the use of TXRX_CMD for one-direction streaming receive operation in non-bitcount mode. In this mode, TXRX_CMD must be pulsed high to terminate the receive packet. The time
that TXRX_CMD is high is limited to the AGC delay.
40 μs < pulse width < 300 μs
TXRX_CMD
receive_en
auto_txrx_en
pll_delay
~2000 μs
rx_en
synth_tx
AGC_DELAY ~300 μs
TXRX_STAT
agc_en
rx_done_irq
RX Packet
SPI_DATA
RX Packet
0018.283v1207.0
Figure 10-15 • One Direction Streaming RX-RX Startup in Non-Bit-Count Mode
10.5 Packet Transfer Operations
10.5.1
Transmit Mode
10.5.1.1
Setup for Transmit Mode
To set up for transmit operation, configure the following:
•
•
If using bit-count mode:
–
Set the bit count tx_cnt by writing to the TX_CNT1 (LSB) and TX_CNT2 (MSB) registers.
–
Set the tx_cnt_en bit in the MAC_CTL2 register.
If whitening data, set the white_en bit in the MAC_CTL2 register.
10.5.1.2
Transmit One Packet
After setting up for transmit mode, perform the following sequence to transmit a single packet:
•
Set the TXRX_CMD pin low.
•
Set bits auto_txrx_en, transmit_en, and port_en by writing 0x25 to the MAC_CTL1 register.
•
Set the TXRX_CMD pin high when ready to send a packet.
•
When the transmission is complete, write 0x00 to the MAC_CTL1 register.
•
Set the TXRX_CMD pin low.
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10.5.1.3
Transmit Multiple Packets
After setting up for transmit mode, perform the following sequence to transmit multiple packets:
•
Set the TXRX_CMD pin low.
•
Set bits multi_pkt_en, auto_txrx_en, transmit_en, and port_en by writing 0x65 to the MAC_CTL1
register.
•
Set the TXRX_CMD pin high when ready to send the first packet.
•
When the transmission is complete, toggle the TXRX_CMD pin low for a minimum of 40µs and
then back high when ready to send the next packet.
•
Repeat the previous step until all packets are sent.
•
When the transmission is complete on the last packet, write 0x00 to the MAC_CTL1 register.
•
Set the TXRX_CMD pin low.
10.5.2
Receive Mode
10.5.2.1
Setup for Receive Mode
To set up for receive operation, configure the following:
•
•
If using bit-count mode:
–
Set the bit count rx_cnt by writing to the RX_CNT1 (LSB) and RX_CNT2 (MSB) registers.
–
Set the rx_cnt_en bit in the MAC_CTL2 register.
If whitening data, set the white_en bit in the MAC_CTL2 register.
10.5.2.2
Receive One Packet
After setting up for receive mode, perform the following sequence to receive a single packet:
•
Set the TXRX_CMD pin low.
•
Set bits auto_txrx_en, receive_en, and port_en by writing 0x23 to the MAC_CTL1 register.
•
When the packet has been received, write 0x00 to the MAC_CTL1 register.
10.5.2.3
Receive Multiple Packets
After setting up for receive mode, perform the following sequence to receive multiple packets:
•
Set the TXRX_CMD pin low.
•
Set bits multi_pkt_en, auto_txrx_en, receive_en, and port_en by writing 0x63 to the MAC_CTL1
register.
•
When a packet has been received, toggle the TXRX_CMD pin high for 40µs and then back low.
(This step is not necessary in bit-count mode.)
•
Repeat the previous step until all packets are received.
•
When the last packet has been received, write 0x00 to the MAC_CTL1 register.
10.5.2.4
Start Up Asynchronous Receive Session and Resume Receive
This method is used when a packet is expected to be received without a long preamble, so the receiver
may come up in the middle of a packet. This method allows resynchronization to the beginning of the
next packet. This can be used by a receiver to jump into a one-way audio session for example.
•
Set up for receive operation with the receiver not in auto-turn-off mode by clearing auto_off. See
"10.5.2.2 Receive One Packet".
•
Use AGC Mode 1, by writing 0x01 to ADC_CTL1 (see "7.3 AGC Modes" on page 27).
•
Set bits multi_pkt_en, auto_txrx_en, receive_en, and port_en by writing 0x63 to the MAC_CTL1
register.
With AGC Mode 1 operation, the following functionality is automatically performed:
1. If there is no RSSI and no blocker, then continue monitoring for an RSSI or blocker.
2. If the RSSI goes away, then restart the RX controller and AGC Mode 1 returns to monitoring for
an RSSI or blocker.
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10.5.3
Bidirectional Operation
10.5.3.1
Setup for Bidirectional Operation
To set up for bidirectional operation, configure the following:
•
•
If using bit-count mode:
–
Set the bit count tx_cnt by writing to the TX_CNT1 (LSB) and TX_CNT2 (MSB) registers.
–
Set the bit count rx_cnt by writing to the RX_CNT1 (LSB) and RX_CNT2 (MSB) registers.
–
Set the tx_cnt_en bit in the MAC_CTL2 register.
–
Set the rx_cnt_en bit in the MAC_CTL2 register.
If whitening data, set the white_en bit in the MAC_CTL2 register.
10.5.3.2
Start Bidirectional Operation, Transmit First (link master)
After setting up for bidirectional operation, perform the following sequence to start bidirectional operation
by sending a packet(s):
•
Set the TXRX_CMD pin low.
•
Set bits multi_pkt_en, auto_txrx_en, tx_first, transmit_en, receive_en, and port_en by writing
0x77 to the MAC_CTL1 register.
•
Toggle the TXRX_CMD pin high for 40µs when ready to send the first packet (after the PLL
delay).
•
Wait to receive the next packet.
•
Toggle the TXRX_CMD pin high for 40µs when ready to send the next packet.
•
Repeat the previous two steps until all packets are transferred.
•
When the last packet has been transferred, disable the MAC by writing 0x00 to the MAC_CTL1
register.
10.5.3.3
Start Bidirectional Operation, Receive First (link slave)
After setting up for bidirectional operation, perform the following sequence to start bidirectional operation
by receiving a packet(s):
•
Set the TXRX_CMD pin low.
•
Set bits rssi_retry_en, multi_pkt_en, auto_txrx_en, transmit_en, receive_en, and port_en by
writing 0xE7 to the MAC_CTL1 register.
•
When a packet has been received, set the TXRX_CMD pin high.
•
When a packet has been transmitted, set the TXRX_CMD pin low.
•
Repeat the previous two steps until all packets are transferred.
•
When the last packet has been transferred, disable the MAC by writing 0x00 to the MAC_CTL1
register.
10.5.4
Transmit or Receive Operation Abort
To manually abort a receive or transmit operation, write 0x00 to the MAC_CTL1 register. This resets the
MAC state machines and counters, halts SPI_CLK, and de-asserts SPI_SEL_B. It also powers down the
analog/RF section.
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10.6 Data Formats
The setup of the MAC, AGC/ADC, and interrupts is the same for PCM operation as it is for SPI operation.
The internal operations of ZL70250 behave the same for both modes of operation, with the only
difference being in the operation of the external signals on the SPI/PCM bus.
Table 10-2 defines the signals for the different modes of operation on the SPI/PCM bus.
Table 10-2 • ZL70250 Data Signal Cross-Reference
Data Formats
ZL70250 Pin Name
SPI
PCM
I2S
SPI_CLK
SCK
PCM_CLK
SCK
SPI_SEL_B
SS_n
PCM_SYNC
WS
SPI_DATA_IN
SOMI
PCM_IN
SDI
SPI_DATA_OUT
SIMO
PCM_OUT
SDO
The registers PCM_CTL and FRM_SIZE control the mode of operation on the SPI/PCM bus. In PCM
mode, when wide sync is selected, the frame size defines the number of bits between the
PCM_SYNC/WS transitions. When wide sync is not selected, the frame size defines the number of bits
between the PCM_SYNC/WS pulses. See the memory map for the definition of the control bits.
For detailed timing information, refer to the ZL70250 Data Sheet.
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11 – System Memory Map
The ZL70250 system memory map (in Table 11-1 on page 47, and in Table 11-2 through Table 11-87 on
pages 50 through 70) contains the address for each register, the bit definitions for the register contents,
and some programming notes when appropriate. If not all bits are used, the unused bits are read-only
and always return a value of zero. All writable bits can be read back at the same address and bit location
as written. For values that are longer than eight bits, multiple register addresses are used and the LSB is
in the lowest address register.
The register bits fall into the following categories.
•
Write and Read (R/W). These bits can be written from the control interface and read back.
•
Read only (R). These bits are read-only from the control interface and are not cleared on read.
•
Clear on Read (CoR). These bits are cleared to zero when read from the control interface.
•
Write, Read, Clear on Done (R/W/CoD). These are command bits that are set to start a
command. The current state of the bit can be read any time without affecting the bit value. The bit
is cleared automatically when the operation of the command is complete.
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11.1 Address Space
Table 11-1 • Memory Map
Address
(Decimal)
Address
(Hexadecimal)
Name
R/W
Reset Value
(Hexadecimal)
Recommended
Value (Note 1)
0
0x00
DEV_ID
R/W
0x45
1
0x01
APP_ID
R/W
0xFF
4
0x04
CLK_ENS
R/W
0x03
5
0x05
SSI_CTL
R/W
0x03
6
0x06
IRQ_EN2
R/W
0x00
7
0x07
IRQ_EN1
R/W
0x00
8
0x08
ADC_CTL1
R/W
0x00
9
0x09
MAC_CTL1
R/W
0x00
10
0x0A
MAC_CTL2
R/W
0x40
11
0x0B
RF_EN1
R/W
0x00
12
0x0C
RF_EN2
R/W
0x0F
15
0x0F
RF_EN5
R/W
0x00
16
0x10
RF_EN6
R/W
0x00
18
0x12
RF_CTL2
R/W
0x04
0x06
19
0X11
RF_CTL3
R/W
0X07
0x0F
20
0x14
RF_CTL4
R/W
0x08
21
0x15
RF_CTL5
R/W
0x6F
0x6B
23
0x17
RF_CTL7
R/W
0x0D
0x08
24
0x18
RF_TRIM_CTL
R/W
0x00
32
0x20
IREF_TRIM
R/W
0x0F
33
0x21
XO_TRIM
R/W
0x26
34
0x22
PRESC_TRIM
R/W
0x02
0x01 (Note 2)
35
0x23
MOD_DAC_TRIM
R/W
0x0F
0x1F
36
0x24
GAUS_TRIM
R/W
0x4A
0xC0
37
0x25
VCO_AMP_TRIM
R/W
0x3F
38
0x26
ANT_TRIM
R/W
0x16
39
0x27
PD_TRIM
R/W
0x14
40
0x28
LNA_TRIM1
R/W
0x16
41
0x29
LNA_TRIM2
R/W
0x05
0x0A
Notes:
1. Use this recommended initial register setting by writing this value after every chip reset. Device characterization
has shown that the recommended value gives better system performance.
2. Value valid for most frequencies. A value of 0x00 should be used for frequencies near the 800-MHz range. A
value of 0x20 should be used for operating frequencies near 965 MHz.
3. It is recommended that the default value (or reset value) be used. Do not write to this register.
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Table 11-1 • Memory Map (continued)
Address
(Decimal)
Address
(Hexadecimal)
Name
R/W
Reset Value
(Hexadecimal)
Recommended
Value (Note 1)
44
0x2C
ADC_CTL2
R/W/CoD
0x00
45
0x2D
ADC_CTL3
R/W
0x30
46
0x2E
ADC_CTL4
R/W
0x14
47
0x2F
LNA_GAIN_INT
R/W
0x07
49
0x31
LNA_GAIN_SEARCH
R/W
0x07
0x0F
50
0x32
LNA_GAIN_MAX
R/W
0x07
0x0F
51
0x33
AGC_THRESH_PD
R/W
0x08
0x1F
52
0x34
AGC_THRESH_RSSI
R/W
0x08
53
0x35
ADC_RESULT
R
0x00
54
0x36
AGC_RESULT_PD
R
0x00
55
0x37
AGC_RESULT_RSSI
R
0x00
56
0x38
ADC_PEAK
R
0x00
57
0x39
ADC_AVG
R
0x00
60
0x3C
PCM_CTL
R/W
0x00
61
0x3D
FRM_SIZE
R/W
0x20
62
0x3E
TIME_CNT
R/W
0x00 (Note 3)
63
0x3F
PLL_DELAY1
R/W
0x74 (Note 3)
64
0x40
PLL_DELAY2
R/W
0x01 (Note 3)
65
0x41
IDLE_DELAY
R/W
0x38 (Note 3)
66
0x42
PA_DELAY
R/W
0x25 (Note 3)
67
0x43
TX_DELAY
R/W
0x5D (Note 3)
68
0x44
SLO_DELAY
R/W
0x13 (Note 3)
69
0x45
AGC_DELAY
R/W
0x38 (Note 3)
70
0x46
RX_DELAY
R/W
0x38
71
0x47
TX_CNT1
R/W
0xFF
72
0x48
TX_CNT2
R/W
0xFF
73
0x49
RX_CNT1
R/W
0xFF
74
0x4A
RX_CNT2
R/W
0xFF
81
0x51
PREAM_CNT1
R/W
0x0A
82
0x52
PREAM_CNT2
R/W
0x00 (Note 3)
85
0x55
ADJ_FAST
R/W
0x03
0xFF
0x1D
0x05
Notes:
1. Use this recommended initial register setting by writing this value after every chip reset. Device characterization
has shown that the recommended value gives better system performance.
2. Value valid for most frequencies. A value of 0x00 should be used for frequencies near the 800-MHz range. A
value of 0x20 should be used for operating frequencies near 965 MHz.
3. It is recommended that the default value (or reset value) be used. Do not write to this register.
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Table 11-1 • Memory Map (continued)
Address
(Decimal)
Address
(Hexadecimal)
Name
R/W
Reset Value
(Hexadecimal)
Recommended
Value (Note 1)
86
0X56
ADJ_SLOW
R/W
0x07
0x0A
93
0x5D
MAC_DOUT0
R/W
0x00
0x40
94
0x5E
MAC_DOUT1
R/W
0x00
95
0x5F
SYNTH_CH_MDIV
R/W
0xB5
96
0x60
SYNTH_CH_ADIV
R/W
0x07
97
0x61
SYNTH_CTL
R/W
0x07
101
0x65
SYS_CLK_DIV
R/W
0x16
102
0x66
CLK_OUT_DIV
R/W
0x18
103
0x67
PLL_CLK_DIV
R/W
0x51
105
0x69
IRQ1
CoR
0x00
107
0x6B
IRQ2
CoR
0x00
108
0x6C
RF_STAT
R
0x00
109
0x6D
AUTO_TRIM_EN
R/W/CoD
0x00
110
0x6E
CONT_TRIM_EN
R/W
0x00
111
0x6F
VFT_RX_L
R/W
0xB4
112
0x70
VFT_RX_H
R/W
0x05
113
0x71
VFT_PAOFF_L
R/W
0xB4
114
0x72
VFT_PAOFF_H
R/W
0x05
115
0x73
VFT_PAON_L
R/W
0xB4
116
0x74
VFT_PAON_H
R/W
0x05
117
0x75
VFT_L
R
0xB4
118
0x76
VFT_H
R
0x05
119
0x77
VCO_FRQ_CNT
R/W
0x2A
122
0x7A
LNA_BEST_ADC
R
0x00
123
0x7B
ANT_BEST_ADC
R
0x00
124
0x7C
RF_CTL8
R/W
0x20
Notes:
1. Use this recommended initial register setting by writing this value after every chip reset. Device characterization
has shown that the recommended value gives better system performance.
2. Value valid for most frequencies. A value of 0x00 should be used for frequencies near the 800-MHz range. A
value of 0x20 should be used for operating frequencies near 965 MHz.
3. It is recommended that the default value (or reset value) be used. Do not write to this register.
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11.2 Control Interface Registers
Table 11-2 • DEV_ID (Address 0x00)
Bit
Bit Definition
7:0
ssi_did
Description
Control interface device ID
Type
Reset Value
R/W
01000101
Type
Reset Value
R/W
11111111
Type
Reset Value
R
00000
Table 11-3 • APP_ID (Address 0x01)
Bit
Bit Definition
7:0
ssi_app_did
Description
Application ID
Table 11-4 • CLK_ENS (Address 0x04)
Bit
Bit Definition
7:3
–
Description
<Reserved>
2
sys_clk_en
Enable the frequency divider that generates the system
clock sys_clk going to the MAC
R/W
0
1
clk_out_en
Enable the frequency divider that generates the external
clock
R/W
1
0
osc_en
Enable XTAL oscillator
R/W
1
Type
Reset Value
R
000000
Table 11-5 • SSI_CTL (Address 0x05)
Bit
Bit Definition
7:2
–
Description
<Reserved>
1
wr_auto_incr
Write autoincrement
R/W
1
0
rd_auto_incr
Read autoincrement
R/W
1
Type
Reset Value
R
00000
Enable PLL globally; turns on all blocks related to PLL
R/W
0
11.3 Global Enables Register
Table 11-6 • RF_EN1 (Address 0x0B)
Bit
Bit Definition
7:3
–
Description
<Reserved>
2
man_pll_en
1
man_rcvr_en
Enable receive channel globally; turns on all blocks
needed for receiver operation
R/W
0
0
man_xmtr_en
Enable transmit channel; turns on all blocks needed for
transmitter operation
R/W
0
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11.4 Analog Enables Registers
Table 11-7 • RF_EN2 (Address 0x0C)
Bit
Bit Definition
7:4
–
3
2
1
0
amx3_short_en
Description
<Reserved>
Short the input of Test Buffer 3 to the output
amx3_pulldown_en Pull down the test pin AMX3
amx2_short_en
Short the input of Test Buffer 2 to the output
amx2_pulldown_en Pull down the test pin AMX2
Type
Reset Value
R
0000
R/W
1
R/W
1
R/W
1
R/W
1
Note: For recommended initial register setting, see "Recommended Value" column of Table 11-1 on page 47.
Table 11-8 • RF_EN5 (Address 0x0F)
Bit
Bit Definition
Description
Type
Reset Value
Enable ADC analog block
R/W
0
Enable AGC
R/W
0
Enable FM detector
R/W
0
7
man_adc_ana_en
6
man_agc_en
5
man_fm_det_en
4
man_rssi_en
Enable RSSI
R/W
0
3
man_limit_en
Enable limiter
R/W
0
2
man_if_filt_en
Enable IF filter
R/W
0
1
man_pd_en
Enable blocker peak detector
R/W
0
0
man_rf_en
Enable mixer and enable LNA
R/W
0
Type
Reset Value
R
00000
R/W
0
Enable transmit mode of power amplifier
R/W
0
Enable power amplifier
R/W
0
Table 11-9 • RF_EN6 (Address 0x10)
Bit
Bit Definition
7:3
–
2
Description
<Reserved>
man_mod_dac_en Enable the modulator DAC
1
man_pa_tx_en
0
man_pa_en
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11.5 Analog Control Registers
Table 11-10 • RF_CTL2 (Address 0x12)
Bit
Bit Definition
7:3
–
2
if_filt1stage
1
gaus_bypass
0
man_gaus_mod
Description
Type
Reset Value
R
00000
Set IF filter to single-stage mode. The receiver IF filter
has two stages, each a third-order Butterworth
bandpass. The first stage should be used for most
applications unless a very large adjacent channel is
present.
R/W
1
When high, the Gaussian filter is bypassed.
R/W
0
The Gaussian filter shapes the modulating signal going
from the modulation DAC to the VCO so that the output
spectrum is reduced in bandwidth.
R/W
0
<Reserved>
Note: For recommended initial register setting, see "Recommended Value" column of Table 11-1 on page 47.
Table 11-11 • RF_CTL3 (Address 0x13)
Bit
Bit Definition
7:4
–
3:0
pump_ioutsel
Description
Type
Reset Value
<Reserved>
R/W
0000
Output current setting
R/W
0111
Type
Reset Value
R
0
Enable DAC scale down by one half
R/W
0
Power amplifier output power; see Note
R/W
001000
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-12 • RF_CTL4 (Address 0x14)
Bit
Bit Definition
7
–
6
dac_scale_dwn
5:0
pa_pwr_ctl
Description
<Reserved>
Note: Warning: Power output depends on the impedance of the load. The power amplifier is designed for current
output into a tuned load of approximately 1kΩ. Care must be taken that the output voltage does not clip and that
the output voltage does not cross talk back to the VCO through the supplies. This can cause instability and
unpredictable behavior.
Table 11-13 • RF_CTL5 (Address 0x15)
Bit
Bit Definition
7:5
pa_feedback_bias
4:3
pa_feedback_gain
2
pa_feedback_en
1
pa_bias_mode
0
pa_drive_en
Description
Type
Reset Value
Power amplifier feedback bias
R/W
011
Power amplifier feedback gain
R/W
01
Enable power amplifier feedback
R/W
1
Power amplifier bias mode. When low, the differential
power amplifier is more balanced, reducing even
harmonic distortion. This slightly reduces the maximum
output power.
R/W
1
Enable power amplifier drive
R/W
1
Note: For recommended initial register setting, see "Recommended Value" column of Table 11-1 on page 47.
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Table 11-14 • RF_CTL7 (Address 0x17)
Bit
Bit Definition
7:5
–
4:3
vco_amp_ctl
2:0
kvco_ctl
Description
<Reserved>
Set the threshold for the VCO peak detector to set the
amplitude of the VCO output. Default value for
vco_amp_ctl results in a trimmed VCO amplitude of
350mV. The threshold and peak detector are used only
during VCO amplitude trim, so changes to the threshold
only affect the VCO amplitude after an amplitude trim is
performed.
•
00: Amplitude of 300mV.
•
01: Amplitude of 350mV.
•
10: Amplitude of 400mV.
•
11: Amplitude of 450mV.
VCO tuning bridge control. kvco_ctl is used to select the
gain of the varactor in the VCO. The higher the VCO
frequency, the higher this control should be set. If
kvco_ctl is 0, the varactor gain is automatically selected
by the VCO frequency trim bits.
Type
Reset Value
R
000
R/W
01
R/W
101
Note: For recommended initial register setting, see "Recommended Value" column of Table 11-1 on page 47.
Table 11-15 • RF_TRIM_CTL (Address 0x18)
Bit
Bit Definition
7:2
–
1
pd_range
Description
<Reserved>
Blocker peak detector control in trim mode:
•
0: Blocker peak detector input range of 50mV.
•
1: Blocker peak detector input range of 100mV.
Type
Reset Value
R
000000
R/W
0
R/W
0
Peak detector range is specified as the voltage into the
peak detector after LNA gain. The full-scale voltage out
of the peak detector is always 700mV, full scale for the
ADC.
0
iref_chop_trim_ctl
IREF chopper control in trim mode:
•
0: Chopper set to straight mode.
•
1: Chopper set to crossed mode.
iref_chop_trim_ctl swaps the inputs to the voltage
comparator used by the IREF trim. This is normally done
automatically by the trim and tune controller and is
available only for testing and debugging purposes.
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11.6 Trim Registers
Table 11-16 • IREF_TRIM (Address 0x20)
Bit
Bit Definition
7:5
–
4:0
iref_trim
Description
<Reserved>
IREF trimming code for the resistor for PTAT and
constant current generator; a higher trim code means a
higher resistor value (and lower current)
Type
Reset Value
R
000
R/W
01111
Type
Reset Value
R
00
R/W
100110
Type
Reset Value
R
000000
R/W
10
Type
Reset Value
R
000
R/W
01111
Table 11-17 • XO_TRIM (Address 0x21)
Bit
Bit Definition
7:6
–
5:0
xo_trim
Description
<Reserved>
Trimming code for crystal oscillator (0 for minimum
frequency; maximum value is 63)
Table 11-18 • PRESC_TRIM (Address 0x22)
Bit
Bit Definition
7:2
–
1:0
presc_bias_trim
Description
<Reserved>
Trimming code for prescaler bias current. A higher trim
code means more current and therefore higher speed of
operations.
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-19 • MOD_DAC_TRIM (Address 0x23)
Bit
Bit Definition
7:5
–
4:0
mod_dac_trim
Description
<Reserved>
Modulation index trimming code; a higher trim value
means wider VCO modulation (higher modulation index)
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-20 • GAUS_TRIM (Address 0x24)
Bit
Bit Definition
Description
Type
Reset Value
7:0
gaus_gm_trim
Tuning value of the Gaussian filter. The trim and tune
block writes this register with the same trim value used
for the IF filter and FM detector (after the FM detector
trim function), but the trim value should be set to 0xFF
for best system performance that still meets the 300kHz
channel restrictions. A higher trim value means wider
bandwidth.
R/W
01001010
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
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Table 11-21 • VCO_AMP_TRIM (Address 0x25)
Bit
Bit Definition
7:6
–
5:0
vco_amp_trim
Description
<Reserved>
Coarse tuning value of the VCO. Higher trim value
means a larger amplitude of oscillations in the VCO. The
default is at the highest level to make sure the VCO
starts. The trim and tune block should be used to trim the
amplitude to 300mV, 350mV, 400mV, or 450mV.
Type
Reset Value
R
00
R/W
111111
Type
Reset Value
R
000
R/W
10110
Type
Reset Value
R
000
R/W
10100
Type
Reset Value
R
000
R/W
10110
Type
Reset Value
R
0000
Table 11-22 • ANT_TRIM (Address 0x26)
Bit
Bit Definition
7:5
–
4:0
ant_trim
Description
<Reserved>
Adjustment value of capacitive load to center frequency
of antenna; higher trim value means larger capacitance
and lower tuning frequency for the antenna
Table 11-23 • PD_TRIM (Address 0x27)
Bit
Bit Definition
7:5
–
4:0
pd_trim
Description
<Reserved>
Blocker peak detector trimming code. This trim is for the
peak detector DC offset. Higher values cause positive
offset. The trim and tune block should be used to
automatically trim this block.
Table 11-24 • LNA_TRIM1 (Address 0x28)
Bit
Bit Definition
7:5
–
4:0
lna_frq_trim
Description
<Reserved>
LNA load tune code. The LNA load is an inductor that
should be tuned to obtain the highest gain from the LNA.
Higher trim values represent higher capacitance and
therefore lower resonant frequency. Use the trim and
tune block to automatically trim.
Table 11-25 • LNA_TRIM2 (Address 0x29)
Bit
Bit Definition
Description
7:4
–
3:2
lna_bias_trim
LNA bias tune code. LNA biases can be set higher to get
more gain on the receiver front-end, but more current is
used. The default is recommended when trying to stay
below 2mA for chip current consumption.
R/W
01
1:0
mix_bias_trim
Mixer bias tune code. Mixer biases can be set higher to
get more gain on the receiver front-end, but more current
is used. The default is recommended when trying to stay
below 2mA for chip current consumption.
R/W
01
<Reserved>
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11.7 ADC/AGC Registers
Table 11-26 • ADC_CTL1 (Address 0x08)
Bit
Bit Definition
7:5
adc_mux_in_sel
4
peak_thresh_en
Description
Type
Reset Value
R/W
000
R/W
0
<Reserved>
R/W
0
Enable fixed manual gain for the AGC modes. When
agc_manual_gain_en is high, the AGC mode is limited to
single ADC conversion only using lna_gain_int gain. If
agc_manual_gain_en is low, then the appropriate gain is
adjusted automatically according to the different AGC
modes.
R/W
0
Select the AGC mode, Mode 0, 1, 2, or 3:
R/W
00
In ADC mode, ADC input selection:
•
000: None of the inputs are selected (analog mux
output floats).
•
001: AMX2 is selected. This should be used for the
mixer offset trim. The VDDTEST pin must be
connected to VDD or 3.5V to allow the analog test
bus to be used properly.
•
010: Blocker peak detector output is selected.
•
100: RSSI output (rx_rssi) is selected.
•
Others: If more than one bit is set, more than one
switch is turned on according to the input selection.
That is an illegal operation.
In ADC mode, select between average value and peak
value to trigger the ADC blocker peak detector threshold
interrupt or the ADC RSSI threshold interrupt. If set high,
peak is selected; if set low, average is selected.
See Note.
3
–
2
agc_manual_gain_en
1:0
agc_mode
•
00: Mode 0. Not recommended.
•
01: Mode 1. Run until the RSSI detected, without
gain adjust (manual gain control mode).
•
10: Mode 2. Run once with gain adjust.
•
11: Mode 3. Not recommended.
Note: The peak_thresh_en bit is ignored when the AGC mode is activated because only one conversion is done.
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Table 11-27 • ADC_CTL2 (Address 0x2C)
Bit
7
6:3
2
Bit Definition
–
pow_n_conv
agc_start
Description
<Reserved>
In ADC mode, determine the number of conversions
before updating the peak value (ADC_PEAK) and the
average value (ADC_AVG). It also determines when the
ADC interrupt pulses (ADC complete and ADC threshold
interrupts) are generated.
•
0000: 1 conversion.
•
0001: 2 conversions.
•
0010: 4 conversions.
•
0011: 8 conversions.
•
0100: 16 conversions.
•
0101 32 conversions.
•
0110: 64 conversions.
•
0111: 128 conversions.
•
1000: 256 conversions.
•
1001: 512 conversions.
•
1010: 1024 conversions.
•
1011 to 1111: 2048 conversions.
Reserved for use with AGC Mode 3 (not recommended).
Start a variant of AGC Mode 3. Measure the blocker and
RSSI at the gain set in lna_gain_search; if there is either
a blocker or RSSI above the threshold, then measure
the RSSI on all gains up to lna_gain_max (in the
LNA_GAIN_MAX register), lowest gain first.
Type
Reset Value
R
0
R/W
0000
R/W/CoD
0
R/W/CoD
0
R/W
0
See Note 1.
1
single_conv
Start single ADC conversion mode if set high. The first
conversion is automatically followed by 2pow_n_conv −1
other conversions in a row for the average value. Then
no more conversions take place.
See Note 2.
0
cont_conv
Start continuous ADC conversions mode if set high.
Single ADC conversions are continuously running.
See Note 2.
Notes:
1. The variant of AGC Mode 3 (controlled by agc_start) has the highest priority over the other AGC modes
(controlled by the internal signal agc_en).
2. The continuous ADC conversions mode has priority over the single ADC conversion mode, in the case where
they are both active. The AGC mode has priority over both continuous conversions mode and single conversion
mode.
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Table 11-28 • ADC_CTL3 (Address 0x2D)
Bit
Bit Definition
7
6:0
–
agc_wait_prg
Description
<Reserved>
Number of clock cycles (sys_clk) that are necessary for
the LNA/RSSI to settle after changing the gain
(lna_gain_int). This is also the number of clock cycles
that are necessary for the input to settle after changing
the input selection at adc_mux_in_sel.
Type
Reset Value
R
0
R/W
0110000
Type
Reset Value
R/W
00010100
Type
Reset Value
R
0000
R/W
0111
Type
Reset Value
R
0000
R/W
0111
The default represents 42.969µs.
Note: Programming 0x00 in the agc_wait_prg word
provides the same behavior as programming
0x01— that is to say, wait for one clock cycle
(sys_clk).
Table 11-29 • ADC_CTL4 (Address 0x2E)
Bit
Bit Definition
7:0
rssi_lost_cnt
Description
Number of times the RSSI has to be below the RSSI
threshold value before stopping the RSSI monitoring
(used in the RSSI_MONITOR state).
Note: Programming 0x00 in the rssi_lost_cnt word
provides the same behavior as programming
0x01— that is to say, one RSSI value below the
RSSI threshold value stops the RSSI monitoring.
Table 11-30 • LNA_GAIN_INT (Address 0x2F)
Bit
Bit Definition
7:4
–
3:0
lna_gain_int
Description
<Reserved>
Internal LNA gain.
The gain word is a thermometer code, where:
•
1111: Highest gain
•
0111
•
0011
•
0001
•
0000: Lowest gain
This word can be written manually or controlled by the
AGC.
Table 11-31 • LNA_GAIN_SEARCH (Address 0x31)
Bit
Bit Definition
7:4
–
3:0
lna_gain_search
Description
<Reserved>
LNA search gain. In the AGC_SEARCH state,
lna_gain_search is used for measuring both the blocker
and the RSSI.
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
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Table 11-32 • LNA_GAIN_MAX (Address 0x32)
Bit
Bit Definition
7:4
–
3:0
lna_gain_max
Description
Type
Reset Value
R
0000
R/W
0111
Type
Reset Value
R
000
R/W
01000
Type
Reset Value
R
000
R/W
01000
Type
Reset Value
<Reserved>
R
000
ADC result after each conversion. The result depends on
which input is selected from the ADC_CTL1 register (see
"7.2 ADC Modes" on page 26).
R
00000
Type
Reset Value
<Reserved>
R
000
ADC result after conversion of the blocker peak detector
output in AGC modes 1and 2 (see "7.2 ADC Modes" on
page 26)
R
00000
Type
Reset Value
<Reserved>
R
000
ADC result after conversion of the RSSI output (rx_rssi)
in AGC modes 1 and 2 (see "7.2 ADC Modes" on
page 26)
R
00000
<Reserved>
Maximum LNA gain. Gain adjustment in the RUN_AGC
state is limited to lna_gain_max unless there is no RSSI.
If there is no RSSI, then the AGC goes above
lna_gain_max to try to get the RSSI.
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-33 • AGC_THRESH_PD (Address 0x33)
Bit
Bit Definition
7:5
–
4:0
Description
<Reserved>
adc_thresh_pd_val Threshold value for the blocker peak detector
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-34 • AGC_THRESH_RSSI (Address 0x34)
Bit
Bit Definition
7:5
–
4:0
Description
<Reserved>
adc_thresh_rssi_val Threshold value for the RSSI
Table 11-35 • ADC_RESULT (Address 0x35)
Bit
Bit Definition
7:5
–
4:0
adc_result
Description
Table 11-36 • AGC_RESULT_PD (Address 0x36)
Bit
Bit Definition
7:5
–
4:0
pd_result
Description
Table 11-37 • AGC_RESULT_RSSI (Address 0x37)
Bit
Bit Definition
7:5
–
4:0
rssi_result
Description
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Table 11-38 • ADC_PEAK (Address 0x38)
Bit
Bit Definition
7:5
–
4:0
adc_peak
Description
Type
Reset Value
<Reserved>
R
000
ADC peak value over the last 2pow_n_conv conversions in
ADC mode
R
00000
Type
Reset Value
R
000
R
00000
Table 11-39 • ADC_AVG (Address 0x39)
Bit
Bit Definition
7:5
–
4:0
adc_avg
Description
<Reserved>
ADC average value over the last 2
conversions in ADC mode
pow_n_conv
11.8 MAC Registers
Table 11-40 • MAC_CTL1 (Address 0x09)
Bit
Bit Definition
Description
Type
Reset Value
7
rssi_retry_en
RSSI retry mode for RX bidirectional mode; enables RX
controller to stay in receive operation when the RSSI is
lost in bidirectional mode
R/W
0
6
multi_pkt_en
Enable auto multiple packets; enables bidirectional and
streaming unidirectional operation
R/W
0
5
auto_txrx_en
Enable auto TX-RX RF control; allows the MAC to
control the analog section for automatic packet transfers
R/W
0
4
tx_first
Transmit first in bidirectional mode
R/W
0
3
auto_off
Enable auto shutdown; enables autoreset of the MAC if
no RSSI is present
R/W
0
2
transmit_en
Enable transmit operations
R/W
0
1
receive_en
Enable receive operations
R/W
0
0
port_en
Enable the MAC; when 0, acts a synchronous reset to
the MAC
R/W
0
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Table 11-41 • MAC_CTL2 (Address 0x0A)
Bit
Bit Definition
Description
Type
Reset Value
7
white_en
Enable whitening in TX operation and dewhitening in RX
operation
R/W
0
6
pream_sel
Selects the preamble pattern and the integration period
for restoring DC:
R/W
1
Invert polarity of received data
R/W
0
•
0: preamble pattern of 8’b01010101 and integration
period of 12 sys_clk
•
1: preamble pattern of 8’b00110011 and integration
period of 24 sys_clk
5
rx_polarity_inv
4
tx_always
Enable continuous TX of packets, with no TXRX_CMD
activity
R/W
0
3
tx_random_all
Enable raw randomized data TX output, with no sync or
preamble
R/W
0
2
tx_random_data
Randomize TX data only; send preamble and sync
pattern
R/W
0
1
rx_cnt_en
Enable bit-count mode for receive operation
R/W
0
0
tx_cnt_en
Enable bit-count mode for transmit operation
R/W
0
Type
Reset Value
R
0000
R/W
0
R/W
0
R/W
0
R/W
0
Type
Reset Value
R
0
R/W
0100000
Table 11-42 • PCM_CTL (Address 0x3C)
Bit
Bit Definition
7:4
–
3
2
1
0
pcm_wide_sync
pcm_sync_inv
pcm_clk_inv
pcm_mode_sel
Description
<Reserved>
PCM wide sync:
•
0: Narrow
•
1: Wide
PCM sync invert:
•
0: Normal
•
1: Invert
PCM clock invert:
•
0: Normal
•
1: Invert
PCM mode select:
•
0: SPI
•
1: PCM
Table 11-43 • FRM_SIZE (Address 0x3D)
Bit
7
6:0
Bit Definition
–
frame_size
Description
<Reserved>
PCM frame size in bits
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Table 11-44 • TIME_CNT (Address 0x3E)
Bit
Bit Definition
Description
Type
Reset Value
7:0
time_cnt
Count interval for other timers – bit value. This counter is
a prescaler that drives the delay timers. It is driven by
the bit clock at sys_clk/6 (186,182Hz at 24.576MHz).
R/W
00000000
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-45 • PLL_DELAY1 (Address 0x3F)
Bit
Bit Definition
Description
Type
Reset Value
7:0
pll_delay[7:0]
PLL start-up delay, LSB, where delay is a function of the
pll_delay value and time_cnt. The PLL delay is
(time_cnt+1)×pll_delay×5.3711, assuming a crystal
frequency of 24.576MHz and sys_clk_div of 22.
R/W
01110100
Type
Reset Value
R
000000
R/W
01
Type
Reset Value
R/W
00111000
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-46 • PLL_DELAY2 (Address 0x40)
Bit
Bit Definition
7:2
–
1:0
pll_delay[9:8]
Description
Reserved
PLL start-up delay, MSB (see PLL_DELAY1)
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-47 • IDLE_DELAY (Address 0x41)
Bit
Bit Definition
7:0
idle_cnt
Description
Transmitter start-up delay, where delay is a function of
the idle_cnt value and time_cnt. The delay is
(time_cnt+1)×idle_cnt×5.3711, assuming a crystal
frequency of 24.576MHz and sys_clk_div of 22.
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-48 • PA_DELAY (Address 0x42)
Bit
Bit Definition
Description
Type
Reset Value
7:0
pwr_amp_cnt
TX power amplifier turn-on delay, where delay is a
function of the pwr_amp_cnt value and time_cnt. The
delay is (time_cnt+1)×pwr_amp_cnt×5.3711, assuming
a crystal frequency of 24.576MHz and sys_clk_div of 22.
R/W
00100101
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
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Table 11-49 • TX_DELAY (Address 0x43)
Bit
Bit Definition
Description
Type
Reset Value
7:0
tx_delay_cnt
TX preamble start delay, where delay is a function of the
tx_delay_cnt value and time_cnt. The delay is
(time_cnt+1)×tx_delay_cnt×5.3711, assuming a crystal
frequency of 24.576MHz and sys_clk_div of 22.
R/W
00111000
Type
Reset Value
R/W
00011100
Type
Reset Value
R/W
00111000
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-50 • SLO_DELAY (Address 0x44)
Bit
Bit Definition
7:0
slo_delay_cnt
Description
TX PLL slow delay, where delay is a function of the
slo_delay_cnt value and time_cnt. The delay is
(time_cnt+1)×slo_delay_cnt×5.3711, assuming a
crystal frequency of 24.576MHz and sys_clk_div of 22.
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-51 • AGC_DELAY (Address 0x45)
Bit
Bit Definition
7:0
rx_agc_cnt
Description
Receiver AGC start delay, where delay is a function of
the rx_agc_cnt value and time_cnt. The delay is
(time_cnt+1)×rx_agc_cnt×5.3711, assuming a crystal
frequency of 24.576MHz and sys_clk_div of 22.
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-52 • RX_DELAY (Address 0x46)
Bit
Bit Definition
Description
Type
Reset Value
7:0
rx_delay_cnt
RX DC restore off delay, where delay is a function of the
rx_delay_cnt value and time_cnt. The delay is
(time_cnt+1)×rx_delay_cnt×5.3711, assuming a crystal
frequency of 24.576MHz and sys_clk_div of 22.
R/W
00111000
Type
Reset Value
R/W
11111111
Type
Reset Value
R/W
11111111
Type
Reset Value
R/W
11111111
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-53 • TX_CNT1 (Address 0x47)
Bit
Bit Definition
7:0
tx_cnt[7:0]
Description
Transmit bit count – LSByte
Table 11-54 • TX_CNT2 (Address 0x48)
Bit
Bit Definition
7:0
tx_cnt[15:8]
Description
Transmit bit count – MSByte
Table 11-55 • RX_CNT1 (Address 0x49)
Bit
Bit Definition
7:0
rx_cnt[7:0]
Description
Receive bit count – LSByte
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Table 11-56 • RX_CNT2 (Address 0x4A)
Bit
Bit Definition
7:0
rx_cnt[15:8]
Description
Receive bit count – MSByte
Type
Reset Value
R/W
11111111
Type
Reset Value
R/W
00001010
Type
Reset Value
R/W
00000000
Type
Reset Value
R/W
00000011
Table 11-57 • PREAM_CNT1 (Address 0x51)
Bit
Bit Definition
7:0
pream_cnt[7:0]
Description
Preamble byte count – LSByte
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-58 • PREAM_CNT2 (Address 0x52)
Bit
Bit Definition
7:0
pream_cnt[15:8]
Description
Preamble byte count – MSByte
Note: It is recommended that the default value (or reset
value) be used. Do not write to this register.
Table 11-59 • ADJ_FAST (Address 0x55)
Bit
Bit Definition
7:0
adj_fast
Description
Threshold value for fast adjustment trigger during clock
recovery
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-60 • ADJ_SLOW (Address 0x56)
Bit
Bit Definition
Description
Type
Reset Value
7:0
adj_slow
Threshold value for slow adjustment trigger during clock
recovery
R/W
00000111
Note: For recommended initial register setting, see
"Recommended Value" column of Table 11-1 on
page 47.
Table 11-61 • MAC_DOUT0 (Address 0x5D)
Bit
Bit Definition
Description
Type
Reset Value
7
pdf_fir_bypass
Bypass FIR filters of data recovery
R/W
0
pdf_thresh_bypass Bypass threshold in the post-detection filter (see Note)
R/W
0
R
0
R/W
00000
6
5
4:0
–
dtbo_0_sel
Reserved
Select output for DOUT0; see Table 11-88 on page 70
Note: For recommended initial register setting, see "Recommended Value" column of Table 11-1 on page 47.
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Table 11-62 • MAC_DOUT1 (Address 0x5E)
Bit
7
Bit Definition
–
Description
Reserved
Type
Reset Value
R
0
6:5
pdf_test_ctrl
Select test input for data recovery and test input for postdetection filter
R/W
00
4:0
dtbo_1_sel
Select output for DOUT1; see Table 11-88 on page 70
R/W
00000
11.9 Synthesizer Registers
Table 11-63 • SYNTH_CH_MDIV (Address 0x5F)
Bit
Bit Definition
Description
Type
Reset Value
7:0
ch_m_div
M counter value — number of times the prescaler counts
to 16 within one phase comparison period
R/W
10110101
Table 11-64 • SYNTH_CH_ADIV (Address 0x60)
Bit
7
6
5:0
Bit Definition
Description
Type
Reset Value
ch_lo_ctl
Control whether the local oscillator (in RX) is set 606kHz
above the wanted channel or 606kHz below the wanted
channel. The choice of LO above or below channel is
influenced by where the possible interferers might be
and the fact that the ZL70250 does not include image
rejection.
R/W
0
R
0
R/W
000111
Type
Reset Value
R
0000
–
ch_a_div
•
1: LO above channel
•
0: LO below channel
<Reserved>
A counter value — number of times the prescaler counts
to 17 within one phase comparison period.
The A divider should be set greater than or equal to 5.
Table 11-65 • SYNTH_CTL (Address 0x61)
Bit
Bit Definition
7:4
–
Description
<Reserved>
3
synth_inv_ctl
Adjustment inversion control. The synth_inv_ctl bit
should not be changed. This controls the inversion of the
correction made to the PLL during modulation.
R/W
0
2
tx_mode_en
Enable TX mode:
R/W
1
•
1: TX mode.
•
0: RX mode (manual control via system bus).
Should be low for any RX mode and during VCO
frequency trimming for RX mode.
1
lo_offset_en
When high, LO offset adjustment is enabled. Controls
whether or not the LO (in RX) is offset by 606kHz from
the channel or not. This is used for debug or test.
R/W
1
0
pherr_accum_en
When high, phase-error accumulator is enabled.
Enables the circuitry that compensates the PLL for the
modulation during transmit.
R/W
1
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11.10 Clock Generator Registers
Table 11-66 • SYS_CLK_DIV (Address 0x65)
Bit
Bit Definition
7:5
–
4:0
sys_clk_div
Description
Type
Reset Value
R
000
R/W
10110
Type
Reset Value
R
000
R/W
11000
Type
Reset Value
R
0
R/W
1010001
Type
Reset Value
R
0
Enable synchronization detect interrupt
R/W
0
Enable trim done interrupt
R/W
0
Enable trimming and tuning process failed interrupt
R/W
0
<Reserved>
Set the divide ratio from the master clock (24.576MHz)
to the system clock, which runs the control interface and
other system functions.
Table 11-67 • CLK_OUT_DIV (Address 0x66)
Bit
Bit Definition
7:5
–
4:0
clk_out_div
Description
<Reserved>
Set the divide ratio from the master clock (24.576MHz)
to the CLK_OUT, which is an output from the ZL70250
IC to be used as a reference for other chips.
Table 11-68 • PLL_CLK_DIV (Address 0x67)
Bit
Bit Definition
7
6:0
–
pll_clk_div
Description
<Reserved>
Set the divide ratio from the master clock (24.576MHz)
to the PLL reference clock. The default is set for 303-kHz
channel spacing.
11.11 Interrupt Controller Registers
Table 11-69 • IRQ_EN1 (Address 0x07)
Bit
Bit Definition
Description
7
–
<Reserved>
6
sync_detect_irq_en
5
trim_done_irq_en
4
trim_fail_irq_en
3
adc_done_irq_en
Enable ADC done interrupt
R/W
0
2
agc_nosig_irq_en
Enable AGC no signal interrupt
R/W
0
1
adc_thresh_rssi_irq_en Enable threshold interrupt for the RSSI output (rx_rssi)
R/W
0
0
adc_thresh_pd_irq_en
R/W
0
Enable threshold interrupt for the blocker peak detector
output
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Table 11-70 • IRQ_EN2 (Address 0x06)
Bit
Bit Definition
7:4
–
Description
<Reserved>
Type
Reset Value
R
0000
3
rx_done_irq_en
Enable receive complete interrupt
R/W
0
2
tx_done_irq_en
Enable transmit complete interrupt
R/W
0
1
pll_lock_err_irq_en
Enable PLL error interrupt
R/W
0
0
sync_err_irq_en
Enable interrupt for no synchronization pattern found
during receive period
R/W
0
Type
Reset Value
R
0
Synchronization detect interrupt
CoR
0
Trim done interrupt
CoR
0
Trimming and tuning process failed interrupt
CoR
0
Table 11-71 • IRQ1 (Address 0x69)
Bit
Bit Definition
Description
7
–
<Reserved>
6
sync_detect_irq
5
trim_done_irq
4
trim_fail_irq
3
adc_done_irq
ADC done interrupt
CoR
0
2
agc_nosig_irq
AGC no signal interrupt
CoR
0
1
adc_thresh_rssi_irq
Threshold interrupt for the RSSI output (rx_rssi)
CoR
0
0
adc_thresh_pd_irq
Threshold interrupt for the blocker peak detector output
CoR
0
Type
Reset Value
R
0000
Table 11-72 • IRQ2 (Address 0x6B)
Bit
Bit Definition
7:4
–
Description
<Reserved>
3
rx_done_irq
Receive complete interrupt
CoR
0
2
tx_done_irq
Transmit complete interrupt
CoR
0
1
pll_lock_err_irq
PLL error (not locked) at startup of TX/RX interrupt
CoR
0
0
sync_err_irq
No synchronization pattern found during receive period
interrupt
CoR
0
Type
Reset Value
<Reserved>
R
00
Lock status of phase lock loop – not latched
R
0
R
0
R
0
VCO frequency comparator output status – not latched
R
0
Table 11-73 • RF_STAT (Address 0x6C)
Bit
Bit Definition
7:6
–
5
4
3
pll_lock_stat
iref_cmp_out_stat
Description
•
0: Open
•
1: Locked
IREF comparator output status – not latched
vco_amp_cmp_out_stat VCO amplitude comparator output status – not latched
2
vco_frq_cmp_out_stat
1
vco_hi_stat
Above PLL range status – not latched
R
0
0
vco_lo_stat
Below PLL range status – not latched
R
0
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11.12 Tune and Trim Registers
Table 11-74 • AUTO_TRIM_EN (Address 0x6D)
Bit
Type
Reset
Value
R
0
Enable tuning of IF filter and FM detector and Gaussian
filter (see Note)
R/W/CoD
0
Bit Definition
Description
7
–
<Reserved>
6
fm_det_en_trim
5
ant_en_trim
Enable tuning of antenna (see Note)
R/W/CoD
0
4
lna_en_trim
Enable tuning of LNA load (see Note)
R/W/CoD
0
3
pd_en_trim
Enable trimming of blocker peak detector offset (see
Note)
R/W/CoD
0
2
vco_amp_en_trim
Enable tuning of VCO amplitude (see Note)
R/W/CoD
0
1
vco_frq_en_trim
Enable tuning of VCO frequency (see Note)
R/W/CoD
0
0
iref_en_trim
Enable trimming of IREF (see Note)
R/W/CoD
0
Note: All bits in the AUTO_TRIM_EN register are cleared when the trim_done_irq signal is generated at the end of the
current tuning/trimming.
Table 11-75 • CONT_TRIM_EN (Address 0x6E)
Bit
Bit Definition
7:2
–
1
0
Description
<Reserved>
incdec_cnt_en
Enable the increment/decrement tuning of the VCO
frequency using an internal counter providing the
adjustment pulse.
incdec_modetrans_en Enable mode transition increment/decrement tuning of
the VCO frequency. Signal incdec_modetrans_en is
gated internally with auto_txrx_en. This tuning procedure
occurs only while in automatic mode or if incdec_cnt_en
is set.
Type
Reset Value
R
000000
R/W
0
R/W
0
Type
Reset Value
R/W
10110100
Type
Reset Value
R
00000
R/W
101
Type
Reset Value
R/W
10110100
Table 11-76 • VFT_RX_L (Address 0x6F)
Bit
Bit Definition
7:0
vco_frq_rx[7:0]
Description
VCO frequency tune LSB value for the RX mode
Table 11-77 • VFT_RX_H (Address 0x70)
Bit
Bit Definition
7:3
–
2:0
vco_frq_rx[10:8]
Description
<Reserved>
VCO frequency tune MSB value for the RX mode
Table 11-78 • VFT_PAOFF_L (Address 0x71)
Bit
7:0
Bit Definition
Description
vco_frq_txpaoff[7:0] VCO frequency tune LSB value for the TX mode (with
modulation off) with the power amplifier off (only bias on)
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Table 11-79 • VFT_PAOFF_H (Address 0x72)
Bit
Bit Definition
7:3
–
2:0
vco_frq_txpaoff[10:8]
Description
<Reserved>
VCO frequency tune MSB value for the TX mode (with
modulation off) with the power amplifier off (only bias on)
Type
Reset Value
R
00000
R/W
101
Type
Reset Value
R/W
10110100
Type
Reset Value
R
00000
R/W
101
Table 11-80 • VFT_PAON_L (Address 0x73)
Bit
Bit Definition
7:0
vco_frq_txpaon[7:0]
Description
VCO frequency tune LSB value for the TX mode (with
modulation off) with the power amplifier on
Table 11-81 • VFT_PAON_H (Address 0x74)
Bit
Bit Definition
7:3
–
2:0
vco_frq_txpaon[10:8]
Description
<Reserved>
VCO frequency tune MSB value for the TX mode (with
modulation off) with the power amplifier on
Table 11-82 • VFT_L (Address 0x75)
Bit
Bit Definition
Description
Type
Reset Value
7:0
vco_frq[7:0]
VCO frequency tune LSB value at output of multiplexer.
This register combined with VFT_H holds the VCO
frequency trim value for the mode (one of the three in the
previous six registers) that the chip is currently in.
R/W
10110100
Type
Reset Value
R
00000
R/W
101
Table 11-83 • VFT_H (Address 0x76)
Bit
Bit Definition
7:3
–
2:0
vco_frq[10:8]
Description
<Reserved>
VCO frequency tune MSB value at output of multiplexer
Table 11-84 • VCO_FRQ_CNT (Address 0x77)
Bit
Bit Definition
Description
Type
Reset Value
7:0
vco_frq_cnt
Counter value used for the increment/decrement tuning
of the VCO frequency. Multiplying this count value by
four sys_clk periods gives the time used between VCO
frequency trim updates (if selected).
R/W
00101010
Type
Reset Value
<Reserved>
R
000
Best (highest) value from the ADC during the latest LNA
tuning. For test or debug only.
R
00000
Table 11-85 • LNA_BEST_ADC (Address 0x7A)
Bit
Bit Definition
7:5
–
4:0
lna_best_adc
Description
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ZL70250 Programmer User’s Guide
Table 11-86 • ANT_BEST_ADC (Address 0x7B)
Bit
Bit Definition
7:5
–
4:0
ant_best_adc
Description
Type
Reset Value
<Reserved>
R
000
Best (highest) value from the ADC during the latest
antenna tuning. For test or debug only.
R
00000
Type
Reset Value
Bypass RSSI retry modification
R/W
0
R/W
0
R
1
Table 11-87 • RF_CTL8 (Address 0x7C)
Bit
Bit Definition
7
rssi_fix_bypass
6
chip_id1
Can be written but reserved for ID
5
chip_id0
Chip ID (always 1)
4
vref_nom
VREF to VCO frequency trim comparator (see Note)
R/W
0
3
vref_low
VREF to VCO frequency trim comparator (see Note)
R/W
0
VCO frequency control
R/W
000
2:0
vco_frq[13:11]
Description
Note: If vref_low is 0 and vref_nom is 0, then Vvco is 611mV (high threshold and default).
If vref_low is 0 and vref_nom is 1, then Vvco is 509mV (nominal).
If vref_low is 1 (and vref_nom is any value), then Vvco is 400mV (low).
Initial VCO frequency should be trimmed with 509-mV reference.
11.13 Data Port Test Modes
Use the values in Table 11-88 to select which signal is output to the DOUT0 and DOUT1 pins. Values are
valid for MAC_DOUT0 and MAC_DOUT1 registers; see Table 11-61 and Table 11-62 on page 65.
Table 11-88 • Data Port Test Modes
Value
Signal
Value
Signal
0x00
–
0x10
auto_dc_res
0x01
txrx_sel
0x11
arm_bit_sync
0x02
rx_en
0x12
arm_correlator
0x03
tx_en
0x13
sync_detect
0x04
pll_lock_err
0x14
sync_err
0x05
white_enbl
0x15
rx_done
0x06
clk_en
0x16
agc_en
0x07
xmtr_en
0x17
agc_running
0x08
pll_slow
0x18
agc_monitoring
0x09
tx_done
0x19
agc_rssi_high
0x0A
pdf_msbn_out
0x1A
adc_done
0x0B
pdf_rx_data
0x1B
agc_nosig
0x0C
rx_input_data
0x1C
adc_thresh_pd
0x0D
rx_spi_data
0x1D
adc_thresh_rssi
0x0E
bit_lock
0x1E
trim_ctrl
0x0F
rcvr_en
0x1F
tt_adj_frq_vco_trim
Revision 3
70
A – References
Document No.
Document Title
FCC Part 15 and the European pr ETS 300-220 regulatory documentation
Mil-Std-883 Method 3015
EN301 357 – 1
Electromagnetic compatibility and Radio Spectrum Matters (ERM);
Cordless audio devices in the range 25 to 2000MHz; Consumer radio microphones and inear monitoring systems operating in the CEPT harmonized band 863 to 865MHz; Part 1:
Technical characteristics and Test methods
EN301 357 – 2
Electromagnetic compatibility and Radio Spectrum Matters (ERM);
Cordless audio devices in the range 25 to 2000MHz; Consumer radio microphones and inear monitoring systems operating in the CEPT harmonized band 863 to 865MHz; Part 2:
Harmonized EN under article 3.2 of the R&TTE Directive
EN301 489 – 1
Electromagnetic compatibility and Radio Spectrum Matters (ERM);
Electromagnetic Compatibility (EMC) (EMC) standards for radio equipment and services;
Part 1: Common technical requirements
EN301 489 – 9
Electromagnetic compatibility and Radio Spectrum Matters (ERM);
Electromagnetic Compatibility (EMC) (EMC) standards for radio equipment and services;
Part 9: Specific conditions for wireless microphones, similar Radio Frequency (RF) audio
link equipment, cordless audio and in-ear monitoring devices
Revision 3
71
B – Glossary of Acronyms
ADC
Analog to Digital Converter
ARQ
Automatic Repeat Request
BER
Bit Error Ratio
CCA
Clear Channel Assessment
CSMA
Carrier Sense Multiple Access
CW
Continuous Wave
DAC
Digital to Analog Converter
EIRP
Effective Isotropic Radiated Power
EMC
Electro-Magnetic Compatibility
FIFO
First In First Out (memory)
FSK
Frequency Shift Keying
GMSK
Gaussian Minimum Shift Keying
IF
Intermediate Frequency
LBT
Listen Before Talk
LO
Local Oscillator
MAC
Media Access Controller (most of the ZL70250 digital section)
PLL
Phase Locked Loop
PN
Pseudo-random Number
PPM
Parts per million
RSSI
Received Signal Strength Indicator
RX
Receive
TX
Transmit
VCO
Voltage Controlled Oscillator
Note: REGISTER NAMES and bit words that are referenced in this document are defined in section "11 –
System Memory Map" on page 46 and its subsections. STATES are defined in section "7.3 AGC
Modes" on page 27. Many PIN NAMES and signal names referenced in this document are defined
in the ZL70250 Data Sheet.
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C – List of Changes
The following table lists substantive changes that were made in the ZL70250 Programmer User’s Guide
(130348).
Revision
Revision 3
(20 August 2012)
Revision 2
(06 August 2012)
Changes
Page
Changed the recommended initialization values for RF_EN2 and RF_CTL7 in
Table 11-1.
47
Corrected the revision date for Revision 2 in this table (Appendix C).
73
Updated page numbering to remove duplicate page number 4.
All
Changed the recommended initialization values and moved them to Table 11-1
from section "2 – Power-Up Initialization".
47
Added a final step to the tune and trim sequence.
15, 25
Updated timing diagrams, Figure 10-2 and Figure 10-3.
34, 35
Corrected pin names to match datasheet:
(1) changed Vdd_test to VDDTEST.
(2) changed WCLK to CLK_OUT.
10, 56, 66,
others
Also capitalized all pin names to match datasheet.
Changed or corrected register names:
(1) changed WCLK_DIV and CLKOUT_DIV to CLK_OUT_DIV.
(2) changed SYSCLK_DIV to SYS_CLK_DIV.
(3) changed DPORT_TEST1 to MAC_DOUT0.
Changed or corrected bit word names:
(1) in AGC_RESULT_PD register, changed adc_result_pd to pd_result.
(2) in AGC_RESULT_RSSI register, changed adc_result_rssi to rssi_result.
(3) in MAC_CTL1 register, changed dp_auto_off to auto_off.
(4) in SYS_CLK_DIV register, changed sys_clk_div_cnt to sys_clk_div.
(5) in CLK_OUT_DIV register, changed clkout_div_cnt to clk_out_div.
(6) in PLL_CLK_DIV register, changed pll_clk_div_cnt to pll_clk_div.
(7) in IRQ_EN1 register, changed dp_sync_detect_irq_en to sync_detect_irq_en.
(8) in IRQ_EN2 register, changed dp_rx_done_irq_en, dp_tx_done_irq_en,
dp_pll_lock_err_irq_en, and dp_sync_err_irq_en to rx_done_irq_en,
tx_done_irq_en, pll_lock_err_irq_en, and sync_err_irq_en (respectively).
(9) in IRQ1 register, changed dp_sync_detect_irq to sync_detect_irq.
(10) in IRQ2 register, changed dp_rx_done_irq, dp_tx_done_irq,
dp_pll_lock_err_irq, and dp_sync_err_irq to rx_done_irq, tx_done_irq,
pll_lock_err_irq, and sync_err_irq (respectively).
(11) in RF_STAT register, changed dp_pll_lock_stat to pll_lock_stat.
Changed terms SSI and SSI slave port to control interface.
10, 47, 64,
others
59 to 67,
others
9, 14, 16, 20
to 27, 32, 46,
50, 66
Removed references to AGC Modes 0 and 3 (or added a caveat), as these
modes are not recommended for customer use.
27, 28, 56,
57, others
References to a 24.000-MHz crystal and numbers derived from that value (for
example, LO above/below channel) were removed or changed to 24.576MHz and
its derivatives.
10, 65, 66,
others
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Revision
Revision 2, cont.
(06 August 2012)
Revision 1
Changes
Page
Added tables to provide bit definitions for additional registers in memory map,
define values for data port test modes, and provide information on power states.
32, 50 to 70
Name change from Zarlink to Microsemi. Included changing document format
and chapter structure. Spelling, grammar, and minor inconsistencies were also
corrected (or clarified) throughout the document.
All
Initial release
–
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ZL70250 Programmer User’s Guide
D – Product Support
Microsemi CMPG backs its products with various support services, including customer service, a
website, electronic mail, and worldwide sales offices. This appendix contains information about
contacting Microsemi CMPG and using these support services.
D.1
Customer Service
Contact Customer Service for non-technical product support, such as product pricing, product upgrades,
update information, order status, and authorization.
From North America, call 800.432.4009
From the rest of the world, call 512.228.5400
Via e-mail, write to [email protected]
D.2
Website
For more information, log on to MyCPMG at www.microsemi.com/cmpg, where you can browse a variety
of technical and non-technical information. Many answers available on the searchable web resource
include diagrams, illustrations, and links to other resources on the website.
D.2.1
MyCMPG
Microsemi CMPG customers may submit and track technical cases online by logging in to MyCMPG.
D.2.2
Outside the U.S.
Customers needing assistance outside the US time zones can also contact technical support via their
regional sales office.
Sales office listings can be found on our website under Contact Sales > Medical Products.
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solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog
and RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
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ZL70250_Prog_UG/130348-3/8.12