AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
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FEATURES
DESCRIPTION
• Minimizes External
Components
• Selectable Enable Polarity and
Threshold (CMOS or PECL)
• 3V to 5.5V Power Supply
• Similar Operation as
AZ100LVEL16VT except
with LVDS Outputs
The AZV99 is a specialized oscillator gain stage with an LVDS output
buffer including an enable. The selectable enable input allows continuous
oscillator operation by only controlling the QHG /Q
¯ HG outputs.
The AZV99 provides adjustable internal pull-down current sources for the
Q/Q
¯ outputs. Internal input biasing further reduces the number of needed
external components
BLOCK DIAGRAM
APPLICATIONS
•
Crystal or saw oscillators that
require minimal external
components
PACKAGE AVAILABILITY
1
2
•
•
•
MLP8
MLP16
MSOP8
•
Green/RoHS Compliant/Pb-Free
Order Number
Package
Marking
AZV99NG 1
MLP8
V1G <Date Code> 2
AZV99NBG 1
MLP8
V8G <Date Code> 2
AZV99NDG 1
MLP8
V2G <Date Code> 2
AZV99LG 1
MLP16
AZMG <Date Code> 2
AZV99T+ 1
MSOP8
AZ+V99 2
Tape & Reel - Add 'R1' at end of PN for 7in (1k parts), 'R2' (2.5k) for 13in
See www.azmicrotek.com for date code format
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1630 S Stapley Dr, Suite 127
Mesa, AZ 85204 USA
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PIN DESCRIPTION AND CONFIGURATION
Table 1 - Pin Description for AZV99N
Pin
Name
Type
Function
1
Q
¯
Output
Inverting PECL Output
2
D
Input
Data Input
3
VBB
Output
Reference Voltage
4
EN
Input
Output Enable
5
VEE
Power
Negative Supply
6
Q
¯ HG
Output
Inverting LVDS Output
7
QHG
Output
LVDS Output
8
VCC
Power
Positive Supply
8
VCC
7
QHG
6
QHG
4
5
VEE
D
1
8
Q
VBB
2
7
VCC
EN
3
6
QHG
VEE
4
5
QHG
Q
1
8
VCC
D
2
7
QHG
VBB
3
6
QHG
EN
4
5
VEE
Q
1
D
2
VBB
3
EN
Leave Pad
open or
connect to
VEE
Table 2 - Pin Description for AZV99NB
Pin
Name
Type
Function
1
D
Input
Data Input
2
VBB
Output
Reference Voltage
3
EN
¯¯
Input
Output Enable
4
VEE
Power
Negative Supply
5
Q
¯ HG
Output
Inverting LVDS Output
6
QHG
Output
LVDS Output
7
VCC
Power
Positive Supply
8
Q
¯
Output
Inverting PECL Output
Leave Pad
open or
connect to
VEE
Table 3 - Pin Description for AZV99ND
Pin
Name
Type
Function
1
Q
¯
Output
Inverting PECL Output
2
D
Input
Data Input
3
VBB
Output
Reference Voltage
4
EN
¯¯
Input
Output Enable
5
VEE
Power
Negative Supply
6
Q
¯ HG
Output
Inverting LVDS Output
7
QHG
Output
LVDS Output
8
VCC
Power
Positive Supply
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Leave Pad
open or
connect to
VEE
2
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 4 - Pin Description for AZV99L
Pin
Name
Type
Function
1
NC
-
N/A
2
D
Input
Data Input
3
D
¯
Input
Inverting Data Input
4
VBB
Output
Reference Voltage
5
EN
Input
Output Enable
6
NC
-
N/A
7
VEE
Power
Negative Supply
8
NC
-
N/A
9
EN-SEL
Input
Enable Polarity Select
10
Q
¯ HG
Output
Inverting LVDS Output
11
QHG
Output
LVDS Output
12
CS-SEL
Input
Current Source Select
13
VCC
Power
Positive Supply
14
NC
-
N/A
15
Q
Output
PECL Output
16
Q
¯
Output
Inverting PECL Output
Table 5 - Pin Description for AZV99T
Pin
Name
Type
Function
1
Q
¯
Output
Inverting PECL Output
2
D
Input
Data Input
3
VBB
Output
Reference Voltage
4
EN
Input
Output Enable
5
VEE
Power
Negative Supply
6
Q
¯ HG
Output
Inverting LVDS Output
7
QHG
Output
LVDS Output
8
VCC
Power
Positive Supply
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Q
1
8
VCC
D
2
7
QHG
VBB 3
6
QHG
EN 4
5
VEE
3
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
ENGINEERING NOTES
The AZV99 is a specialized oscillator gain stage with LVDS output buffer including an enable. The enable input (EN)
allows continuous oscillator operation by only controlling the QHG /Q
¯ HG outputs.
The AZV99 also provides a VBB and 470Ω internal bias resistors from D to VBB and D
¯ to VBB. The VBB pin can support
1.5 mA sink/source current. Bypassing VBB to ground with a 0.01 µF capacitor is recommended.
FUNCTIONALITY MLP16 PACKAGE (AZV99L)
The MLP16 and die versions of the AZV99 provide a selectable enable (EN). Enable polarity and threshold can be
selected to accommodate either CMOS/TTL or PECL input levels. See the enable truth table for enable function. If enable
pull-up is desired in the CMOS/TTL mode, an external ≤20kΩ resistor connecting EN to VCC will override the on-chip
pull-down resistor.
Outputs Q/Q
¯ each have a selectable on-chip pull-down current source. See the current source truth table for current source
functions. External resistors may also be used to increase pull-down current to a maximum of 25mA (includes internal onchip current source).
FUNCTIONALITY MLP8 PACKAGE (AZV99NB & AZV99ND)
The MLP8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (EN
¯¯¯). When the ¯¯¯
EN input is
LOW, the Q
¯ and QHG/Q
¯ HG outputs pass data from the inputs. When ¯¯¯
EN is HIGH, the Q
¯ output continues to pass data
while the QHG output is forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An
external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current
source).
The AZV99NB and AZV99ND versions operate with a single ended data input (D). The D
¯ input is internally bonded
directly to the VBB pin bypassing the 470Ω bias resistor.
FUNCTIONALITY MLP8 PACKAGE (AZV99N) & MSOP8 PACKAGE (AZV99T)
The MSOP8 (T) and MLP8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When the EN
input is HIGH, the Q
¯ and QHG/Q
¯ HG outputs pass data from the inputs. When EN is LOW, the Q
¯ output continues to pass
data while the QHG output is forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of CS-SEL. An
external resistor may also be used to increase pull-down current to a maximum of 25mA (includes 4mA on-chip current
source).
The MSOP8 (T) and MLP8 (N) AZV99 operates with a single ended data input (D). The D
¯ input is internally bonded
directly to the VBB pin bypassing the 470Ω bias resistor.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 6 – Enable Truth Table
EN-SEL
Q/Q
¯
QHG
Q
¯ HG
PECL Low, VEE or NC
Data
Data
Data
PECL High or VCC
Data
High
Low
CMOS/TTL Low, VEE or NC
Data
High
Low
CMOS/TTL High or VCC2
Data
Data
Data
EN/ EN
NC
VEE1
1 EN-SEL connections must be less than 1Ω.
An external ≤ 20kΩ pull-up resistor between EN and VCC ensures a High when the
2
EN pin is not driven.
D
EN
{
EN-SEL OPEN
(PECL)
EN-SEL SHORTED TO VEE
(CMOS)
Q
Q
QHG
QHG
Figure 1 – Timing Diagram
Table 7 - Current Source Truth Table
CS-SEL
Q
Q
¯
NC
4mA typ
4mA typ
VEE
8mA typ
8mA typ
VCC1
0
4mA typ
1
1 Connection must be less than 1Ω
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
AC Coupling Capacitor
C2
R1
See table
EL16VO
Front End
3.3 or 5 V
CMOS
D
R2
470 Ω
D
VBB
C1
0.01 μF
Figure 2 - Application circuit for CMOS inputs
Table 8 – Recommended Component Values for CMOS Single Ended Inputs
R11 Value
AC Coupled (C2 in circuit)
DC Coupled (C2 shorted)
3.3 V CMOS
1.1 kΩ
2.0 kΩ
5.0 V CMOS
1.6 kΩ
3.3 kΩ
1. R1 should be chosen so that the input swing on the D input with respect to D
¯
is in the range of ±80 to ±1000 mV, per the AC Characteristics table and the
D input is < ±750 mV with respect to VBB.
Input Type
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Figure 3 - S11, 50Ω AC load
Figure 4 - S12, 50Ω AC load
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Figure 5 – S21, 50Ω AC load
Figure 6 – S22, 50Ω AC load
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PERFORMANCE DATA
Table 9 – Absolute Maximum Ratings
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
Characteristic
Condition
Rating
Unit
VCC
PECL Power Supply
VI
PECL Input Voltage
VEE = 0V
0 to + 6.0
V
VEE = 0V
0 to + 6.0
V
VD/
D/D
¯ Input Voltage
Referenced to VBB
V
Continuous Q/Q
¯
±0.75
25
Surge Q/Q
¯
50
Continuous QHG/Q
¯ HG
5
Surge QHG/Q
¯ HG
10
Operating Temperature Range
-
-40 to +85
°C
IOUT
Output Current
TA
mA
TSTG
Storage Temperature Range
-
-65 to +150
°C
ESDHBM
Human Body Model Electro Static Discharge
-
2500
V
ESDMM
Machine Model Electro Static Discharge
-
200
V
ESDCDM
Charged Device Model Electro Static Discharge
-
2000
V
Table 10 - 100K LVPECL DC Characteristics
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
Characteristic
VOH
VOL
VIL
VBB
IIH
0°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
2255
2465
2275
2465
2275
2465
2275
2465
mV
1,2
1375
1745
1400
1680
1400
1680
1400
1680
mV
Input HIGH Voltage D,EN
(EN-SEL open)1
2135
2560
2135
2560
2135
2560
2135
2560
mV
Input HIGH Voltage EN
(EN-SEL tied to VEE)1
2000
VCC
2000
VCC
2000
VCC
2000
VCC
mV
Input LOW Voltage D,EN
(EN-SEL open)1
1400
1825
1400
1825
1400
1825
1400
1825
mV
Input LOW Voltage EN
(EN-SEL tied to VEE)1
GND
800
GND
800
GND
800
GND
800
mV
Reference Voltage1
1910
2050
1910
2050
1910
2050
1910
2050
mV
150
µA
Output LOW Voltage
VIH
-40°C
Input HIGH Current EN
3
3
IIL
Input LOW Current EN
IEE
2
Power Supply Current
1
Voltage levels vary 1:1 with VCC
2
Specified with CS-SEL open
3
Specified with EN-SEL open
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150
0.5
150
0.5
48
150
0.5
48
0.5
48
µA
48
mA
9
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 11 - 100K PECL DC Characteristics
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
Characteristic
VOH
VOL
VIL
VBB
IIH
0°C
25°C
85°C
Unit
Min
Max
Min
Max
Min
Max
Min
Max
Output HIGH Voltage1,2
3955
4165
3975
4165
3975
4165
3975
4165
mV
1,2
3075
3445
3100
3380
3100
3380
3100
3380
mV
Input HIGH Voltage D,EN
(EN-SEL open)1
3835
4260
3835
4260
3835
4260
3835
4260
mV
Input HIGH Voltage EN
(EN-SEL tied to VEE)1
2000
VCC
2000
VCC
2000
VCC
2000
VCC
mV
Input LOW Voltage D,EN
(EN-SEL open)1
3100
3525
3100
3525
3100
3525
3100
3525
mV
Input LOW Voltage EN
(EN-SEL tied to VEE)1
GND
800
GND
800
GND
800
GND
800
mV
Reference Voltage1
3610
3750
3610
3750
3610
3750
3610
3750
mV
150
µA
Output LOW Voltage
VIH
-40°C
Input HIGH Current EN
3
150
3
IIL
Input LOW Current EN
IEE
2
0.5
0.5
Power Supply Current
1
Voltage levels vary 1:1 with VCC
2
Specified with CS-SEL open
3
Specified with EN-SEL open
150
150
0.5
48
0.5
48
µA
48
52
mA
Table 12 – LVDS DC Characteristics
LVDS DC Characteristics for QHG/Q
¯ HG Outputs1 (VEE = GND, VCC = +3.0V to +5.5V)
Symbol
Characteristic
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
VOC
Output Common Mode Voltage
∆VOC
-40°C
Min
0°C
Max
Min
1600
900
2
25°C
Max
Min
1600
900
85°C
Max
Min
1600
900
Max
1600
900
Unit
mV
mV
1125
1375
1125
1375
1125
1375
1125
1375
mV
Change in Common Mode Voltage3
-50
50
-50
50
-50
50
-50
50
mV
VOUT
Single-Ended Output Swing
250
450
250
450
250
450
250
450
mV
VDIFF_OUT
Differential Output Swing
500
900
500
900
500
900
500
900
mV
1
Specified with 100Ω resistor connecting QHG and Q
¯ HG together.
2
Common mode voltage is the center voltage between QHG and Q
¯ HG during a steady state.
3
Change in common mode voltage is the difference between common mode voltages at opposite binary states.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
Table 13 – AC Characteristics
AC Characteristics (VEE = -3.0V to -5.5V; VCC=GND or VEE=GND; VCC = +3.0V to +5.5V)
Symbol
-40°C
Characteristic
Min
Typ
0°C
Max
Min
Typ
25°C
Max
Min
Typ
85°C
Max
Min
Typ
Max
Unit
Propagation Delay
D to Q/Q
¯1
tPLH/tPHL
2
D to QHG/Q
¯ HG
3
tSKEW
Duty Cycle Skew
Vpp (AC)
4
Input Swing
5
400
400
400
430
ps
550
550
550
630
ps
20
ps
mV
20
5
20
5
20
5
80
1000
80
1000
80
1000
80
1000
100
260
100
260
100
260
100
260
180
280
180
280
180
280
180
280
1
Output Rise/Fall
(20% - 80%) - Q
Output Rise/Fall1
(20% - 80%) QHG
tr/tf
1
2
3
ps
Specified with CS-SEL connected to VEE and Q/Q
¯ with AC coupled 50Ω loads.
Specified with 100Ω resistor connecting QHG and Q
¯ HG together.
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
4
The peak-to-peak differential input swing is the range for which AC parameters guaranteed. VD and V must remain
within the range of ±750 mV with respect to VBB.
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May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PACKAGE DIAGRAM
MLP8
Green/RoHS compliant/Pb-Free
MSL=1
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12
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PACKAGE DIAGRAM
MLP16
Green/RoHS compliant/Pb-Free
MSL=1
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13
May 2012, Rev 2.0
Arizona Microtek, Inc.
AZV99
PECL/LVDS Oscillator Gain Stage &
Buffer with Selectable Enable
PACKAGE DIAGRAM
MSOP8
Green/RoHS compliant/Pb-Free
MSL=1
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice.
Arizona Microtek, Inc. makes no warranty, representation or guarantee regarding the suitability of its products for
any particular purpose, nor does Arizona Microtek, Inc. assume any liability arising out of the application or use of
any product or circuit and specifically disclaims any and all liability, including without limitation special,
consequential or incidental damages. Arizona Microtek, Inc. does not convey any license rights nor the rights of
others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc.
product could create a situation where personal injury or death may occur. Should Buyer purchase or use Arizona
Microtek, Inc. products for any such unintended or unauthorized application, Buyer shall indemnify and hold
Arizona Microtek, Inc. and its officers, employees, subsidiaries, affiliates, and distributors harmless against all
claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of
personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
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May 2012, Rev 2.0