ARIZONA MICROTEK, INC.
AZV99
PECL/LVDS Oscillator Gain Stage & Buffer with Selectable Enable
FEATURES
•
•
•
•
•
•
•
Green and RoHS Compliant /
Lead (Pb) Free Packages Available
Similar Operation as AZ100LVEL16VT
except with LVDS Outputs
Operating Range of 3.0V to 5.5V
Minimizes External Components
Selectable Enable Polarity and
Threshold (CMOS/TTL or PECL)
Available in a 2x2 or 3x3mm
MLP Package
S–Parameter (.s2p) and IBIS Model
Files Available on Arizona Microtek
Website
PACKAGE AVAILABILITY
PACKAGE
MARKING
NOTES
AZV99NG
V1G
<Date Code>
1,2
MLP 8 (2x2x0.75)
AZV99NA
V9
<Date Code>
1,2
AZV99NBG
V8G
<Date Code>
1,2
AZV99NDG
V2G
<Date Code>
1,2
AZV99LG
AZMG
V99
<Date Code>
1,2
AZV99T+
AZ+
V99
1,2,3
AZV99XP
AZV99XR
N/A
N/A
4
5
MLP 8 (2x2x0.75)
Green / RoHS
Compliant / Lead (Pb)
Free
MLP 8 (2x2x0.75)
Green / RoHS
Compliant / Lead (Pb)
Free
MLP 16 (3x3) Green /
RoHS Compliant /
Lead (Pb) Free
TSSOP 8 RoHS
Compliant / Lead (Pb)
Free
DIE
DIE
1
DESCRIPTION
PART NUMBER
MLP 8 (2x2x0.75)
Green / RoHS
Compliant / Lead (Pb)
Free
2
3
4
5
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts) Tape &
Reel.
Date code format: “Y” for year followed by “WW” for week.
Date Code “YWW” on underside of part.
Waffle Pack. Die thickness 180 μm.
Die on 7 inch Tape & Reel, 3k parts per reel. Die thickness 180 μm.
The AZV99 is a specialized oscillator gain stage with LVDS output buffer including an enable. The enable
input (EN) allows continuous oscillator operation by only controlling the QHG /Q
¯ HG outputs.
¯ to VBB. The VBB pin can
The AZV99 also provides a VBB and 470Ω internal bias resistors from D to VBB and D
support 1.5 mA sink/source current. Bypassing VBB to ground with a 0.01 μF capacitor is recommended.
MLP 16, 3x3 mm Package (L) or DIE (X)
The MLP 16 and die versions of the AZV99 provide a selectable enable (EN). Enable polarity and threshold can
be selected to accommodate either CMOS/TTL or PECL input levels. See the enable truth table for enable function.
If enable pull-up is desired in the CMOS/TTL mode, an external ≤20kΩ resistor connecting EN to VCC will override
the on-chip pull-down resistor.
Outputs Q/Q
¯ each have a selectable on-chip pull-down current source. See the current source truth table for
current source functions. External resistors may also be used to increase pull-down current to a maximum of 25mA
(includes internal on-chip current source).
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (623) 505-2414
www.azmicrotek.com
AZV99
MLP 8, 2x2 mm Package, NA, NB & ND Options
The MLP 8 NA, NB and ND options of the AZV99 provide a PECL/ECL level enable input (EN
¯¯¯). When the
¯¯¯
EN input is LOW, the Q
¯ and QHG/Q
¯ HG outputs pass data from the inputs. When ¯¯¯
EN is HIGH, the Q
¯ output
continues to pass data while the QHG output is forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes
4mA on-chip current source).
The AZV99NB and AZV99ND versions operates with a single ended data input (D). The D
¯ input is internally
bonded directly to the VBB pin bypassing the 470Ω bias resistor.
TSSOP 8 Package (T), MLP 8 Package, (N)
The TSSOP 8 (T) and MLP 8 (N) versions of the AZV99 provide a CMOS/TTL level enable input (EN). When
the EN input is HIGH, the Q
¯ and QHG/Q
¯ HG outputs pass data from the inputs. When EN is LOW, the Q
¯ output
continues to pass data while the QHG output is forced high and the Q
¯ HG output is forced low.
Only the Q
¯ output operates with a current source (4 mA) to VEE. This is accomplished by internal bonding of
CS-SEL. An external resistor may also be used to increase pull-down current to a maximum of 25mA (includes
4mA on-chip current source).
The TSSOP 8 (T) and MLP 8 (N) AZV99 operates with a single ended data input (D). The D
¯ input is internally
bonded directly to the VBB pin bypassing the 470Ω bias resistor.
NOTE: Specifications in the ECL/PECL tables are valid when thermal equilibrium is established.
PIN DESCRIPTION
4mA EA.
Q
PIN
D/D
¯
Q/Q
¯
QHG/Q
¯ HG
VBB
EN-SEL
EN/EN
¯¯
CS-SEL
VEE
VCC
FUNCTION
Data Inputs
PECL Data Outputs
LVDS Data Outputs
Reference Voltage Output
Selects Enable Logic
Enable Input
Selects Q and Q
¯ Current Source Magnitude
Negative Supply
Positive Supply
Q
CS-SEL
D
QHG
D
QHG
470
VBB
VEE
EN/EN
CMOS/TTL
THRESHOLD
EN-SEL
ENABLE TRUTH TABLE
EN-SEL
EN/EN
¯¯¯
Q/Q
¯
QHG
Q
¯ HG
NC
PECL Low or NC
Data Data Data
NC
PECL High or VCC
Data High Low
CMOS/TTL Low, VEE or NC
VEE1
Data High Low
VEE1
CMOS/TTL High or VCC2
Data Data Data
1
EN-SEL connections must be less than 1Ω.
2
An external ≤20kΩ pull-up resistor between EN and VCC ensures a
High when the EN pin is not driven.
June 2009 * REV - 13
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2
CURRENT SOURCE TRUTH TABLE
CS-SEL
Q
Q
¯
NC
4mA typ.
4mA typ.
VEE1
8mA typ.
8mA typ.
0
4mA typ.
VCC1
1
CS-SEL connections must be less than 1Ω.
AZV99
Absolute Maximum Ratings are those values beyond which device life may be impaired.
Symbol
VCC
VI
VD/D¯
IOUT
TA
TSTG
Characteristic
Power Supply
Input Voltage
D/D
¯ Input Voltage
Output Current
— Continuous
Q/Q
¯
— Surge
Q/Q
¯
¯ HG
— Continuous QHG/Q
¯ HG
— Surge
QHG/Q
Operating Temperature Range
Storage Temperature Range
Rating
0 to +6.0
0 to +6.0
±0.75 with respect to VBB
25
50
5
10
-40 to +85
-65 to +150
Unit
Vdc
Vdc
Vdc
mA
°C
°C
100K LVPECL DC Characteristics (VEE = GND, VCC = +3.3V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIL
IIH
IEE
1.
2.
3.
Characteristic
1,2
Output HIGH Voltage
Q/Q
¯
Output LOW Voltage1,2
Q/Q
¯
Input HIGH Voltage
D/D
¯ 1, EN (EN-SEL open)1
EN (EN-SEL tied to VEE)
Input LOW Voltage
D/D
¯ 1, EN (EN-SEL open)1
EN (EN-SEL tied to VEE)
Reference Voltage1
Input LOW Current EN3
Input HIGH Current EN3
Power Supply Current2
Voltage levels vary 1:1 with VCC.
Specified with CS-SEL open.
Specified with EN-SEL open.
-40°C
0°C
25°C
85°C
Unit
Min
2255
1375
Max
2465
1745
Min
2275
1400
Max
2465
1680
Min
2275
1400
Max
2465
1680
Min
2275
1400
Max
2465
1680
2135
2000
2560
VCC
2135
2000
2560
VCC
2135
2000
2560
VCC
2135
2000
2560
VCC
mV
1400
GND
1910
0.5
1825
800
2050
1400
GND
1910
0.5
1825
800
2050
1400
GND
1910
0.5
1825
800
2050
1400
GND
1910
0.5
1825
800
2050
mV
150
48
150
48
150
48
150
52
mV
mV
mV
μA
μA
mA
100K PECL DC Characteristics (VEE = GND, VCC = +5.0V)
Symbol
VOH
VOL
VIH
VIL
VBB
IIL
IIH
IEE
1.
2.
3.
Characteristic
1,2
Output HIGH Voltage
Q/Q
¯
Output LOW Voltage1,2
Q/Q
¯
Input HIGH Voltage
D/D
¯ 1, EN (EN-SEL open)1
EN (EN-SEL tied to VEE)
Input LOW Voltage
D/D
¯ 1, EN (EN-SEL open)1
EN (EN-SEL tied to VEE)
Reference Voltage1
Input LOW Current EN3
Input HIGH Current EN3
Power Supply Current2
Voltage levels vary 1:1 with VCC.
Specified with CS-SEL open.
Specified with EN-SEL open.
June 2009 * REV - 13
-40°C
0°C
25°C
85°C
Unit
Min
3955
3075
Max
4165
3445
Min
3975
3100
Max
4165
3380
Min
3975
3100
Max
4165
3380
Min
3975
3100
Max
4165
3380
3835
2000
4260
VCC
3835
2000
4260
VCC
3835
2000
4260
VCC
3835
2000
4260
VCC
mV
3100
GND
3610
0.5
3525
800
3750
3100
GND
3610
0.5
3525
800
3750
3100
GND
3610
0.5
3525
800
3750
3100
GND
3610
0.5
3525
800
3750
mV
150
48
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3
150
48
150
48
150
52
mV
mV
mV
μA
μA
mA
AZV99
¯ HG Outputs1 (VEE = GND, VCC = +3.0V to +5.5V)
LVDS DC Characteristics for QHG/Q
Symbol
-40°C
Characteristic
Min
0°C
Max
1600
Min
25°C
Max
1600
Min
VOH
Output HIGH Voltage
VOL
Output LOW Voltage
900
900
900
VOC
Output Common Mode Voltage2
1125
1375
1125
1375
1125
Change in Common Mode Voltage3
-50
50
-50
50
-50
ΔVOC
VOUT
Single-Ended Output Swing
250
450
250
450
250
VDIFF_OUT Differential Output Swing
500
900
500
900
500
1.
Specified with 100Ω resistor connecting QHG and Q
¯ HG together.
¯ HG during a steady state.
2.
Common mode voltage is the center voltage between QHG and Q
3.
Change in common mode voltage is the difference between common mode voltages at opposite binary states.
85°C
Max
1600
1375
50
450
900
Min
Max
1600
900
1125
-50
250
500
1375
50
450
900
Unit
mV
mV
mV
mV
mV
mV
AC Characteristics (VEE = GND, VCC = +3.0V to +5.5V)
Symbol
tPLH / tPHL
tSKEW
VPP (AC)
tr / t f
1.
2.
3.
4.
Characteristic
Min
Propagation Delay
D to Q/Q
¯ Outputs1
D to QHG/Q
¯ HG Outputs2
Duty Cycle Skew Q/Q
¯3
Differnetial Input Swing4
Output Rise/Fall Times
(20% - 80%)
(SE)
(SE)
(SE)
-40°C
Typ
5
80
Max
400
550
20
1000
Min
0°C
Typ
5
80
Max
400
550
20
1000
Min
25°C
Typ
5
80
Max
400
550
20
1000
Min
85°C
Typ
5
80
Max
430
630
20
1000
100
260
100
260
100
260
100
260
Q/Q
¯1
¯ HG2
180
280
180
280
180
280
180
280
QHG/Q
Specified with CS-SEL connected to VEE and Q/Q
¯ with AC coupled 50Ω loads.
¯ HG together.
Specified with 100Ω resistor connecting QHG and Q
Duty cycle skew is the difference between a tPLH and tPHL propagation delay through a device.
The peak-to-peak differential input swing is the range for which AC parameters guaranteed. VD and VD¯ must remain within the range of ±750 mV
with respect to VBB.
AC PP INPUT
D
D
V PP (AC)
June 2009 * REV - 13
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4
Unit
ps
ps
mV
ps
AZV99
-10
0.85
-20
Magnitude
0.9
0.8
-30
0.75
-40
0.7
Phase
0
S11 MAG 8mA
S11 MAG 4mA
S11 PHASE 8mA
S11 PHASE 4mA
Phase
0.95
S12 MAG 8mA
S12 MAG 4mA
S12 PHASE 8mA
S21 PHASE 4mA
-50
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
S11, D to Q
¯ , 50 Ω AC load on Q
¯
250.00
0.02
200.00
0.015
150.00
Magnitude
0.025
0.01
100.00
0.005
50.00
0
0.00
50
150
250
350
450
550
650
750
850
950
1050 1150 1250 1350
Frequency (MHz)
S12, D to Q
¯ , 50 Ω AC load on Q
¯
June 2009 * REV - 13
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5
180
35
160
30
140
25
120
20
100
15
80
10
60
5
40
0
Phase
40
S21 MAG 8mA
S21 MAG 4mA
S21 PHASE 8mA
S21 PHASE 4mA
Phase
Magnitude
AZV99
S22 MAG 8mA
S22 MAG 4mA
S22 PHASE 8mA
S22 PHASE 4mA
20
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
1350
Frequency (MHz)
Magnitude
S21, D to Q
¯ , 50 Ω AC load on Q
¯
0.8
180.00
0.7
160.00
0.6
140.00
0.5
120.00
0.4
100.00
50
150
250
350
450
550
650
750
850
950
1050
1150
1250
Frequency (MHz)
S22, D to Q
¯ , 50 Ω AC load on Q
¯
June 2009 * REV - 13
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6
1350
AZV99
AC Coupling Capacitor
C2
3.3 or 5 V
CMOS
R1
See table
AZV99
Front End
D
D
VBB
C1
0.01 μF
Application Circuit for CMOS Inputs
R11
Input
Type
AC
Coupled
(C2 in
circuit)
DC
Coupled
(C2
shorted)
3.3 V
1.1 kΩ
2.0 kΩ
CMOS
5 V CMOS
1.6 kΩ
3.3 kΩ
1
R1 should be chosen so that the input swing on the D input
with respect to D
¯ is in the range of ±80 to ±1000 mV, per the
AC Characteristics table and the D input is < ±750 mV with
respect to VBB.
Recommended Component Values for CMOS Single Ended Inputs
June 2009 * REV - 13
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7
AZV99
TIMING DIAGRAM
D
EN/
EN
{
(PECL)
EN-SEL OPEN (EN)
(CMOS/TTL)
EN-SEL SHORTED TO VEE (EN)
Q
Q
QHG
QHG
PINOUT FOR AZV99L
MLP 16, 3x3mm
AZV99L
Q
Q
NC
VCC
16
15
14
13
NC
1
12 CS-SEL
D
2
11
D
3
10 QHG
VBB
4
9
5
6
7
8
EN
NC
VEE
NC
QHG
EN-SEL
TOP VIEW
Bottom Center Pad may be left open or tied to VEE
June 2009 * REV - 13
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8
AZV99
LOGIC DIAGRAMS AND PINOUTS FOR
AZV99NA, AZV99NB, AZV99ND
4mA
4mA
Q
VEE
D
QHG
D
QHG
470
470
Q
VEE
D
QHG
QHG
470
VBB/D
VBB
AZV99NB
AZV99ND
AZV99NA
EN
EN
EN operation follows PECL functionality. See the
Timing Diagram.
MLP 8, 2x2mm
MLP 8, 2x2mm
D
1
D
2
AZV99NA
D
1
AZV99NB
8
Q
2
7
VCC
EN
3
6
QHG
VEE
4
5
QHG
8
Q
7
VCC
VBB/D
6
QHG
5
QHG
VEE
VBB
3
EN
4
TOP VIEW
Bottom Center Pad is the VEE
return.
MLP 8, 2x2mm
Q
1
D
AZV99ND
8
VCC
2
7
QHG
VBB/D
3
6
QHG
EN
4
TOP VIEW
5 VEE
Bottom Center Pad may be left open
or tied to VEE. Pin 5 is the VEE return.
June 2009 * REV - 13
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9
TOP VIEW
Bottom Center Pad may be left open
or tied to VEE. Pin 4 is the VEE return.
AZV99
LOGIC DIAGRAM AND PINOUTS FOR
AZV99T, AZV99N
4mA
Q
VEE
D
QHG
QHG
470
VBB/D
AZV99T
AZV99N
EN
CMOS/TTL
THRESHOLD
EN follows CMOS/TTL functionality. See the
Timing Diagram.
Q 1
D 2
VBB / D 3
8 VCC
7 QHG
AZV99T
TSSOP 8
6 QHG
5 VEE
EN 4
MLP 8, 2x2mm
Q
1
D
AZV99N
8
VCC
2
7
QHG
VBB/D
3
6
QHG
EN
4
TOP VIEW
5 VEE
Bottom Center Pad may be left open
or tied to VEE. Pin 5 is the VEE return.
June 2009 * REV - 13
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10
AZV99
DIE PAD COORDINATES
AZV99 DIE:
AZV99
A
B
L
M
DIE SIZE: 950u X 940u
DIE THICKNESS: 180u
C
BOND PAD: 85u X 85u
D
E
F
K
J
I
H
G
Note: Other die thicknesses available. Contact factory for further information.
PAD COORDINATES1
NAME
1.
A
B
C
D
E
F
G
H
I
J
K
L
M
0, 0 is center of die.
June 2009 * REV - 13
PAD DESIGNATION
D
D
¯
VBB
EN/EN
¯¯¯
VEE
NC
EN-SEL
Q
¯ HG
QHG
CS-SEL
VCC
Q
Q
¯
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11
PAD CENTERS
X(Microns)
Y(Microns)
-342.5
312.5
-342.5
144.5
-342.5
-87.0
-342.5
-255.0
-33.5
-312.5
126.5
-312.5
312.5
-248.5
312.5
-98.5
312.5
51.5
312.5
201.5
302.5
342.5
142.5
342.5
-140.5
342.5
AZV99
DIE ON TAPE
ORIENTATION
DIE ID
Direction of Feed
Package
X (Die)
Suffix
R
June 2009 * REV - 13
Reel
Diameter
7”
Quantity
3000
www.azmicrotek.com
12
Carrier Tape
Width
8mm
Carrier Tape
Pitch
4mm
AZV99
PACKAGE DIAGRAM
MLP 16
A
D
D
2
2.
INDEX AREA
(D/2 x E/2)
D2
D2/2
B
E2/2
E2
E
2
3x
E
e
2
e
2x
1
aaa C
2x
aaa C
TOP VIEW
bbb M C A B
5.
16 x b
L
3.
3x e
BOTTOM VIEW
ccc C
A3
A
4.
0.08 C
A1
SIDE
VIEW
NOTES:
1. DIMENSIONING AND TOLERANCING
CONFORM TO ASME T14-1994.
2. THE TERMINAL #1 AND PAD
NUMBERING CONVENTION SHALL
CONFORM TO JESD 95-1 SPP-012.
3. DIMENSION b APPLIES TO METALLIZED
PAD AND IS MEASURED BETWEEN 0.25
AND 0.30 mm FROM PAD TIP.
4. COPLANARITY APPLIES TO THE
EXPOSED PADS AS WELL AS THE
TERMINALS.
5. INSIDE CORNERS OF METALLIZED PAD
MAY BE SQUARE OR ROUNDED
June 2009 * REV - 13
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13
C
SEATING
PLANE
MILLIMETERS
DIM
A
A1
A3
b
D
D2
E
E2
e
L
aaa
bbb
ccc
MIN
MAX
0.80
1.00
0.05
0.00
0.25 REF
0.18
0.30
2.90
3.10
0.25
1.95
2.90
3.10
0.25
1.95
0.50 BSC
0.30
0.50
0.25
0.10
0.10
AZV99
PACKAGE DIAGRAM
MLP 8 2x2mm
Pin 1 Dot
By Marking
2.000±0.050
MLP 8
(2x2mm)
2.000±0.050
TOP VIEW
Pin 1 Identification
R0.100 TYP
0.350±0.050
0.250±0.050
0.500 bsc
8
1
7
6
2 1.200±0.050
exp. pad
3
5
4
0.600±0.050
exp. pad
BOTTOM VIEW
0.900±0.050
0.000-0.050
1
2
SIDE VIEW
Note: All dimensions are in mm
June 2009 * REV - 13
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14
3 4
0.203±0.025
1.750
Ref.
AZV99
PACKAGE DIAGRAM
TSSOP 8
DIM
A
A1
A2
A3
bp
c
D
E
e
HE
L
Lp
v
w
y
Z
θ
NOTES:
1.
DIMENSIONS D AND E DO NOT
INCLUDE MOLD PROTRUSION.
2.
MAXIMUM MOLD PROTRUSION
FOR D IS 0.15mm.
3.
MAXIMUM MOLD PROTRUSION
FOR E IS 0.25mm.
June 2009 * REV - 13
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15
MILLIMETERS
MIN
MAX
1.10
0.05
0.15
0.80
0.95
0.25
0.25
0.45
0.15
0.28
2.90
3.10
2.90
3.10
0.65
4.70
5.10
0.94
0.40
0.70
0.10
0.10
0.10
0.35
0.70
6O
0O
AZV99
Arizona Microtek, Inc. reserves the right to change circuitry and specifications at any time without prior notice. Arizona Microtek, Inc.
makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Arizona
Microtek, Inc. assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all
liability, including without limitation special, consequential or incidental damages. Arizona Microtek, Inc. does not convey any license
rights nor the rights of others. Arizona Microtek, Inc. products are not designed, intended or authorized for use as components in systems
intended to support or sustain life, or for any other application in which the failure of the Arizona Microtek, Inc. product could create a
situation where personal injury or death may occur. Should Buyer purchase or use Arizona Microtek, Inc. products for any such
unintended or unauthorized application, Buyer shall indemnify and hold Arizona Microtek, Inc. and its officers, employees, subsidiaries,
affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly
or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that
Arizona Microtek, Inc. was negligent regarding the design or manufacture of the part.
June 2009 * REV - 13
www.azmicrotek.com
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