ROHM BD3507HFV

High Performance Regulators for PCs
Nch FET Ultra LDO
for PC Chipsets
BD3507HFV
No.10030EAT31
●Description
The BD3507HFV is suited for power supply for chipset bus. Though small in size, BD3507HFV adopts power PKG with
radiation fins, and it therefore can be used for a regulator up to 550mA. Because it adopts Nch MOSFET and can form a
ultra LDO power supply of RON=300mΩ (TYP), BD3507HFV can compose a high-efficiency system, though it is of a linear
type power supply. The output voltage can be set by VREF terminal and can be synchronized with other power supply.
In addition, it can be used as a high side switch (RON = 300mΩ/lo = 550mA) of low-voltage power supply line.
Because ceramic capacitors can be used for output capacitors, BD3507HFV contributes to downsizing and reduced
thickness not only of IC but also of sets.
●Features
1) Built-in high-accuracy buffer circuit (can be set to 0.65-2.7V)
2) Adoption of ceramic capacitors
3) Built-in enable function (0μA at standby)
4) Built-in current limiting circuit (550mA Max)
5) Built-in under voltage lockout circuit (UVLO)
6) Built-in thermal shutdown circuit (TSD)
7) Adoption of ultra-small-size high-power HVSOF6 package (3.0 x 1.6 x 0.75 mm)
●Applications
Notebook PC, desktop PC, digital camera, digital home appliances
●Absolute Maximum Ratings (Ta=25℃)
Parameter
Symbol
Ratings
Unit
*1 *2
V
Input Voltage1
VCC
6.0
Input Voltage2
VIN
6.0 *1 *2
V
VEN
*1 *2
V
Enable Input Voltage
6.0
*3
mW
mW
Power Dissipation1
Pd1
512.5
Power Dissipation2
Pd2
850.0 *4
Operating Temperature Range
Topr
-10～+100
℃
Storage Temperature Range
Tstg
-55～+150
℃
Tjmax
+150
℃
Maximum Junction Temperature
*1 However, not exceeding Pd.
*2 Maximum rating that can stand instantaneous voltage application such as surge, back EMF, or continuous pulse application whose duty ratio lowers 10%.
*3 In the case of Ta≥25°C (when mounting to 70mmx70mmx1.6mm glass epoxy substrate), derated at 4.1 mW/°C.
*4 In the case of Ta≥25°C (when mounting to 70mmx70mmx1.6mm glass epoxy substrate (copper foil area: 100 mm2)), derated at 6.8 mW/°C.
●Operating Conditions (Ta=25℃)
Parameter
Input Voltage1
Input Voltage2
Symbol
VCC
Ratings
Unit
MIN
MAX
4.5
5.5
V
VIN
1.2
Vcc-1
V
VREF Setup Voltage
VREF
0.65
2.7
V
EN Input Voltage
VEN
-0.3
5.5
V
IO
0
550
mA
Output Current
★ No radiation-resistant design is adopted for the present product.
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1/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Electrical Characteristics (unless otherwise noted, Ta=25℃, VCC=5V, VIN=1.8V, VREF=1.2V, VEN=3V)
Standard Value
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
Bias Current
ICC
-
0.4
0.7
mA
Standby Current1
ISTB
-
0
10
μA
VEN=0V
Standby Current2
IINSTB
-
0
10
μA
VEN=0V
Output Voltage1
VO1
1.188
1.200
1.212
V
Io=0mA
Output Voltage2
VO2
1.188
1.200
1.212
V
Io=300mA
Output Voltage3
VO3
1.176
1.200
1.224
V
Io=0mA to 550mA
Vcc=4.5V to 5.5V
Ta=-10℃ to 100℃
Output Voltage4
Vo4
2.475
2.500
2.525
V
VIN=3.3V,VREF=2.5V Io=0mA
Output Voltage5
Vo5
2.475
2.500
2.525
V
Output Voltage6
Vo6
2.450
2.500
2.550
V
Over Current Protect
ICL
600
-
-
mA
Output ON Resistance
RON
-
300
550
mΩ
High Level Enable Input Voltage
ENHigh
2.0
-
-
V
EN:Sweep-up
Low Level Enable Input Voltage
ENLOW
-0.2
-
0.8
V
EN:Sweep-down
IEN
-
7
10
μA
VEN=3V
UVLO OFF Voltage
VUVLO
3.5
3.8
4.1
V
Vcc:Sweep-up
UVLO Hysteresis Voltage
VHYS
100
160
220
mV
Vcc:Sweep-down
VREF Pin Bias Current
IVREF
-0.1
-
0.1
μA
VREF=0→2.7 V *5
VREF Discharge ON Resistance
RONREF
-
1.0
2.0
kΩ
Output Discharge ON Resistance
RONDIS
-
0.1
0.3
kΩ
Enable Pin Input Current
*5
VIN=3.3V,VREF=2.5V
Io=300mA
VIN=3.3V,VREF=2.5V
Io=0mA to 550mA
Vcc=4.5V to 5.5V
Ta=-10℃ to 100℃ *5
*5 Design Guarantee
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2/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Reference Data
1.75
0.50
280
0.45
0.35
1.65
0.25
0.20
0.15
IIN(mA)
200
0.30
Icc(nA)
Icc(mA)
1.70
240
0.40
160
120
1.55
80
0.10
0.00
-10
1.50
40
0.05
10
30
50
Ta( ℃)
70
0
-55
90
1.60
-15
25
65
Ta(℃)
105
1.45
-10
145
30
Fig.2 Ta-ISTB
(Vcc)
Fig.1 Ta-Icc
(Vcc)
50
Ta(℃)
70
90
70
90
Fig.3 Ta-IIN
(VIN)
35
240
1.208
Vo=1.2V
200
32
120
Io(mA)
1.203
160
Vo(V)
IIN(nA)
10
1.198
29
26
80
1.193
23
40
0
-55
-15
25
65
Ta( ℃)
105
145
1.188
-10
10
Fig.4 Ta-IINSTB
(VIN)
30
50
Ta( ℃)
70
20
-10
90
10
8
VREF=1.2V
500
7
2.175
450
6
2.165
2.5V
400
5
RON[mΩ]
IEN(uA)
IREF(mA)
2.170
4
3
2.160
50
Ta( ℃)
Fig.6 Ta-IODIS
Fig.5 Ta-Vo
2.180
30
1.8V
350
300
2
2.155
1
250
2.150
0
-60
200
-10
10
30
50
70
90
-20
Ta( ℃)
Fig.7 Ta-IrefDIS
20
60
Ta( ℃)
100
140
1.2V
4
4.5
5
VCC[V]
5.5
6
Fig.9 Vcc-Ron
Fig.8 Ta-IEN
400
350
RON[mΩ］
300
EN
EN
VREF
VREF
VO
VO
250
200
150
100
50
0
-10
10
30
50
70
90
Ta(℃)
Fig.10 Ta-Ron
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Fig.11 Startup Wave Form
3/15
Fig.12 Shutdown Wave Form
2010.05 - Rev.A
Technical Note
BD3507HFV
VCC
EN
VCC
VCC
EN
EN
VREF
VREF
VO
VO
VO
Fig.13 Input Sequence 1
Fig.14 Input Sequence 2
VREF
VCC
EN
VREF
VO
VCC
VCC
EN
EN
VREF
VREF
VO
VO
Fig.16 Input Sequence 4
Fig.17 Input Sequence 5
VO
VO
IO
IO
Fig.19 Transient Response
(0→550mA/μs)
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Fig.15 Input Sequence 3
Fig.18 Input Sequence 6
Fig.20 Transient Response
(550→0mA/μs)
4/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Block Diagram
VCC
VCC
VIN
VIN
UVLO
UVLO
Current
Limit
CL
VREF
+
VREF
EN
UVLO
EN
EN
Enable
VO
-
EN
VO
TSD
UVLO
Ceramic Capacitor
EN
EN
EN
TSD
TSD
GND
UVLO
●Pin Function
Pin No.
Pin Name
PIN Function
1
VCC
VCC Pin
2
EN
Enable Input Pin
3
VIN
Input Voltage Pin
4
Vo
Output Pin
5
VREF
Reference Voltage Input Pin
6
GND
Ground Pin
●Pin Configration
VCC
1
6
GND
EN
2
5
VREF
VIN
3
4
VO
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5/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Block Function
・AMP
An error amplifier that compares reference voltage (VREF) to Vo and drives Nch FET (Ron=300 mΩ) of output. The
frequency characteristics are optimized so that ceramic capacitors can be used for output capacitors and high-speed
transient response can be achieved. The input voltage range at the AMP section is GND-2.7V and the output voltage
range of the AMP section is GND-VCC. At the time of EN OFF or UVLO, the output is brought to the LOW level and the
output NchFET is turned OFF.
・EN
By the logic input pin, regulator ON/OFF is controlled. At the time of OFF, the circuit current is controlled to be 0µA to
reduce the standby current consumption of the apparatus. In addition, EN turns ON FET that can discharge VREF and Vo
and removes excess electric charge to prevent maloperation of IC on the load side. Since there is no electrical
connection with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input sequence.
・UVLO
UVLO turned OFF output to prevent output voltage from making maloperation at the time of Vcc reduced voltage. Same
as EN, UVLO discharges VREF and Vo. When voltage exceeds the threshold voltage (TYP 3.8V), UVLO starts output.
・CURRENT LIMIT
In the event the output current that exceeds the current (0.6A or more) set inside the IC flows when output is turned ON,
output voltage is attenuated to protect the IC on the load side. When current reduces, output voltage returns to the set
voltage.
・SOFT START
Adding external resistor and capacitor to VREF pin can achieve soft-start. By the time constant that is determined by the
time constant of CR, VREF pin becomes dull, and output rises in synchronism with VREF pin. Overshoot of output voltage
or inrush current can be prevented.
・VREF
VREF is a reference voltage input pin and sets output voltage. Since there is no electrical connection with the Vcc
terminal as is the case of Di for electrostatic measures, it does not depend on the input sequence.
・TSD(Thermal Shut down)
In order to prevent thermal breakdown and thermal runaway of the IC, the output is turned OFF when chip temperature
becomes high. In addition, when temperature returns to the specified temperature, the output is recovered. However,
since the temperature protection circuit is originally built in to protect the IC itself, thermal design within Tj(max) is
requested.
・VIN
This is a large-current supply line. The VIN terminal is connected to the rain of output NchFET. Since there is no
electrical connection with the Vcc terminal as is the case of Di for electrostatic measures, it does not depend on the input
sequence. However, because there is body Di of output Nch FET between VIN and Vo, there is electrical connection
(Di-connection) between VIN and Vo. Consequently, when the output is turned ON/OFF by VIN, reverse current flows
from Vo to VIN, to which care must be taken.
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6/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Timing Chart
EN
ON/OFF
VIN
VCC
EN
Vref
Vo
t
VCC ON/OFF
VIN
hysteresis
VCC
EN
Vref
Vo
t
Vref Synchronous Action
VIN
VCC
EN
Vref
Vo
t
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7/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Application setting method
Vcc
VR
GND
Vcc
R1
C1
VIN
VREF
VREF
EN
ON/OFF
R2
VIN
VO
C2
C4
Vo
C3
Ceramic Capacitor
Part No
Value
Notes for Use
R1/R2
22k/11k
The present IC can set output voltage by external reference voltage (VR) and value of output
voltage setting resistors (R1, R2). Output voltage can be set by VRxR2/(R1+R2) but it is
recommended to use at the resistance value (total: about 10 kΩ) which is not susceptible to VREF
bias current (±100nA).
C3
22μF
C1
0.1μF
C2
10μF
C4
1μF
Connect the output capacitor between Vo terminal and GND terminal without fail in order to
stabilize output voltage. The output capacitor has a role to compensate for the phase of loop
gain and to reduce output voltage fluctuation when load is rapidly changed. When there is an
insufficient capacity value, there is a possibility to cause oscillation, and when the equivalent serial
resistance (ESR) of the capacitors is large, output voltage fluctuation is increased when load is
rapidly changed. About 22µF ceramic capacitors are recommended but output capacitor greatly
depends on temperature and load conditions. In addition, when various capacitors are
connected in series, the total phase allowance of loop gain becomes not sufficient, and oscillation
may result. Thoroughgoing confirmation at application temperature and under load range
conditions is requested.
The input capacitor plays a part to lower output impedance of a power supply connected to input
terminals (Vcc). When output impedance of this power supply increases, the input voltages
(Vcc, VIN) become unstable and there is a possibility of giving rise to oscillation and degraded
ripple rejection characteristics. The use of capacitors of about 10μF with low ESR, which provide
less capacity value changes caused by temperature changes, is recommended, but since input
capacitor greatly depends on characteristics of the power supply used for input, substrate wiring
pattern, thoroughgoing confirmation under the application temperature and load range, is
requested.
The input capacitor plays a part to lower output impedance of a power supply connected to input
terminals (VIN). When output impedance of this power supply increases, the input voltages (Vcc,
VIN) become unstable and there is a possibility of giving rise to oscillation and degraded ripple
rejection characteristics. The use of capacitors of about 10μF with low ESR, which provide less
capacity value changes caused by temperature changes, is recommended, but since input
capacitor greatly depends on characteristics of the power supply used for input, substrate wiring
pattern, thoroughgoing confirmation under the application temperature and load range, is
requested.
The present IC can set the output voltage buildup time by VREF terminal capacitor (C4) and R1 and
R2 values. When EN terminal is “High” or UVLO is reset, output voltage is built up by the time
constant determined by C4, R1, and R2. It is recommended to use capacitors (B special) with
little capacity value change caused by temperature change for C4.
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8/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Directions for pattern layout of PCB
■ BD3507HFV Evaluation Board Circuit
U1
VCC
1
GND
BD3507HFV
VCC
GND
6
C1
VCC
VREF
EN
SW
2
5
VREF
EN
C5
VIN
3
VIN
Vo
■ BD3507HFV Evaluation Board Application Components
Part No Value
Company
Parts Name
R5_2
Vo
4
C4_1
C3
ROHM
VR
R5_1
C4_2
Part No
Value
Company
C1
1μF
MURATA
GRM18 Series
BD3507HFV
Parts Name
U1
-
R5_1
22k
ROHM
MCR03 Series
C3
10μF
MURATA
GRM21 Series
R5_2
11k
ROHM
MCR03 Series
C4_1
22μF
MURATA
GRM31 Series
1μF
MURATA
GRM18 Series
C4_2
C5
■ BD3507HFV Evaluation Board Layout
Silk Screen
Mid Layer 2
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Mid Layer 1
TOP Layer
Bottom Layer
9/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●About heat loss
In designing heat, operate the apparatus within the following conditions.
(Because the following temperatures are warranted temperature, be sure to take margin, etc. into account.)
1. Ambient temperature Ta shall be not more than 100°C.
2. Chip junction temperature Tj shall be not more than 150°C.
Chip junction temperature Tj can be considered under the following two cases.
①Chip junction temperature Tj is found
from IC surface temperature TC under
actual application conditions:
Tj=TC+θj-c×W
＜Reference value＞
θj-c:HVSOF6 30℃/W
②Chip junction temperature Tj is found from ambient temperature Ta:
Tj=Ta+θj-a×W
＜Reference value＞
θj-a:HVSOF6 243.9℃/W Single-layer substrate
(substrate surface copper foil area: less 3%)
147.1℃/W Single-layer substrate
2
(substrate surface copper foil area:100mm )
89.3℃/W Single-layer substrate
2
(substrate surface copper foil area:900mm )
73.5℃/W Single-layer substrate
2
(substrate surface copper foil area:2500mm )
3
Substrate size 70×70×1.6mm
When multilayer substrates are used, if any GND pattern is present in the inner layer, arrange heat radiation vias on the
package rear side. Because the present package size is as small as 1.0 x 1.6 mm and vias are unable to be arranged in a
large quantity at the lower part of IC, the pattern is expanded as illustrated below and the number of vias is increased to
obtain superb heat radiation characteristics (the figure below is an image figure only, and the size and the quantity of vias
that match the condition must be designed into patterns).
Most of heat loss in BD3507HFV occurs at the output N-channel FET. The power lost is determined by multiplying the
voltage between VIN and Vo by the output current. Confirm the VIN and Vo voltages used and output current conditions,
and check with the thermal derating characteristics. As this IC employs the power PKG, the thermal derating characteristics
significantly depends on the pc board conditions. When designing, care must be taken to the size of a pc board to be used.
Power dissipation (W) = {Input voltage (VIN) – Output voltage (V0≒VREF)}×Io (averaged)
Ex.) If VIN = 1.8 volts, V0=1.2 volts, and Io (averaged)=0.5 A, the power dissipation is given by the following:
Power dissipation (W) =(1.8 volts – 1.2 volts) × 0.5 (A)
= 0.3 W
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10/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Example of applied circuit
Specifications: High side switch of low-voltage power supply line (1.2-2.5V)
Characteristics: RON = 300 mΩ, lo max) = 550 mA, with soft start function and overheat protection circuit equipped.
Example Circuit
VCC
VCC
GND
VCC
R1
C1
VIN
VREF
VREF
EN
ON/OFF
C4
VIN
VO
C2
Vo
C3
Ceramic Capacitor
●Equivalent Circuit
2pin (EN)
1pin (VCC)
Vcc
3pin (VIN)
VIN
4pin (Vo)
5pin (VREF)
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11/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Notes for use
1. Absolute maximum ratings
For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working
temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because
it is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute
maximum rating, physical safety measures are requested to be taken, such as fuses, etc.
2. GND potential
Bring the GND terminal potential to the minimum potential in any operating condition.
3. Thermal design
Consider permissible dissipation (Pd) under actual working condition and carry out thermal design with sufficient margin
provided.
4. Terminal-to-terminal short-circuit and erroneous mounting
When the present IC is mounted to a printed circuit board, take utmost care to direction of IC and displacement. In the
event that the IC is mounted erroneously, IC may be destroyed. In the event of short-circuit caused by foreign matter that
enters in a clearance between outputs or output and power-GND, the IC may be destroyed.
5. Operation in strong electromagnetic field
The use of the present IC in the strong electromagnetic field may result in maloperation, to which care must be taken.
6. Built-in thermal shutdown protection circuit
The present IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C
(standard value) and has a -15°C (standard value) hysteresis width. When the IC chip temperature rises and the TSD
circuit operates, the output terminal is brought to the OFF state. The built-in thermal shutdown protection circuit (TSD
circuit) is first and foremost intended for interrupt IC from thermal runaway, and is not intended to protect and warrant the
IC. Consequently, never attempt to continuously use the IC after this circuit is activated or to use the circuit with the
activation of the circuit premised.
7. Capacitor across output and GND
In the event a large capacitor is connected across output and GND, when Vcc and VIN are short-circuited with 0V or GND
for some kind of reasons, current charged in the capacitor flows into the output and may destroy the IC. Use a capacitor
smaller than 1000μF between output and GND.
8. Inspection by set substrate
In the event a capacitor is connected to a pin with low impedance at the time of inspection with a set substrate, there is a
fear of applying stress to the IC. Therefore, be sure to discharge electricity for every process. As electrostatic
measures, provide grounding in the assembly process, and take utmost care in transportation and storage. Furthermore,
when the set substrate is connected to a jig in the inspection process, be sure to turn OFF power supply to connect the jig
and be sure to turn OFF power supply to remove the jig.
9. IC terminal input
+
The present IC is a monolithic IC and has a P substrate and P isolation between elements.
With this P layer and N layer of each element, PN junction is formed, and when the potential relation is
GND>terminal A>terminal B, PN junction works as a diode, and
Terminal B>GND terminal A, PN junction operates as a parasitic transistor.
The parasitic element is inevitably formed because of the IC construction. The operation of the parasitic element gives
rise to mutual interference between circuits and results in malfunction, and eventually, breakdown. Consequently, take
utmost care not to use the IC to operate the parasitic element such as applying voltage lower than GND (P substrate) to
the input terminal.
Resistor
Transistor (NPN)
Pin A
Pin B
C
Pin B
B
Pin A
N
P+
N
P
P+
GND
N
N
P substrate
Parasitic element
E
P
+
Parasitic
element
N
B
P
P
+
N
C
E
P substrate
Parasitic element
GND
GND
GND
Parasitic
element
Other adjacent elements
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12/15
2010.05 - Rev.A
Technical Note
BD3507HFV
10. GND wiring pattern
If there are a small signal GND and a high current GND, it is recommended to separate the patterns for the high current
GND and the small signal GND and provide a proper grounding to the reference point of the set not to affect the voltage at
the small signal GND with the change in voltage due to resistance component of pattern wiring and high current. Also for
GND wiring pattern of component externally connected, pay special attention not to cause undesirable change to it.
11 Input terminals (VCC,VIN,EN,VREF)
In the present IC, EN terminal, VIN terminal, VCC terminal, and VREF terminal have an independent construction. In
addition, in order to prevent malfunction at the time of low input, the UVLO function is equipped with the VCC terminal.
They begin to start output voltage when all the terminals reach threshold voltage without depending on the input order of
input terminals.
12. Heat sink
Heatsink is connected to SUB, which should be short-circuited to GND. Solder the heatsink to a pc board properly, which
offers lower thermal resistance.
13. Operating range
Within the operating range, the operation and function of the circuits are generally guaranteed at an ambient temperature
within the range specified. The values specified for electrical characteristics may not be guaranteed, but drastic change
may not occur to such characteristics within the operating range.
14. For the present product, thoroughgoing quality control is carried out, but in the event that applied voltage, working
temperature range, and other absolute maximum rating are exceeded, the present product may be destroyed. Because
it is unable to identify the short mode, open mode, etc., if any special mode is assumed, which exceeds the absolute
maximum rating, physical safety measures are requested to be taken, such as fuses, etc.
15. In the event that load containing a large inductance component is connected to the output terminal, and generation of
back-EMF at the start-up and when output is turned OFF is assumed, it is requested to insert a protection diode.
(Example)
OUTPUT PIN
HVSOF6 land pattern
MIE
b2
D3
e
E3
L2
Unit:mm
Land Pitch
e
Land Space
MIE
Land Length
l2
Land Width
b2
0.50
2.20
0.55
0.25
Pad Length
D3
Pad Width
E3
1.60
1.60
In actually designing, optimize in accordance with the condition.
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13/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Power Dissipation
HVSOF 6
2.5
Power Dissipation ：Pd （W)
2.0
③1.70W
1.5
②1.40W
1.0
①0.85W
0.5
0.0
0
25
50
75
100
125
150
Ambient Temperature：Ta(℃)
①:PCB 1st layer (Cu-area : 100mm2)
θja = 147.1℃/W
②:PCB 1st layer (Cu-area : 900mm2)
θja = 89.3℃/W
③:PCB 1st layer (Cu-area : 2500mm2)
θja = 73.5℃/W
PCB size : 70mm×70mm×1.6mm
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© 2010 ROHM Co., Ltd. All rights reserved.
14/15
2010.05 - Rev.A
Technical Note
BD3507HFV
●Ordering part number
B
D
3
Part No.
5
0
7
Part No.
H
F
V
-
Package
HFV : HVSOF6
T
R
Packaging and forming specification
TR: Embossed tape and reel
HVSOF6
<Tape and Reel information>
(1.5)
(0.45)
6 5 4
Embossed carrier tape
Quantity
3000pcs
TR
The direction is the 1pin of product is at the upper right when you hold
( reel on the left hand and you pull out the tape on the right hand
(0.15)
(1.4)
1 2 3
Tape
Direction
of feed
(1.2)
)
1pin
0.145±0.05
0.75Max.
3.0±0.1
2.6±0.1
(MAX 2.8 include BURR)
1.6±0.1
(MAX 1.8 include BURR)
S
0.1 S
0.22±0.05
Direction of feed
0.5
Reel
(Unit : mm)
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© 2010 ROHM Co., Ltd. All rights reserved.
15/15
∗ Order quantity needs to be multiple of the minimum quantity.
2010.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
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http://www.rohm.com/contact/
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© 2010 ROHM Co., Ltd. All rights reserved.
R1010A