ROHM BD4156MUV

Power Management Switch IC Series for PCs and Digital Consumer Product
Power Switch for
ExpressCardTM
No. 09029EAT02
BD4156MUV
●Description
BD4156MUV is a power management switch IC for the next generation PC card (ExpressCardTM) developed by the PCMCIA.
TM
TM
It conforms to the PCMCIA ExpressCard Standard, ExpressCard Compliance Checklist. The power switch offers a
number of functions - card detector, and system status detector - which are ideally suited for laptop and desktop computers.
●Features
1)
2)
3)
4)
5)
6)
7)
8)
9)
10)
11)
12)
13)
TM
Incorporates three low on-resistance FETs for ExpressCard .
Incorporates an FET for output discharge.
Incorporates an enabler.
Incorporates under voltage lockout (UVLO) protection.
Employs an SSOP-B20 package.
Built-in thermal shutdown protector (TSD).
Built-in soft start function.
Incorporates an overcurrent protection (OCP).
Built-in enable signal for PLL
TM
Built-in Pull up resistance for detecting ExpressCard
TM
Conforms to the ExpressCard Standard.
TM
Conforms to the ExpressCard Compliance Checklist.
TM
Conforms to the ExpressCard Implementation Guideline.
●Applications
TM
Laptop and desktop computers, and other ExpressCard equipped digital devices.
●Product Lineup
Parameter
Package
BD4156MUV
VQFN020V4040
TM
“ExpressCard ” is a registered trademark registered of the PCMCIA (Personal Computer Memory Card International
Association).
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c 2009 ROHM Co., Ltd. All rights reserved.
○
1/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●ABSOLUTE MAXIMUM RATINGS
◎BD4156MUV
Parameter
Symbol
Limit
Unit
11
Input Voltage
V3AUX_IN, V3_IN, V15_IN
Logic Input Voltage 1
EN,CPPE#,CPUSB#,SYSR,
PERST_IN#,RCLKEN
-0.3～V3AUX_IN+0.3 *11
V
Logic Output Voltage 1
RCLKEN
-0.3～V3AUX_IN+0.3 *11
V
Logic Output Voltage 2
PERST#
-0.3～V3AUX_IN+0.3
V
V3AUX,V3, V15
-0.3～5.0 *11
V
Output Current 1
IOV3AUX
1.0
A
Output Current 2
IOV3
2.0
A
Output Current 3
IOV15
2.0
Output Voltage
Power Dissipation 1
-0.3～5.0 *
Pd1
V
A
12
W
13
W
0.34 *
Power Dissipation 2
Pd2
Operating Temperature Range
Topr
-40～+100
℃
Storage Temperature Range
Tstg
-55～+150
℃
Tjmax
+150
℃
Maximum Junction Temperature
0.70 *
*11 Not to exceed Pd.
*12 Reduced by 2.7mW for each increase in Ta of 1℃ over 25℃
*13 Reduced by 5.6mW for each increase in Ta of 1℃ over 25℃(When mounted on a board 70mm×70mm×1.6mm Glass-epoxy PCB).
●OPERATING CONDITIONS (Ta=25℃)
◎BD4156MUV
Parameter
Symbol
MIN
MAX
Unit
Input Voltage 1
V3AUX_IN
3.0
3.6
V
Input Voltage 2
V3_IN
3.0
3.6
V
Input Voltage 3
V15_IN
1.35
1.65
V
Logic Input Voltage 1
EN
-0.3
3.6
V
Logic Input Voltage 2
CPPE#,CPUSB#,SYSR,
PERST_IN#,RCLKEN
0
V3AUX_IN
V
Logic Output Voltage 1
RCLKEN
0
V3AUX_IN
V
Logic Output Voltage 2
PERST#
0
V3AUX_IN
V
Output Current 1
IOV3AUX
0
275
mA
Output Current 2
IOV3
0
1.3
A
Output Current 3
IOV15
0
650
mA
★ This product is not designed to offer protection against radioactive rays.
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c 2009 ROHM Co., Ltd. All rights reserved.
○
2/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●ELECTRICAL CHARACTERISTICS (unless otherwise noted, Ta=25℃, VEN=3.3V, V3AUX_IN =V3_IN=3.3V, V15_IN=1.5V)
Standard Value
Parameter
Symbol
Unit
Condition
MIN
TYP
MAX
VEN=0V
Standby Current
IST
40
80
uA
(Include IEN, IRCLKEN)
Bias Current 1
Icc1
120
250
uA
VSYSR=0V
Bias Current 2
Icc2
250
500
uA
VSYSR=3.3V
[Enable]
High Level Enable Input Voltage
VENHI
2.0
5.5
V
Low Level Enable Input Voltage
VENLOW
-0.2
0.8
V
Enable Pin Input Current
IEN
10
30
uA
VEN=0V
[Logic]
High Level Logic Input Voltage
VLHI
2.0
V
Low Level Logic Input Voltage
VLLOW
0.8
V
0
1
uA
CPPE#=3.6V
ICPPE#
10
30
uA
CPPE#=0V
0
1
uA
CPUSB#=3.6V
ICPUSB#
10
30
uA
CPUSB#=0V
0
1
uA
SYSR=3.6V
Logic Pin Input Current
ISYSR
10
30
uA
SYSR=0V
0
1
uA
PERST_IN#=3.6V
IPRT_IN#
10
30
uA
PERST_IN#=0V
0
1
uA
RCLKEN=3.6V
IRCLKEN
10
30
uA
RCLKEN=0V
RCLKEN Low Voltage
VRCLKEN
0.1
0.3
V
IRCLKEN=0.5mA
RCLKEN Leak Current
IRCLKEN
1
uA
VRCLKEN=3.65V
[Switch V3AUX]
On Resistance
RV3AUX
120
220
mΩ
Tj=-10～100℃ *
Discharge On Resistance
RV3AUX Dis
60
150
Ω
[Switch V3]
On Resistance
RV3
42
90
mΩ
Tj=-10～100℃ *
Discharge On Resistance
RV3Dis
60
150
Ω
[Switch V15]
On Resistance
RV15
45
90
mΩ
Tj=-10～100℃ *
Discharge On Resistance
RV15Dis
60
150
Ω
[Over Current Protection]
V3 Over Current
OCPV3
1.3
A
V3AUX Over Current
OCPV3AUX
0.275
A
V15 Over Current
OCPV15
0.65
A
[Under Voltage Lockout]
V3_IN UVLO OFF Voltage
VUVLOV3_IN
2.60
2.80
3.00
V
sweep up
V3_IN Hysteresis Voltage
⊿VUVLOV3_IN
50
100
150
mV
sweep down
V3AUX_IN UVLO OFF Voltage VUVLOV3AUX_IN
2.60
2.80
3.00
V
sweep up
V3AUX_IN Hysteresis Voltage
⊿VUVLOV3AUX_IN
50
100
150
mV
sweep down
V15_IN UVLO OFF Voltage
VUVLOV15_IN
1.10
1.20
1.30
V
sweep up
V15_IN Hysteresis Voltage
⊿VUVLOV15_IN
50
100
150
mV
sweep down
[POWER GOOD]
V3 POWER GOOD Voltage
PGV3
2.700
2.850
3.000
V
V3AUX POWER GOOD
2.700
2.850
3.000
V
PGV3AUX
Voltage
V15 POWER GOOD Voltage
PGV15
1.200
1.275
1.350
V
PERST# LOW Voltage
VPERST#Low
0.1
0.3
V
IPERST=0.5mA
PERST# HIGH Voltage
VPERST#HIGH
3.0
V
PERST# Delay Time
TPERST#
4
20
ms
PERST# assertion time
Tast
500
ns
[OUTPUT RISE TIME]
V3_IN to V3
TV3
0.1
3
ms
V3AUX_IN to V3AUX
TV3AUX
0.1
3
ms
V15_IN to V15
TV15
0.1
3
ms
* Design target
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c 2009 ROHM Co., Ltd. All rights reserved.
○
3/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●Reference data
CPPE#(2V/div)
CPPE#(2V/div)
SYSR(2V/div)
V3(2V/div)
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V3AUX(2V/div) RV3=3.3Ω
RV3AUX=13.2Ω
RV15=3Ω
V3AUX(2V/div)
V15(1V/div)
V15(1V/div)
5.0ms/div
Fig.1
V15(1V/div)
5.0ms/div
Card Assert/ De-assert
(Active)
Fig.2
Card Assert/De-assert
(Standby)
SYSR(2V/div)
V3AUX(2V/div)
V15(1V/div)
5.0ms/div
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V3AUX(2V/div)
V15(1V/div)
V15(1V/div)
500μs/div
500μs/div
Fig.5
Wakeup Wave Form
(Card Assert)
EN(2V/div)
V3(2V/div)
V3AUX(2V/div)
Fig.6
CPPE#(2V/div)
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V15(1V/div)
V15(1V/div)
500μs/div
500μs/div
Fig.8
Wakeup Wave Form
(Standby→Active)
CPUSB#(2V/div)
Wakeup Wave Form
(USB2.0 Assert)
SYSR(2V/div)
V3AUX(2V/div)
V15(1V/div)
Fig.7
Wakeup Wave Form
(Shut Down→Active)
CPUSB#(2V/div)
CPPE#(2V/div)
V3(2V/div)
Fig.4 System Active
⇔Standby(No Card)
5.0ms/div
Fig.3
System Active
⇔Standby( Card Present)
500μs/div
Fig.9
Power Down Wave Form
(Card De-assert)
EN(2V/div)
SYSR(2V/div)
V3(2V/div)
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V3AUX(2V/div)
V15(1V/div)
V15(1V/div)
V3AUX(2V/div)
500μs/div
Fig.10 Power Down Wave Form
(USB2.0 De-assert)
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c 2009 ROHM Co., Ltd. All rights reserved.
○
V15(1V/div)
5.0ms/div
500μs/div
Fig.11
Power Down Wave Form
(Active→Shut Down)
4/23
Fig.12
Power Down Wave Form
(Active→Standby)
2009.05 - Rev.A
Technical Note
BD4156MUV
CPPE#(2V/div)
CPPE#(2V/div)
CPPE#(2V/div)
V3(2V/div)
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V3AUX(2V/div)
V3AUX(2V/div)
RCLKEN(2V/div)
PERST#(2V/div)
PERST#(2V/div)
5.0ms/div
5.0ms/div
Fig.13 PERST# Wave Form
(Card Assert/ De-assert)
CPUSB#(2V/div)
5.0ms/div
Fig.14 RCLKEN Wave Form
(Card Assert/ De-assert)
PERST_IN#(2V/div)
PERST_IN#(2V/div)
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V3AUX(2V/div)
RCLKEN(2V/div)
V3(2V/div)
5.0ms/div
1.0ms/div
V3_IN(2V/div)
V3AUX(2V/div)
V15(1V/div)
500μs/div
1.0ms/div
Fig.17 PERST# Wave Form
(PERST_IN# Input)
V3AUX_IN(2V/di
v)
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V15(1V/div)
V3_IN(2V/div)
V3(2V/div)
Fig.18 RCLKEN Wave Form
(PERST_IN# Input)
V15_IN(2V/div)
V3(2V/div)
V3AUX(2V/div)
V15(1V/div)
500μs/div
500μs/div
Fig.19 Output Voltage
(V3_IN:OFF→ON)
V3AUX(2V/div)
RCLKEN(2V/div)
PERST#(2V/div)
Fig.16 RCLKEN Wave Form
(USB2.0 Assert/ De-assert)
Fig.15 PERST# Wave Form
(USB2.0 Assert/ De-assert)
Fig.20 Output Voltage
(V3AUX_IN:OFF→ON)
V3AUX_IN(2V/di
v)
Fig.21 Output Voltage
(V15_IN:OFF→ON)
V15_IN(2V/div)
V3(2V/div)
V3(2V/div)
V3AUX(2V/div)
V3AUX(2V/div)
V3AUX(2V/div)
V15(1V/div)
RV3=3.3Ω
RV3AUX=13.2Ω
RV15=3Ω
500μs/div
Fig.22 Output Voltage
(V3_IN:ON→OFF)
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c 2009 ROHM Co., Ltd. All rights reserved.
○
V15(1V/div)
RV3=3.3Ω
RV3AUX=13.2Ω
RV15=3Ω
500μs/div
Fig.23 Output Voltage
(V3AUX_IN:ON→OFF)
5/23
RV3=3.3Ω
V15(1V/div) RV3AUX=13.2Ω
RV15=3Ω
500μs/div
Fig.24 Output Voltage
(V15_IN:ON→OFF)
2009.05 - Rev.A
Technical Note
BD4156MUV
●BLOCK DIAGRAM
3.3V/1.30A
V3
V3_IN
2
3.3V
5
VD
4
V3_IN
3
V3
TSD,CL,UVLO
3.3V AUX/275mA
V3AUX_IN
17
15
VD
V3AUX
3.3V
TSD,CL,UVLO_AUX
V15_IN
V15
12
V15_IN
V3AUX_IN
14
1.5V
1.5V/625mA
11
13
V3AUX_IN
VD
V15
CPPE#
10
Input
9
logic
CPUSB#
SYSR
EN,SYSR,CPUSB#,CPPE#
V3_IN,V3AUX_IN,V15_IN
Block
Charge
VD
V15_IN
UVLO
lock out
Pump
UVLO_AUX
GND
●PHYSICAL DIMENSIONS
4.0±0.1
4.0±0.1
D4156
1.0Max.
Lot No.
5
20
6
16
10
0.5
2.1±0.1
0.4±0.1
0.02 +0.03
-0.02
(0.22)
S
15
PERST_IN#
Under
voltage
1.0
6
CL
V3_IN
V3AUX_IN
1
PERST#
TSD
Thermal
protection
Reference
20
C0.2 2.1±0.1
8
V3,V3AUX,V15
EN
0.08 S
RCLKEN
good
TSD,CL,UVLO
1
V3AUX_IN
18
Power
11
●PIN FUNCTION
PIN No
PIN NAME
1
SYSR
2
V3_IN
3
V3
4
V3_IN
5
V3
6
PERST_IN#
7
GND
8
PERST#
CPUSB#
9
10
CPPE#
11
V15
12
V15_IN
13
V15
14
V15_IN
15
V3AUX
16
TEST
17
V3AUX_IN
18
RCLKEN
19
20
N.C.
EN
7
PIN FUNCTION
Logic input pin
V3 input pin
V3 output pin
V3 input pin
V3 output pin
PERST# control input pin (SysReset#)
GND pin
Logic output pin
Logic input pin
Logic input pin
V15 output pin
V15 input pin
V15 output pin
V15 input pin
V3AUX output pin
Test pin
V3AUX input pin 1
Reference clock enable signal /
Power good signal (No delay)
Must be open or GND.
Enable input pin
0.25 +0.05
-0.04
VQFN020V4040 Package (Unit:mm)
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○
6/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●Description of block operation
EN
With an input of 2.0 volts or higher, this terminal goes HIGH to activate the circuit, and goes LOW to deactivate the circuit
(with the standby circuit current of 40 μA), It discharges each output and lowers output voltage when the input falls to 0.8 volts
or less.
V3_IN, V15_IN, and V3AUX_IN
These are the input terminals for each channel of a 3ch switch. V3_IN and V15_IN terminals have two pins each, which
should be short-circuited on the pc board with a thick conductor. A large current runs through these three terminals : (V3_IN:
1.35A; V3AUX_IN: 0.275 A; and V15_IN: 0.625 A). In order to lower the output impedance of the connected power supply, it
is recommended that ceramic capacitors (with B-type characteristics or better) be provided between these terminals and the
ground. Specifically, the capacitors should be on the order of 1 μF between V3_IN and GND, and between V15_IN and GND;
and on the order of 0.1 μF between V3AUX_IN and GND.
V3, V15, and V3AUX
These are the output terminals for each switch. The V3 and V15 terminals have two pins each, which should be
short-circuited on the PC board and connected to an ExpressCard connector with a thick conductor, as short as possible. In
order to stabilize the output, it is recommended that ceramic capacitors (with B-type characteristics or better) be provided
between these terminals and the ground. Specifically, the capacitors should be on the order of 10 μF between V3 and GND,
and between V15 and GND; and on the order of 1 μF between V3AUX and GND.
CPPE#
This pin is used to find whether or not a PCI-Express signal compatible card is present. Turns to “High” level with an input of
2.0 volts or higher, which means that no card is provided, while it turns to “Low” level when the input is lowered to 0.8 volts or
less, which means that a card is provided. Controls the ON/OFF, switch selecting the proper mode based on the status of
the system.Pull up resistance (100kΩ～200kΩ) is built into, so the number of components is reduced.
CPUSB#
This pin is used to find whether or not a USB2.0 signal compatible card is present. Turns to “High” level with an input of 2.0
volts or higher, which means that no card is provided, while it turns to “Low” level when the input is lowered to 0.8 volts or less,
which means that a card is provided. Controls the ON/OFF switch, selecting the proper mode based on the system status.
Pull up resistance (100kΩ～200kΩ) is built into, so the number of components is reduced.
SYSR
This pin is used to detect the system status. Turns to “High” level with an input of 2.0 volts or higher, which means that the
system is activated, while it turns to “Low” level when the input is lowered to 0.8 volts or less, which means that the system is
on standby.
PERST_IN#
This pin is used to control the reset signal (PERST#) to a card from the system side. (Also referred to as “SysReset#” by
PCMCIA.) Turns to “High” level with an input of 2.0 volts or higher, and sets PERST# to “High” AND with a “Power Good”
output. Turns to “Low” level and sets PERST# to “Low” when the input falls to 0.8 volts or less.
PERST#
This pin is used to send a reset signal to a PCI-Express compatible card. Reset status is determined by the outputs,
PERST_IN#, CPPE# system status, and EN on/off status. Turns to “High” level and activates the PCI-Express compatible
card only if each output is within the “Power Good” threshold, with the card inserted and PERST_IN# turned to “High” level.
RCLKEN
This pin is used to send an enable signal to the reference clock. Activation status is determined by the outputs, CPPE#
system status, and EN on/off status. Turns to “High” level and activates the reference clock PLL only if each output is within
the “Power Good” threshold, with the card kept inserted.
TEST
This pin is used to test, which should be short-circuited to the GND. When it is short-circuited to V3AUX_IN, UVLO (V3_IN,
V15_IN) turns OFF.
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○
7/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●TIMING CHART
TM
Power ON/OFF Status of ExpressCard
System Status
Primary
Auxiliary
OFF
OFF
ON
ON
ON
ExpressCardTM Module
Status
ON
Power Switch Status
Primary
(+3.3V and +1.5V)
Auxiliary
(3.3V Aux)
Don’t care
OFF
OFF
De-asserted
OFF
OFF
Asserted
ON
ON
De-asserted
OFF
OFF
Asserted Before This
OFF
ON
Asserted After This
OFF
OFF
TM
ExpressCard
States Transition Diagram
SYSR=L
CP#=L→H
SYSR=H⇔L
CP#=H
SYSR=H
CP#=H→L
SYSR=L
CP#=H⇔L
V3AUX=OFF
V15=V3=OFF
SYSR=L→H
CP#=L
V3AUX=ON
V15=V3=ON
SYSR=H→L
CP#=L
SYSR=H
CP#=L→H
SYSR=L→H
CP#=L
V3AUX=ON
V15=V3=OFF
SYSR=H→L
CP#=L
SYSR=L
⇔
CP#=L
SYSR=H
CP#=H
System Status
Card Status
Stand-by Status
:SYSR=L
Card Asserted Status
:CP#=L
ON Status
:SYSR=H
Card De-asserted Status
:CP#=H
From ON to Stand-by Status :SYSR=H→L
From De-asserted to Asserted Status :CP#=H→L
From Stand-by to ON Status :SYSR=L→H
From Asserted to De-asserted Status :CP#=L→H
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○
8/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●EXPRESS CARD TIMING DIAGRAMS
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
PERST_IN#
a
CPPE#
Card Power
(V3AUX,V3,V15)
RCLKEN
b
PERST#
Tpd
a
b
c
d
e
f
g
REFCLK
g
c
d
e
f
Timing Signals-Card Present Before Host Power is On
Min
Max
System Dependent
100
System Dependent
System Dependent
100
4
20
10
Units
us
us
ms
ms
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
PERST_IN#
a
CPUSB#
Card Power
(V3AUX,V3,V15)
RCLKEN
Tpd
a
b
PERST#
REFCLK
(Either Tri-Stated or Off)
Min
Max
System Dependent
10
Units
ms
b
Timing Signals-USB Present Before Host Power is On
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○
9/23
2009.05 - Rev.A
Technical Note
BD4156MUV
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
PERST_IN#
CPPE#
Card Power
(V3AUX,V3,V15)
RCLKEN
a
PERST#
REFCLK
b
c
d
e
Tpd
a
b
c
d
e
Min
Max
100
10
System Dependent
System Dependent
4
10
Units
us
ms
ms
Timing Signals Host Power is On Prior to Card Insertion
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
PERST_IN#
CPUSB#
Card Power
(V3AUX,V3,V15)
RCLKEN
Tpd
a
PERST#
Min
-
Max
10
Units
ms
REFCLK
(Either Tri-Stated or Off)
a
Timing Signals Host Power is On Prior to USB Insertion
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○
10/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●APPLICATION INFORMATION (continued)
Host Power
(V3AUX_IN)
Host Power
(V3_IN,V15_IN,SYSR)
PERST_IN#
CPPE#
Card Power
(V3AUX,V3,V15)
RCLKEN
PERST#
REFCLK
(Either Tri-Stated or Off)
Timing Signals-Host System In Standby Prior to Card Insertion
Host Power
(V3AUX_IN)
Host Power
(V3_IN,V15_IN,SYSR)
PERST_IN#
CPUSB#
Card Power
(V3AUX,V3,V15)
RCLKEN
PERST#
REFCLK
(Either Tri-Stated or Off)
Timing Signals-Host System In Standby Prior to USB Insertion
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○
11/23
2009.05 - Rev.A
Technical Note
BD4156MUV
Host Power
(V3AUX_IN,
V3_IN,V15_IN)
c
PERST_IN
CPPE#
Card Power
(V3AUX,V3,V15)
d
RCLKEN
a
e
PERST#
REFCLK
b
Tpd
a
b
c
d
e
Min
Max
2
System Dependent
System Dependent
Load Dependent
2
Units
us
Tpd
a
b
Min
Max
System Dependent
Load Dependent
Units
us
Timing Signals Host Controlled Power Down
Host Power
(V3AUX_IN,
V3_IN,V15_IN)
a
PERST_IN
CPUSB#
Card Power
(V3AUX,V3,V15)
b
RCLKEN
PERST#
REFCLK
(Either Tri-Stated or Off)
Timing Signals Host Controlled Power Down
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c 2009 ROHM Co., Ltd. All rights reserved.
○
12/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●APPLICATION INFORMATION (continued)
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
e
EN
CPPE#
f
Card Power
(V3AUX,V3,V15)
RCLKEN
a
d
PERST#
c
b
REFCLK
Tpd
a
b
c
d
e
f
Min
Max
Load Dependent
System Dependent
500
2
System Dependent
System Dependent
Units
Tpd
a
b
c
Min
Max
Load Dependent
System Dependent
System Dependent
Units
ns
us
Timing Signals Controlled Power Down When EN Asserted
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
b
EN
CPUSB#
Card Power
(V3AUX,V3,V15)
c
a
RCLKEN
PERST#
REFCLK
(Either Tri-Stated or Off)
Timing Signals Controlled Power Down When EN Asserted
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○
13/23
2009.05 - Rev.A
Technical Note
BD4156MUV
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
RERST_IN#
CPPE#
Card Power
(V3AUX,V3,V15)
a
RCLKEN
d
PERST#
b
REFCLK
c
Tpd
a
b
c
d
Min
Max
Load Dependent
500
System Dependent
2
Units
Tpd
a
Min
Max
Load Dependent
Units
ns
us
Timing Signals-Surprise Card Removal
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
RERST_IN#
CPUSB#
Card Power
(V3AUX,V3,V15)
a
RCLKEN
PERST#
REFCLK
(Either Tri-Stated or Off)
Timing Signals-Surprise USB Removal
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c 2009 ROHM Co., Ltd. All rights reserved.
○
14/23
2009.05 - Rev.A
Technical Note
BD4156MUV
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
SYSR
CPPE#
Card Power
(V3AUX)
a
Card Power
(V3,V15)
b
b
c
PERST#
d
e
REFCLK
RCLKEN=OPEN, PERST_IN=3.3V,EN=3.3V
Tpd
a
b
c
d
e
Min
Max
System Dependent
4
20
2
System Dependent
System Dependent
Units
Tpd
a
Min
Max
System Dependent
Units
ms
us
Timing Signals Power state transitions (Signal applies for SYSR)
Host Power
(V3AUX_IN,V3_IN,
V15_IN)
SYSR
CPUSB#
Card Power
(V3AUX)
a
Card Power
(V3,V15)
PERST#
REFCLK
(Either Tri-Stated or Off)
RCLKEN=OPEN, PERST_IN=3.3V,EN=3.3V
Timing Signals Power state transitions (Signal applies for SYSR)
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c 2009 ROHM Co., Ltd. All rights reserved.
○
15/23
2009.05 - Rev.A
Technical Note
BD4156MUV
V3AUX_IN
EN
V3_IN,SYSR
V15_IN
PERST_IN#
CPPE#
Card Power
(V3AUX)
a
Card Power
(V3,V15)
b
b
c
PERST#
e
d
Tpd
a
b
c
d
e
Min
Max
System Dependent
4
20
2
System Dependent
System Dependent
Units
Tpd
a
Min
Max
System Dependent
Units
ms
us
REFCLK
RCLKEN=OPEN, PERST_IN# is asserted in advance of power changes.
Timing Signals – Power state transitions
(SYSR and EN are connected to V3_IN/V3AUX_IN.)
V3AUX_IN
EN
V3_IN,SYSR
V15_IN
PERST_IN#
CPUSB#
Card Power
(V3AUX)
a
Card Power
(V3,V15)
PERST#
REFCLK
(Either Tri-Stated or Off)
RCLKEN=OPEN, PERST_IN# is asserted in advance of power changes.
Timing Signals – Power state transitions
(SYSR and EN are connected to V3_IN/V3AUX_IN.)
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c 2009 ROHM Co., Ltd. All rights reserved.
○
16/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●APPLICATION CIRCUIT (CIRCUIT for ExpressCardTM Compliance Checklist)
CPPE#(1)
CPPE#(10pin)
RCLKEN(18pin)
CPUSB#(2)
CPUSB#(9pin)
V3_IN(2,4pin)
3.3V(3)
V3(3,5pin)
V3AUX_IN(17pin)
3.3V(7)
3.3Vaux(8)
BD4156MUV
3.3Vaux(4)
V3AUX(15pin)
V15_IN(12,14pin)
1.5V(9)
1.5V(5)
V15(11,13pin)
PERST_IN#(6pin)
SysReset#(10)
PERST#(6)
PERST#(8pin)
EN(20pin)
TEST(16pin)
SYSR(1pin)
GND(7pin)
●Heat loss
Thermal design should allow the device to operate within the following conditions. Note that the temperatures listed are the
allowed temperature limits. Thermal design should allow sufficient margin from these limits.
1. Ambient temperature Ta can be no higher than 100°C.
2. Chip junction temperature Tj can be no higher more than 150°C.
Chip junction temperature Tj can be determined as follows:
①Chip junction temperature Tj is calculated
from IC surface temperature TC under
actual application conditions:
Tj=TC+θj-c×W
<Reference value>
θj-c:VQFN020V4040
**℃/W
②Chip junction temperature Tj is calculated from ambient temperature Ta:
Tj=TC+θj-a×W
<Reference value>
θj-a:VQFN020V4040
**℃/W (IC only)
**℃/W Single-layer substrate
(substrate surface copper foil area: less than 3%)
3
Substrate size 70×70×1.6mm (thermal vias in the board.)
Most of heat loss in the BD4156MUV occurs at the output switch.
on-resistance by the square of output current of each switch.
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c 2009 ROHM Co., Ltd. All rights reserved.
○
17/23
The power lost is determined by multiplying the
2009.05 - Rev.A
Technical Note
BD4156MUV
●EQUIVALENT CIRCUIT
1pin<SYSR>
2,4pin<V3_IN>
V3AUX_IN
3,5pin<V3>
V3_IN
V3AUX_IN
V3
6pin<PERST_IN#>
V3AUX_IN
8pin<PERST#>
V3AUX_IN
10pin<CPPE#>
V3AUX_IN
9pin<CPUSB#>
V3AUX_IN
V3AUX_IN
11,13pin<V15>
V3AUX_IN
12,14pin<V15_IN>
V3AUX_IN
V3_IN
V15
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c 2009 ROHM Co., Ltd. All rights reserved.
○
18/23
2009.05 - Rev.A
Technical Note
BD4156MUV
15pin<V3AUX>
16pin<TEST>
17pin<V3AUX_IN>
V3AUX_IN
V3AUX
18pin<RCLKEN >
20pin<EN>
V3AUX_IN
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c 2009 ROHM Co., Ltd. All rights reserved.
○
V3AUX_IN
19/23
V3AUX_IN
2009.05 - Rev.A
Technical Note
BD4156MUV
●USE NOTES
1.Absolute maximum ratings
Although quality is rigorously controlled, the device may be destroyed when applied voltage, operating temperature, etc.
exceeds its absolute maximum rating. Because the source (short mode or open mode) cannot be identified once the IC is
destroyed, it is important to take physical safety measures such as fusing when implementing any special mode that
operates in excess of absolute rating limits.
2.Thermal design
Consider allowable loss (Pd) under actual operating conditions and provide sufficient margin in the thermal design.
3.Terminal-to-terminal short-circuit and mis-mounting
When the mounting the IC to a printed circuit board, take utmost care to assure the position and orientation of the IC are
correct. In the event that the IC is mounted erroneously, it may be destroyed. The IC may also be destroyed when a
short-circuit is caused by foreign matter introduced into the clearance between outputs, or between an output and
power-GND.
4.Operation in strong electromagnetic fields
Using the IC in strong electromagnetic fields may cause malfunctions. Exercise caution in respect to electromagnetic
fields.
5.Built-in thermal shutdown protection circuit
This IC incorporates a thermal shutdown protection circuit (TSD circuit). The working temperature is 175°C (standard
value) with a -15°C (standard value) hysteresis width. When the IC chip temperature rises the TSD circuit is activated,
while the output terminal is brought to the OFF state. The built-in TSD circuit is intended exclusively to shut down the IC in
a thermal runaway event, and is not intended to protect the IC or guarantee performance in these conditions. Therefore,
do not operate the IC after with the expectation of continued use or subsequent operation once this circuit is activated.
6.Capacitor across output and GND
When a large capacitor is connected across the output and GND, and the V3AUX_IN is short-circuited with 0V or GND for
any reason, current charged in the capacitor flows into the output and may destroy the IC. Therefore, use a capacitor
smaller than 1000 μF between the output and GND.
7.Set substrate inspection
Connecting a low-impedance capacitor to a pin when running an inspection with a set substrate may produce stress on the
IC. Therefore, be certain to discharge electricity at each process of the operation. To prevent electrostatic accumulation
and discharge in the assembly process, thoroughly ground yourself and any equipment that could sustain ESD damage,
and continue observing ESD-prevention procedures in all handling, transfer and storage operations. Before attempting to
connect the set substrate to the test setup, make certain that the power supply is OFF. Likewise, be sure the power supply
is OFF before removing the substrate from the test setup.
8.IC terminal input
+
This integrated circuit is a monolithic IC, with P substrate and P isolation between elements.
The P layer and N layer of each element form a, PN junction. When the potential relation is GND>terminal A>terminal B,
the PN junction works as a diode, and when terminal B>GND terminal A, the PN junction operates as a parasitic transistor.
Parasitic elements inevitably form, due to the nature of the IC construction. The operation of the parasitic element gives
rise to mutual interference between circuits and results in malfunction, and eventually, breakdown. Consequently, take
utmost care not to use the IC in a way that would cause the parasitic element to actively operate, such as applying voltage
lower than GND (P substrate) to the input terminal.
Resistor
Transistor (NPN)
Pin A
Pin B
C
B
Pin B
E
Pin A
N
P+
N
P+
P
N
N
P substrate
Parasitic element
GND
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c 2009 ROHM Co., Ltd. All rights reserved.
○
P+
Parasitic
element
B
N
P+
P
N
C
E
P substrate
Parasitic element
20/23
GND
GND
GND
Parasitic
element
Other adjacent elements
2009.05 - Rev.A
Technical Note
BD4156MUV
9. GND wiring pattern
If both a small signal GND and a high current GND are present, it is recommended that the patterns for the high current
GND and the small signal GND be separated. Proper grounding to the reference point of the set should also be provided.
In this way, the small signal GND voltage will by unaffected by the change in voltage stemming from the pattern wiring
resistance and the high current. Also, pay special attention to avoid undesirable wiring pattern fluctuations in any
externally connected GND component.
10. Electrical characteristics
The electrical characteristics in the Specifications may vary, depending on ambient temperature, power supply voltage,
circuit(s) externally applied, and/or other conditions. Therefore, please check all such factors, including transient
characteristics, that could affect the electrical characteristics.
11. Capacitors applied to input terminals
The capacitors applied to the input terminals (V3_IN, V3AUX_IN and V15_IN) are used to lower the output impedance of
the connected power supply. An increase in the output impedance of the power supply may result in destabilization of
input voltages (V3_IN, V3AUX_IN and V15_IN). It is recommended that a low-ESR capacitor be used, with a lower
temperature coefficient (change in capacitance vs. change in temperature), Recommended capacitors are on the order of
0.1 μF for V3AUX_IN, and1 μF for V3_IN and V15_IN. However, they must be thoroughly checked at the temperature and
with the load range expected in actual use, because capacitor selection depends to a significant degree on the
characteristics of the input power supply to be used and the conductor pattern of the PC board.
12. Capacitors applied to output terminals
Capacitors for the output terminals (V3, V3_AUX, and V15), should be connected between each of the output terminals and
GND. A low-ESR, low temperature coefficient output capacitor is recommended-on the order of 1 μF for V3 and V15
terminals, and 1μF less for V3_AUX. However, they must be thoroughly checked at the temperature and with the load
range expected in actual use, because capacitor selection depends to a significant degree on the temperature and the load
conditions.
13. Not of a radiation-resistant design.
14. Allowable loss (Pd)
With respect to the allowable loss, please refer to the thermal derating characteristics shown in the Exhibit, which serves as
a rule of thumb. When the system design causes the IC to operate in excess of the allowable loss, chip temperature will
rise, reducing the current capacity and decreasing other basic IC functionality. Therefore, design should always enable IC
operation within the allowable loss only.
15. Operating range
Basic circuit functions and operations are warranted within the specified operating range the working ambient temperature
range. Although reference values for electrical characteristics are not warranted, no rapid or extraordinary changes in
these characteristics are expected, provided operation is within the normal operating and temperature range.
16. The applied circuit example diagrams presented here are recommended configurations. However, actual design depends
on IC characteristics, which should be confirmed before operation. Also, note that modifying external circuits may impact
static, noise and other IC characteristics, including transient characteristics. Be sure to allow sufficient margin in the
design to accommodate these factors.
17. Wiring to the input terminals (V3 IN, V3AUX IN, and V15 IN) and output terminals (V3, V3AUX and V15) of the built-in FET
should be carried out with special care. Using unnecessarily long and/or thin conductors may decrease output voltage
and degrade other characteristics.
18. Heatsink
The heatsink is connected to the SUB, which should be short-circuited to the GND. Proper heatsink soldering to the PC
board should enable lower thermal resistance.
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○
21/23
2009.05 - Rev.A
Technical Note
BD4156MUV
●POWER DISSIPATION
◎BD4156MUV
Power Dissipation (Pd)
[W] 1.0
0.8
②0.70W
0.6
Mounted on board
70mm×70mm×1.6mm
Glass-epoxy PCB
θj-a=178.6℃/W
Without heat sink.
θj-a=367.6℃/W
0.4
①0.34W
0.2
0
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c 2009 ROHM Co., Ltd. All rights reserved.
○
25 50
75 100 125 150
Ambient Temperature (Ta)
[℃]
22/23
2009.05 - Rev.A
Technical Note
BD4156MUV
 Ordering part number
B
D
4
Part No.
1
5
6
M
Part No.
U
V
-
Package
MUV: VQFN020V4040
E
2
Packaging and forming specification
E2: Embossed tape and reel
VQFN020V4040
<Tape and Reel information>
4.0±0.1
4.0±0.1
2.1±0.1
1.0
0.4±0.1
1
6
16
0.5
Direction
of feed
E2
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
5
20
10
15
2500pcs
(0.22)
S
C0.2
Embossed carrier tape
Quantity
11
2.1±0.1
0.08
S
+0.03
0.02 –0.02
1.0MAX
1PIN MARK
Tape
+0.05
0.25 –0.04
1pin
Reel
(Unit : mm)
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○
23/23
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2009.05 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
http://www.rohm.com/contact/
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R0039A