EFM8SB20F16G-A-QFN24

EFM8 Sleepy Bee Family
EFM8SB2 Data Sheet
The EFM8SB2, part of the Sleepy Bee family of MCUs, is the
world’s most energy friendly 8-bit microcontrollers with a comprehensive feature set in small packages.
ENERGY FRIENDLY FEATURES
• Lowest MCU sleep current with supply
brownout detection (50 nA)
These devices offer lowest power consumption by combining innovative low energy techniques and short wakeup times from energy saving modes into small packages, making
them well-suited for any battery operated applications. With an efficient 8051 core, 6-bit
current reference, and precision analog, the EFM8SB2 family is also optimal for embedded applications.
• Lowest MCU active current with these
features (170 μA / MHz at 24.5 MHz clock
rate)
EFM8SB2 applications include the following:
• Ultra-fast wake up for digital and analog
peripherals (< 2 μs)
• Battery-operated consumer electronics
• Sensor interfaces
• Hand-held devices
• Industrial controls
Core / Memory
RAM Memory
(4352 bytes)
(up to 64 KB)
• Integrated low drop out (LDO) voltage
regulator to maintain ultra-low active
current at all voltages
Clock Management
CIP-51 8051 Core
(25 MHz)
Flash Program
Memory
• Lowest MCU sleep current using internal
RTC operating and supply brownout
detection (<300 nA)
Debug Interface
with C2
Energy Management
External
Oscillator
Low Power 20
MHz RC
Oscillator
External 32 kHz
RTC Oscillator
High Frequency
24.5 MHz RC
Oscillator
Internal LDO
Regulator
Power-On Reset
Brown-Out Detector
8-bit SFR bus
Serial Interfaces
UART
2 x SPI
I2C / SMBus
I/O Ports
External
Interrupts
General
Purpose I/O
Timers and Triggers
Pin Reset
Timers
0/1/2/3
PCA/PWM
Pin Wakeup
Watchdog
Timer
Real Time
Clock
Analog Interfaces
ADC
Comparator 0
Comparator 1
Internal Voltage
Reference
Security
16/32-bit CRC
Internal Current Reference
Lowest power mode with peripheral operational:
Normal
Idle
Suspend
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Rev. 1.1
EFM8SB2 Data Sheet
Feature List
1. Feature List
The EFM8SB2 highlighted features are listed below.
• Core:
• Pipelined CIP-51 Core
• Fully compatible with standard 8051 instruction set
• 70% of instructions execute in 1-2 clock cycles
• 25 MHz maximum operating frequency
• Memory:
• Up to 64 kB flash memory, in-system re-programmable
from firmware.
• Up to 4352 bytes RAM (including 256 bytes standard 8051
RAM and 4096 bytes on-chip XRAM)
• Power:
• Internal LDO regulator for CPU core voltage
• Power-on reset circuit and brownout detectors
• I/O: Up to 24 total multifunction I/O pins:
• Flexible peripheral crossbar for peripheral routing
• 5 mA source, 12.5 mA sink allows direct drive of LEDs
• Clock Sources:
• Internal 20 MHz low power oscillator with ±10% accuracy
• Internal 24.5 MHz precision oscillator with ±2% accuracy
• External RTC 32 kHz crystal
• External crystal, RC, C, and CMOS clock options
• Timers/Counters and PWM:
• 32-bit Real Time Clock (RTC)
• 6-channel programmable counter array (PCA) supporting
PWM, capture/compare, and frequency output modes with
watchdog timer function
• 4 x 16-bit general-purpose timers
• Communications and Digital Peripherals:
• UART
• 2 x SPI™ Master / Slave
• SMBus™/I2C™ Master / Slave
• External Memory Interface (EMIF)
• 16-bit/32-bit CRC unit, supporting automatic CRC of flash at
1024-byte boundaries
• Analog:
• Programmable current reference (IREF0)
• 10-Bit Analog-to-Digital Converter (ADC0)
• 2 x Low-current analog comparators
• On-Chip, Non-Intrusive Debugging
• Full memory and register inspection
• Four hardware breakpoints, single-stepping
• Pre-loaded UART bootloader
• Temperature range -40 to 85 ºC
• Single power supply 1.8 to 3.6 V
• QFP32, QFN32, and QFN24 packages
With on-chip power-on reset, voltage supply monitor, watchdog timer, and clock oscillator, the EFM8SB2 devices are truly standalone
system-on-a-chip solutions. The flash memory is reprogrammable in-circuit, providing non-volatile data storage and allowing field upgrades of the firmware. The on-chip debugging interface (C2) allows non-intrusive (uses no on-chip resources), full speed, in-circuit
debugging using the production MCU installed in the final application. This debug logic supports inspection and modification of memory
and registers, setting breakpoints, single stepping, and run and halt commands. All analog and digital peripherals are fully functional
while debugging. Each device is specified for 1.8 to 3.6 V operation and is available in 24-pin QFN, 32-pin QFN, or 32-pin QFP packages. All package options are lead-free and RoHS compliant.
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EFM8SB2 Data Sheet
Ordering Information
2. Ordering Information
EFM8 SB2 0 F 64 G – A – QFN32 R
Tape and Reel (Optional)
Package Type
Revision
Temperature Grade G (-40 to +85)
Flash Memory Size – 64 KB
Memory Type (Flash)
Family Feature Set
Sleepy Bee 2 Family
Silicon Labs EFM8 Product Line
Figure 2.1. EFM8SB2 Part Numbering
All EFM8SB2 family members have the following features:
• CIP-51 Core running up to 25 MHz
• Three Internal Oscillators (24.5 MHz, 20 MHz, and 16 kHz)
• SMBus / I2C
• 2 x SPI
• UART
• 6-Channel Programmable Counter Array (PWM, Clock Generation, Capture/Compare)
• 4 16-bit Timers
• 2 Analog Comparators
• 6-bit programmable current reference
• 10-bit Analog-to-Digital Converter with integrated multiplexer, voltage reference, and temperature sensor
• Low-current 32 kHz oscillator and Real Time Clock
• 16-bit CRC Unit
• Pre-loaded UART bootloader
In addition to these features, each part number in the EFM8SB2 family has a set of features that vary across the product line. The
product selection guide shows the features available on each family member.
EFM8SB20F64G-A-QFP32
64
4352
24
23
12
Yes
-40 to +85 C
QFP32
EFM8SB20F64G-A-QFN24
64
4352
16
15
8
Yes
-40 to +85 C
QFN24
EFM8SB20F32G-A-QFN32
32
4352
24
23
12
Yes
-40 to +85 C
QFN32
EFM8SB20F32G-A-QFP32
32
4352
24
23
12
Yes
-40 to +85 C
QFP32
EFM8SB20F32G-A-QFN24
32
4352
16
15
8
Yes
-40 to +85 C
QFN24
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Package
QFN32
Range
-40 to +85 C
Temperature
Yes
Pb-free
Comparator
12
Inputs
ADC Channels
23
I/Os (Total)
Digital Port
24
Memory (kB)
4352
Flash
64
Number
EFM8SB20F64G-A-QFN32
Ordering Part
RAM (Bytes)
(RoHS Compliant)
Table 2.1. Product Selection Guide
Rev. 1.1 | 2
EFM8SB2 Data Sheet
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Yes
-40 to +85 C
Package
Range
Temperature
(RoHS Compliant)
8
Pb-free
15
Inputs
Comparator
16
ADC Channels
4352
I/Os (Total)
Memory (kB)
Digital Port
16
RAM (Bytes)
EFM8SB20F16G-A-QFN24
Flash
Number
Ordering Part
Ordering Information
QFN24
Rev. 1.1 | 3
EFM8SB2 Data Sheet
System Overview
3. System Overview
3.1 Introduction
CIP-51 8051 Controller
Core
Power On
Reset/PMU
Wake
Reset
Debug /
Programming
Hardware
Digital Peripherals
64/32/16 KB ISP Flash
Program Memory
UART
256 Byte SRAM
Timers 0,
1, 2, 3
4096 Byte XRAM
PCA/WDT
C2D
VDD
Priority
Crossbar
Decoder
SMBus
Power Net
Analog
Power
VREG
Digital
Power
Crossbar Control
SFR
Bus
Port 1
Drivers
P1.n
Port 2
Drivers
P2.n
External Memory Interface
Control
Precision
24.5 MHz
Oscillator
Address
Data
Low Power
20 MHz
Oscillator
XTAL1
XTAL2
XTAL4
P0.n
CRC
SYSCLK
System Clock
Configuration
GND
XTAL3
Port 0
Drivers
SPI 0,1
External
Oscillator
Circuit
RTC
Oscillator
Analog Peripherals
Internal
External
VREF
VREF
10-bit
300ksps
ADC
AMUX
C2CK/RSTb
Port I/O Configuration
Comparators
VDD
VREF
Temp
Sensor
+
-+
6-bit
IREF
IREF0
GND
Figure 3.1. Detailed EFM8SB2 Block Diagram
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EFM8SB2 Data Sheet
System Overview
3.2 Power
All internal circuitry draws power from the VDD supply pin. External I/O pins are powered from the VIO supply voltage (or VDD on devices without a separate VIO connection), while most of the internal circuitry is supplied by an on-chip LDO regulator. Control over the
device power can be achieved by enabling/disabling individual peripherals as needed. Each analog peripheral can be disabled when
not in use and placed in low power mode. Digital peripherals, such as timers and serial buses, have their clocks gated off and draw little
power when they are not in use.
Table 3.1. Power Modes
Power Mode
Details
Mode Entry
Wake-Up Sources
Normal
Core and all peripherals clocked and fully operational
—
—
Set IDLE bit in PCON0
Any interrupt
Idle
• Core halted
• All peripherals clocked and fully operational
• Code resumes execution on wake event
Suspend
• Core and digital peripherals halted
• Internal oscillators disabled
• Code resumes execution on wake event
1. Switch SYSCLK to
HFOSC0 or LPOSC0
2. Set SUSPEND bit in
PMU0CF
•
•
•
•
RTC0 Alarm Event
RTC0 Fail Event
Port Match Event
Comparator 0 Rising
Edge
Sleep
•
•
•
•
•
1. Disable unused analog peripherals
2. Set SLEEP bit in
PMU0CF
•
•
•
•
RTC0 Alarm Event
RTC0 Fail Event
Port Match Event
Comparator 0 Rising
Edge
Most internal power nets shut down
Select circuits remain powered
Pins retain state
All RAM and SFRs retain state
Code resumes execution on wake event
3.3 I/O
Digital and analog resources are externally available on the device’s multi-purpose I/O pins. Port pins P0.0-P2.6 can be defined as general-purpose I/O (GPIO), assigned to one of the internal digital resources through the crossbar or dedicated channels, or assigned to an
analog function. Port pin P2.7 can be used as GPIO. Additionally, the C2 Interface Data signal (C2D) is shared with P2.7.
•
•
•
•
•
Up to 24 multi-functions I/O pins, supporting digital and analog functions.
Flexible priority crossbar decoder for digital peripheral assignment.
Two drive strength settings for each pin.
Two direct-pin interrupt sources with dedicated interrupt vectors (INT0 and INT1).
Up to 16 direct-pin interrupt sources with shared interrupt vector (Port Match).
3.4 Clocking
The CPU core and peripheral subsystem may be clocked by both internal and external oscillator resources. By default, the system
clock comes up running from the 20 MHz low power oscillator divided by 8.
•
•
•
•
•
•
Provides clock to core and peripherals.
20 MHz low power oscillator (LPOSC0), accurate to +/- 10% over supply and temperature corners.
24.5 MHz internal oscillator (HFOSC0), accurate to +/- 2% over supply and temperature corners.
External RTC 32 kHz crystal.
External RC, C, CMOS, and high-frequency crystal clock options (EXTCLK).
Clock divider with eight settings for flexible clock scaling: Divide the selected clock source by 1, 2, 4, 8, 16, 32, 64, or 128.
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EFM8SB2 Data Sheet
System Overview
3.5 Counters/Timers and PWM
Real Time Clock (RTC0)
The RTC is an ultra low power, 36 hour 32-bit independent time-keeping Real Time Clock with alarm. The RTC has a dedicated 32 kHz
oscillator. No external resistor or loading capacitors are required, and a missing clock detector features alerts the system if the external
crystal fails. The on-chip loading capacitors are programmable to 16 discrete levels allowing compatibility with a wide range of crystals.
The RTC module includes the following features:
• Up to 36 hours (32-bit) of independent time keeping.
• Support for external 32 kHz crystal or internal self-oscillate mode.
• Internal crystal loading capacitors with 16 levels.
• Operation in the lowest power mode and across the full supported voltage range.
• Alarm and oscillator failure events to wake from the lowest power mode or reset the device.
Programmable Counter Array (PCA0)
The programmable counter array (PCA) provides multiple channels of enhanced timer and PWM functionality while requiring less CPU
intervention than standard counter/timers. The PCA consists of a dedicated 16-bit counter/timer and one 16-bit capture/compare module for each channel. The counter/timer is driven by a programmable timebase that has flexible external and internal clocking options.
Each capture/compare module may be configured to operate independently in one of five modes: Edge-Triggered Capture, Software
Timer, High-Speed Output, Frequency Output, or Pulse-Width Modulated (PWM) Output. Each capture/compare module has its own
associated I/O line (CEXn) which is routed through the crossbar to port I/O when enabled.
•
•
•
•
•
•
•
•
•
16-bit time base.
Programmable clock divisor and clock source selection.
Up to six independently-configurable channels
8, 9, 10, 11 and 16-bit PWM modes (edge-aligned operation).
Frequency output mode.
Capture on rising, falling or any edge.
Compare function for arbitrary waveform generation.
Software timer (internal compare) mode.
Integrated watchdog timer.
Timers (Timer 0, Timer 1, Timer 2, and Timer 3)
Several counter/timers are included in the device: two are 16-bit counter/timers compatible with those found in the standard 8051, and
the rest are 16-bit auto-reload timers for timing peripherals or for general purpose use. These timers can be used to measure time intervals, count external events and generate periodic interrupt requests. Timer 0 and Timer 1 are nearly identical and have four primary
modes of operation. The other timers offer both 16-bit and split 8-bit timer functionality with auto-reload and capture capabilities.
Timer 0 and Timer 1 include the following features:
• Standard 8051 timers, supporting backwards-compatibility with firmware and hardware.
• Clock sources include SYSCLK, SYSCLK divided by 12, 4, or 48, the External Clock divided by 8, or an external pin.
• 8-bit auto-reload counter/timer mode
• 13-bit counter/timer mode
• 16-bit counter/timer mode
• Dual 8-bit counter/timer mode (Timer 0)
Timer 2 and Timer 3 are 16-bit timers including the following features:
• Clock sources include SYSCLK, SYSCLK divided by 12, or the External Clock divided by 8.
• 16-bit auto-reload timer mode
• Dual 8-bit auto-reload timer mode
• Comparator 0 or RTC0 capture (Timer 2)
• Comparator 1 or EXTCLK/8 capture (Timer 3)
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EFM8SB2 Data Sheet
System Overview
Watchdog Timer (WDT0)
The device includes a programmable watchdog timer (WDT) integrated within the PCA0 peripheral. A WDT overflow forces the MCU
into the reset state. To prevent the reset, the WDT must be restarted by application software before overflow. If the system experiences
a software or hardware malfunction preventing the software from restarting the WDT, the WDT overflows and causes a reset. Following
a reset, the WDT is automatically enabled and running with the default maximum time interval. If needed, the WDT can be disabled by
system software. The state of the RSTb pin is unaffected by this reset.
The Watchdog Timer integrated in the PCA0 peripheral has the following features:
• Programmable timeout interval
• Runs from the selected PCA clock source
• Automatically enabled after any system reset
3.6 Communications and Other Digital Peripherals
Universal Asynchronous Receiver/Transmitter (UART0)
UART0 is an asynchronous, full duplex serial port offering modes 1 and 3 of the standard 8051 UART. Enhanced baud rate support
allows a wide range of clock sources to generate standard baud rates. Received data buffering allows UART0 to start reception of a
second incoming data byte before software has finished reading the previous data byte.
The UART module provides the following features:
• Asynchronous transmissions and receptions
• Baud rates up to SYSCLK/2 (transmit) or SYSCLK/8 (receive)
• 8- or 9-bit data
• Automatic start and stop generation
Serial Peripheral Interface (SPI0 and SPI1)
The serial peripheral interface (SPI) module provides access to a flexible, full-duplex synchronous serial bus. The SPI can operate as a
master or slave device in both 3-wire or 4-wire modes, and supports multiple masters and slaves on a single SPI bus. The slave-select
(NSS) signal can be configured as an input to select the SPI in slave mode, or to disable master mode operation in a multi-master
environment, avoiding contention on the SPI bus when more than one master attempts simultaneous data transfers. NSS can also be
configured as a firmware-controlled chip-select output in master mode, or disabled to reduce the number of pins required. Additional
general purpose port I/O pins can be used to select multiple slave devices in master mode.
The SPI module includes the following features:
• Supports 3- or 4-wire operation in master or slave modes.
• Supports external clock frequencies up to SYSCLK / 2 in master mode and SYSCLK / 10 in slave mode.
• Support for four clock phase and polarity options.
• 8-bit dedicated clock clock rate generator.
• Support for multiple masters on the same data lines.
System Management Bus / I2C (SMB0)
The SMBus I/O interface is a two-wire, bi-directional serial bus. The SMBus is compliant with the System Management Bus Specification, version 1.1, and compatible with the I2C serial bus.
The SMBus module includes the following features:
• Standard (up to 100 kbps) and Fast (400 kbps) transfer speeds.
• Support for master, slave, and multi-master modes.
• Hardware synchronization and arbitration for multi-master mode.
• Clock low extending (clock stretching) to interface with faster masters.
• Hardware support for 7-bit slave and general call address recognition.
• Firmware support for 10-bit slave address decoding.
• Ability to inhibit all slave states.
• Programmable data setup/hold times.
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EFM8SB2 Data Sheet
System Overview
External Memory Interface (EMIF0)
The External Memory Interface (EMIF) enables access of off-chip memories and memory-mapped devices connected to the GPIO
ports. The external memory space may be accessed using the external move instruction (MOVX) with the target address specified in
either 8-bit or 16-bit formats.
• Supports multiplexed memory access.
• Four external memory modes:
• Internal only.
• Split mode without bank select.
• Split mode with bank select.
• External only
• Configurable ALE (address latch enable) timing.
• Configurable address setup and hold times.
• Configurable write and read pulse widths.
16/32-bit CRC (CRC0)
The cyclic redundancy check (CRC) module performs a CRC using a 16-bit or 32-bit polynomial. CRC0 accepts a stream of 8-bit data
and posts the result to an internal register. In addition to using the CRC block for data manipulation, hardware can automatically CRC
the flash contents of the device.
The CRC module is designed to provide hardware calculations for flash memory verification and communications protocols. The CRC
module includes the following features:
• Support for CCITT-16 polynomial (0x1021).
• Support for CRC-32 polynomial (0x04C11DB7).
• Byte-level bit reversal.
• Automatic CRC of flash contents on one or more 1024-byte blocks.
• Initial seed selection of 0x0000/0x00000000 or 0xFFFF/0xFFFFFFFF.
3.7 Analog
Programmable Current Reference (IREF0)
The programmable current reference (IREF0) module enables current source or sink with two output current settings: Low Power Mode
and High Current Mode. The maximum current output in Low Power Mode is 63 µA (1 µA steps) and the maximum current output in
High Current Mode is 504 µA (8 µA steps).
The IREF module includes the following features:
• Capable of sourcing or sinking current in programmable steps.
• Two operational modes: Low Power Mode and High Current Mode.
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EFM8SB2 Data Sheet
System Overview
10-Bit Analog-to-Digital Converter (ADC0)
The ADC is a successive-approximation-register (SAR) ADC with 10- and 8-bit modes, integrated track-and hold and a programmable
window detector. The ADC is fully configurable under software control via several registers. The ADC may be configured to measure
different signals using the analog multiplexer. The voltage reference for the ADC is selectable between internal and external reference
sources.
•
•
•
•
•
•
•
•
•
•
•
Up to 22 external inputs.
Single-ended 10-bit mode.
Supports an output update rate of 300 ksps samples per second.
Operation in low power modes at lower conversion speeds.
Asynchronous hardware conversion trigger, selectable between software, external I/O and internal timer sources.
Output data window comparator allows automatic range checking.
Support for burst mode, which produces one set of accumulated data per conversion-start trigger with programmable power-on settling and tracking time.
Conversion complete and window compare interrupts supported.
Flexible output data formatting.
Includes an internal 1.65 V fast-settling reference and support for external reference.
Integrated temperature sensor.
Low Current Comparators (CMP0, CMP1)
Analog comparators are used to compare the voltage of two analog inputs, with a digital output indicating which input voltage is higher.
External input connections to device I/O pins and internal connections are available through separate multiplexers on the positive and
negative inputs. Hysteresis, response time, and current consumption may be programmed to suit the specific needs of the application.
The comparator module includes the following features:
• Up to 12 external positive inputs.
• Up to 11 external negative inputs.
• Additional input options:
• Capacitive Sense Comparator output.
• VDD.
• VDD divided by 2.
• Internal connection to LDO output.
• Direct connection to GND.
• Synchronous and asynchronous outputs can be routed to pins via crossbar.
• Programmable hysteresis between 0 and +/-20 mV.
• Programmable response time.
• Interrupts generated on rising, falling, or both edges.
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EFM8SB2 Data Sheet
System Overview
3.8 Reset Sources
Reset circuitry allows the controller to be easily placed in a predefined default condition. On entry to this reset state, the following occur:
• The core halts program execution.
• Module registers are initialized to their defined reset values unless the bits reset only with a power-on reset.
• External port pins are forced to a known state.
• Interrupts and timers are disabled.
All registers are reset to the predefined values noted in the register descriptions unless the bits only reset with a power-on reset. The
contents of RAM are unaffected during a reset; any previously stored data is preserved as long as power is not lost. The Port I/O latches are reset to 1 in open-drain mode. Weak pullups are enabled during and after the reset. For Supply Monitor and power-on resets,
the RSTb pin is driven low until the device exits the reset state. On exit from the reset state, the program counter (PC) is reset, and the
system clock defaults to an internal oscillator. The Watchdog Timer is enabled, and program execution begins at location 0x0000.
Reset sources on the device include the following:
• Power-on reset
• External reset pin
• Comparator reset
• Software-triggered reset
• Supply monitor reset (monitors VDD supply)
• Watchdog timer reset
• Missing clock detector reset
• Flash error reset
• RTC0 alarm or oscillator failure
3.9 Debugging
The EFM8SB2 devices include an on-chip Silicon Labs 2-Wire (C2) debug interface to allow flash programming and in-system debugging with the production part installed in the end application. The C2 interface uses a clock signal (C2CK) and a bi-directional C2 data
signal (C2D) to transfer information between the device and a host system. See the C2 Interface Specification for details on the C2
protocol.
3.10 Bootloader
All devices come pre-programmed with a UART bootloader. This bootloader resides in flash and can be erased if it is not needed.
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EFM8SB2 Data Sheet
Electrical Specifications
4. Electrical Specifications
4.1 Electrical Characteristics
All electrical parameters in all tables are specified under the conditions listed in Table 4.1 Recommended Operating Conditions on page
11, unless stated otherwise.
Table 4.1. Recommended Operating Conditions
Parameter
Symbol
Operating Supply Voltage on VDD
VDD
Minimum RAM Data Retention
Voltage on VDD1
VRAM
System Clock Frequency
fSYSCLK
Operating Ambient Temperature
TA
Test Condition
Min
Typ
Max
Unit
1.8
2.4
3.6
V
Not in Sleep Mode
—
1.4
—
V
Sleep Mode
—
0.3
0.5
V
0
—
25
MHz
–40
—
85
°C
Min
Typ
Max
Units
Note:
1. All voltages with respect to GND.
Table 4.2. Power Consumption
Parameter
Symbol
Conditions
IDD
VDD = 1.8–3.6 V, fSYSCLK
= 24.5 MHz
—
4.1
5.0
mA
VDD = 1.8–3.6 V, fSYSCLK = 20
MHz
—
3.5
—
mA
VDD = 1.8–3.6 V, fSYSCLK = 32.768
kHz
—
90
—
µA
VDD = 1.8–3.6 V, T = 25 °C,
fSYSCLK < 14 MHz
—
226
—
µA/MHz
VDD = 1.8–3.6 V, T = 25 °C,
fSYSCLK > 14 MHz
—
120
—
µA/MHz
VDD = 1.8–3.6 V, fSYSCLK = 24.5
MHz
—
2.5
3.0
mA
VDD = 1.8–3.6 V, fSYSCLK = 20
MHz
—
1.8
—
mA
VDD = 1.8–3.6 V, fSYSCLK = 32.768
kHz
—
84
—
µA
Idle Mode Supply Current Frequen- IDDFREQ
cy Sensitivity1 ,6
VDD = 1.8–3.6 V, T = 25 °C
—
95
—
µA/MHz
Suspend Mode Supply Current
IDD
VDD = 1.8–3.6 V
—
77
—
µA
Sleep Mode Supply Current with
RTC running from 32.768 kHz
crystal
IDD
1.8 V, T = 25 °C
—
0.60
—
µA
3.6 V, T = 25 °C
—
0.85
—
µA
1.8 V, T = 85 °C
—
1.30
—
µA
3.6 V, T = 85 °C
—
1.90
—
µA
Digital Supply Current
Normal Mode supply current - Full
speed with code executing from
flash 3 , 4 , 5
Normal Mode supply current frequency sensitivity1, 3, 5
Idle Mode supply current - Core
halted with peripherals running4 , 6
IDDFREQ
IDD
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EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Sleep Mode Supply Current (RTC
off)
IDD
1.8 V, T = 25 °C
—
0.05
—
µA
3.6 V, T = 25 °C
—
0.12
—
µA
1.8 V, T = 85 °C
—
0.75
—
µA
3.6 V, T = 85 °C
—
1.20
—
µA
—
7
—
µA
VDD Monitor Supply Current
IVMON
Oscillator Supply Current
IHFOSC0
25 °C
—
300
—
µA
ADC0 Always-on Power Supply
Current7
IADC
300 ksps
—
800
—
µA
—
680
—
µA
CPMD = 11
—
0.4
—
µA
CPMD = 10
—
2.6
—
µA
CPMD = 01
—
8.8
—
µA
CPMD = 00
—
23
—
µA
VDD = 3.0 V
Tracking
VDD = 3.0 V
Comparator 0 (CMP0) Supply Cur- ICMP
rent
Internal Fast-settling 1.65V ADC0
Reference, Always-on8
IVREFFS
—
200
—
µA
On-chip Precision Reference
IVREFP
—
15
—
µA
Temp sensor Supply Current
ITSENSE
—
35
—
µA
Programmable Current Reference
(IREF0) Supply Current9
IIREF
Current Source, Either Power
Mode, Any Output Code
—
10
—
µA
Low Power Mode, Current Sink
—
1
—
µA
—
11
—
µA
—
12
—
µA
—
81
—
µA
IREF0DAT = 000001
Low Power Mode, Current Sink
IREF0DAT = 111111
High Current Mode, Current Sink
IREF0DAT = 000001
High Current Mode, Current Sink
IREF0DAT = 111111
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EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Conditions
Min
Typ
Max
Units
Note:
1. Based on device characterization data; Not production tested.
2. SYSCLK must be at least 32 kHz to enable debugging.
3. Digital Supply Current depends upon the particular code being executed. The values in this table are obtained with the CPU executing an “sjmp $” loop, which is the compiled form of a while(1) loop in C. One iteration requires 3 CPU clock cycles, and the
flash memory is read on each cycle. The supply current will vary slightly based on the physical location of the sjmp instruction and
the number of flash address lines that toggle as a result. In the worst case, current can increase by up to 30% if the sjmp loop
straddles a 128-byte flash address boundary (e.g., 0x007F to 0x0080). Real-world code with larger loops and longer linear sequences will have few transitions across the 128-byte address boundaries.
4. Includes supply current from regulator and oscillator source (24.5 MHz high-frequency oscillator, 20 MHz low-power oscillator, or
32.768 kHz RTC oscillator).
5. IDD can be estimated for frequencies < 10 MHz by simply multiplying the frequency of interest by the frequency sensitivity number for that range, then adding an offset of 90 µA. When using these numbers to estimate IDD for > 10 MHz, the estimate should
be the current at 25 MHz minus the difference in current indicated by the frequency sensitivity number. For example: VDD = 3.0 V;
F = 20 MHz, IDD = 4.1 mA – (25 MHz – 20 MHz) x 0.120 mA/MHz = 3.5 mA assuming the same oscillator setting.
6. Idle IDD can be estimated by taking the current at 25 MHz minus the difference in current indicated by the frequency sensitivity
number. For example: VDD = 3.0 V; F = 5 MHz, Idle IDD = 2.5 mA – (25 MHz – 5 MHz) x 0.095 mA/MHz = 0.6 mA.
7. ADC0 always-on power excludes internal reference supply current.
8. The internal reference is enabled as-needed when operating the ADC in burst mode to save power.
9. IREF0 supply current only. Does not include current sourced or sunk from IREF0 output pin.
Table 4.3. Reset and Supply Monitor
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
VDD Supply Monitor Threshold
VVDDM
Reset Trigger
1.7
1.75
1.8
V
VWARN
Early Warning
1.8
1.85
1.9
V
—
300
—
ns
Initial Power-On (Rising Voltage on
VDD)
—
0.75
—
V
Falling Voltage on VDD
0.7
0.8
0.9
V
Brownout Recovery (Rising Voltage on VDD)
—
0.95
—
V
VDD Supply Monitor Turn-On Time tMON
Power-On Reset (POR) Monitor
Threshold
VPOR
VDD Ramp Time
tRMP
Time to VDD ≥ 1.8 V
—
—
3
ms
Reset Delay
tRST
Time between release of reset
source and code execution
—
10
—
µs
RST Low Time to Generate Reset
tRSTL
15
—
—
µs
Missing Clock Detector Response
Time (final rising edge to reset)
tMCD
100
650
1000
µs
Missing Clock Detector Trigger
Frequency
FMCD
—
7
10
kHz
Min
Typ
Max
Units
FSYSCLK > 1 MHz
Table 4.4. Flash Memory
Parameter
Symbol
Test Condition
Write Time1
tWRITE
One Byte
57
64
71
µs
Erase Time1
tERASE
One Page
28
32
36
ms
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EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Endurance (Write/Erase Cycles)
NWE
Test Condition
Min
Typ
Max
Units
1k
30 k
—
Cycles
Note:
1. Does not include sequencing time before and after the write/erase operation, which may be multiple SYSCLK cycles.
2. Data Retention Information is published in the Quarterly Quality and Reliability Report.
Table 4.5. Power Management Timing
Parameter
Symbol
Test Condition
Idle Mode Wake-up Time
tIDLEWK
Suspend Mode Wake-up Time
tSUS-
CLKDIV = 0x00
PENDWK
Precision Osc.
CLKDIV = 0x00
Min
Typ
Max
Units
2
—
3
SYSCLKs
—
400
—
ns
—
1.3
—
µs
—
2
—
µs
Min
Typ
Max
Unit
Low Power Osc.
Sleep Mode Wake-up Time
tSLEEPWK
Table 4.6. Internal Oscillators
Parameter
Symbol
Test Condition
High Frequency Oscillator 0 (24.5 MHz)
Oscillator Frequency
fHFOSC0
Full Temperature and Supply
Range
24
24.5
25
MHz
fLPOSC
Full Temperature and Supply
Range
18
20
22
MHz
fLFOSC
Bias Off
—
12 ± 5
—
kHz
Bias On
—
25 ± 10
—
kHz
Min
Typ
Max
Unit
0.02
-
25
MHz
Min
Typ
Max
Unit
Low Power Oscillator (20 MHz)
Oscillator Frequency
RTC in Self-Oscillate Mode
Oscillator Frequency
Table 4.7. Crystal Oscillator
Parameter
Symbol
Crystal Frequency
fXTAL
Test Condition
Table 4.8. External Clock Input
Parameter
Symbol
Test Condition
External Input CMOS Clock
fCMOS
0
—
25
MHz
External Input CMOS Clock High
Time
tCMOSH
18
—
—
ns
External Input CMOS Clock Low
Time
tCMOSL
18
—
—
ns
Frequency (at EXTCLK pin)
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EFM8SB2 Data Sheet
Electrical Specifications
Table 4.9. ADC
Parameter
Symbol
Test Condition
Min
Typ
Max
Resolution
Nbits
Throughput Rate
fS
—
—
300
ksps
Tracking Time
tTRK
1.5
—
—
µs
Power-On Time
tPWR
1.5
—
—
µs
SAR Clock Frequency
fSAR
—
—
8.33
MHz
Conversion Time
TCNV
13
—
—
Clocks
Sample/Hold Capacitor
CSAR
Gain = 1
—
30
—
pF
Gain = 0.5
—
28
—
pF
10
High Speed Mode,
Unit
Bits
Input Pin Capacitance
CIN
—
20
—
pF
Input Mux Impedance
RMUX
—
5
—
kΩ
Voltage Reference Range
VREF
1
—
VDD
V
Input Voltage Range1
VIN
Gain = 1
0
—
VREF
V
Gain = 0.5
0
—
2 x VREF
V
PSRRADC Internal High Speed VREF
—
67
—
dB
External VREF
—
74
—
dB
Power Supply Rejection Ratio
DC Performance
Integral Nonlinearity
INL
—
±0.5
±1
LSB
Differential Nonlinearity (Guaranteed Monotonic)
DNL
—
±0.5
±1
LSB
Offset Error
EOFF
–2
0
2
LSB
Offset Temperature Coefficient
TCOFF
—
0.004
—
LSB/°C
Slope Error
EM
—
±0.06
±0.24
%
VREF = 1.65 V
Dynamic Performance 10 kHz Sine Wave Input 1dB below full scale, Max throughput
Signal-to-Noise
SNR
54
58
—
dB
Signal-to-Noise Plus Distortion
SNDR
54
58
—
dB
Total Harmonic Distortion (Up to
5th Harmonic)
THD
—
-73
—
dB
Spurious-Free Dynamic Range
SFDR
—
75
—
dB
Min
Typ
Max
Unit
1.60
1.65
1.70
V
Note:
1. Absolute input pin voltage is limited by the VDD supply.
Table 4.10. Voltage References
Parameter
Symbol
Test Condition
Internal Fast Settling Reference
Output Voltage
VREFFS
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EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Temperature Coefficient
Test Condition
Min
Typ
Max
Unit
TCREFFS
—
50
—
ppm/°C
Turn-on Time
tVREFFS
—
—
1.5
µs
Power Supply Rejection
PSRRREF
—
400
—
ppm/V
1.645
1.68
1.715
V
4.7 µF tantalum + 0.1 µF ceramic
bypass on VREF pin
—
15
—
ms
0.1 µF ceramic bypass on VREF
pin
—
300
—
µs
No bypass on VREF pin
—
25
—
µs
Load = 0 to 200 µA to GND
—
400
—
µV / µA
FS
On-chip Precision Reference
Output Voltage
VREFP
Turn-on Time, settling to 0.5 LSB
tVREFP
Load Regulation
LRVREFP
Short-circuit current
ISCVREFP
—
3.5
—
mA
Power Supply Rejection
PSRRVRE
—
140
—
ppm/V
1
—
VDD
V
—
5.25
—
µA
Min
Typ
Max
Unit
FP
External Reference
Input Voltage
VEXTREF
Input Current
IEXTREF
Sample Rate = 300 ksps; VREF =
3.0 V
Table 4.11. Temperature Sensor
Parameter
Symbol
Test Condition
Offset
VOFF
TA = 0 °C
—
940
—
mV
Offset Error1
EOFF
TA = 0 °C
—
18
—
mV
Slope
M
—
3.40
—
mV/°C
Slope Error1
EM
—
40
—
µV/°C
—
±1
—
°C
—
1.8
—
µs
Min
Typ
Max
Unit
Linearity
Turn-on Time
tPWR
Note:
1. Represents one standard deviation from the mean.
Table 4.12. Comparators
Parameter
Symbol
Test Condition
Response Time, CPMD = 00
(Highest Speed)
tRESP0
+100 mV Differential
—
130
—
ns
–100 mV Differential
—
200
—
ns
+100 mV Differential
—
1.75
—
µs
–100 mV Differential
—
6.2
—
µs
Response Time, CPMD = 11 (Low- tRESP3
est Power)
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EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Positive Hysterisis
HYSCP+
Mode 0 (CPMD = 00)
Negative Hysterisis
HYSCP-
Mode 0 (CPMD = 00)
Positive Hysterisis
HYSCP+
Mode 1 (CPMD = 01)
Negative Hysterisis
HYSCP-
Mode 1 (CPMD = 01)
Positive Hysterisis
HYSCP+
Mode 2 (CPMD = 10)
Negative Hysterisis
HYSCP-
Mode 2 (CPMD = 10)
Positive Hysteresis
HYSCP+
Mode 3 (CPMD = 11)
Negative Hysteresis
HYSCP-
Mode 3 (CPMD = 11)
Min
Typ
Max
Unit
CPHYP = 00
—
0.4
—
mV
CPHYP = 01
—
8
—
mV
CPHYP = 10
—
16
—
mV
CPHYP = 11
—
32
—
mV
CPHYN = 00
—
-0.4
—
mV
CPHYN = 01
—
–8
—
mV
CPHYN = 10
—
–16
—
mV
CPHYN = 11
—
–32
—
mV
CPHYP = 00
—
0.5
—
mV
CPHYP = 01
—
6
—
mV
CPHYP = 10
—
12
—
mV
CPHYP = 11
—
24
—
mV
CPHYN = 00
—
-0.5
—
mV
CPHYN = 01
—
–6
—
mV
CPHYN = 10
—
–12
—
mV
CPHYN = 11
—
–24
—
mV
CPHYP = 00
—
0.7
—
mV
CPHYP = 01
—
4.5
—
mV
CPHYP = 10
—
9
—
mV
CPHYP = 11
—
18
—
mV
CPHYN = 00
—
-0.6
—
mV
CPHYN = 01
—
–4.5
—
mV
CPHYN = 10
—
–9
—
mV
CPHYN = 11
—
–18
—
mV
CPHYP = 00
—
1.5
—
mV
CPHYP = 01
—
4
—
mV
CPHYP = 10
—
8
—
mV
CPHYP = 11
—
16
—
mV
CPHYN = 00
—
-1.5
—
mV
CPHYN = 01
—
–4
—
mV
CPHYN = 10
—
–8
—
mV
CPHYN = 11
—
–16
—
mV
Input Range (CP+ or CP–)
VIN
-0.25
—
VDD+0.25
V
Input Pin Capacitance
CCP
—
12
—
pF
Common-Mode Rejection Ratio
CMRRCP
—
70
—
dB
Power Supply Rejection Ratio
PSRRCP
—
72
—
dB
Input Offset Voltage
VOFF
-10
0
10
mV
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EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Input Offset Tempco
TCOFF
Test Condition
Min
Typ
Max
Unit
—
3.5
—
µV/°C
Typ
Max
Units
Table 4.13. Programmable Current Reference (IREF0)
Parameter
Symbol
Conditions
Min
Static Performance
Resolution
Nbits
Output Compliance Range
VIOUT
6
bits
Low Power Mode, Source
0
—
VDD – 0.4
V
High Current Mode, Source
0
—
VDD – 0.8
V
Low Power Mode, Sink
0.3
—
VDD
V
High Current Mode, Sink
0.8
—
VDD
V
Integral Nonlinearity
INL
—
<±0.2
±1.0
LSB
Differential Nonlinearity
DNL
—
<±0.2
±1.0
LSB
Offset Error
EOFF
—
<±0.1
±0.5
LSB
Full Scale Error
EFS
Low Power Mode, Source
—
—
±5
%
High Current Mode, Source
—
—
±6
%
Low Power Mode, Sink
—
—
±8
%
High Current Mode, Sink
—
—
±8
%
Low Power Mode Sourcing 20 µA
—
<±1
±3
%
Absolute Current Error
EABS
Dynamic Performance
Output Settling Time to 1/2 LSB
tSETTLE
—
300
—
ns
Startup Time
tPWR
—
1
—
µs
Min
Typ
Max
Unit
Note:
1. The PCA block may be used to improve IREF0 resolution by PWMing the two LSBs.
Table 4.14. Port I/O
Parameter
Symbol
Test Condition
Output High Voltage (High Drive)
VOH
IOH = –3 mA
VDD – 0.7
—
—
V
Output Low Voltage (High Drive)
VOL
IOL = 8.5 mA
—
—
0.6
V
Output High Voltage (Low Drive)
VOH
IOH = –1 mA
VDD – 0.7
—
—
V
Output Low Voltage (Low Drive)
VOL
IOL = 1.4 mA
—
—
0.6
V
Input High Voltage
VIH
VDD = 2.0 to 3.6 V
VDD – 0.6
—
—
V
VDD = 1.8 to 2.0 V
0.7 x VDD
—
—
V
VDD = 2.0 to 3.6 V
—
—
0.6
V
VDD = 1.8 to 2.0 V
—
—
0.3 x VDD
V
Input Low Voltage
VIL
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EFM8SB2 Data Sheet
Electrical Specifications
Parameter
Symbol
Test Condition
Weak Pull-Up Current
IPU
VDD = 1.8 V
Min
Typ
Max
Unit
—
–4
—
µA
–35
–20
—
µA
–1
—
1
µA
Min
Typ
Max
Unit
VIN = 0 V
VDD = 3.6 V
VIN = 0 V
Input Leakage
ILK
Weak pullup disabled or pin in analog mode
4.2 Thermal Conditions
Table 4.15. Thermal Conditions
Parameter
Symbol
Test Condition
Thermal Resistance1
θJA
QFN-24 Packages
—
35
—
°C/W
QFN-32 Packages
—
28
—
°C/W
QFP-32 Packages
—
80
—
°C/W
Note:
1. Thermal resistance assumes a multi-layer PCB with any exposed pad soldered to a PCB pad.
4.3 Absolute Maximum Ratings
Stresses above those listed in Table 4.16 Absolute Maximum Ratings on page 19 may cause permanent damage to the device. This
is a stress rating only and functional operation of the devices at those or any other conditions above those indicated in the operation
listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. For
more information on the available quality and reliability data, see the Quality and Reliability Monitor Report at http://www.silabs.com/
support/quality/pages/default.aspx.
Table 4.16. Absolute Maximum Ratings
Parameter
Symbol
Ambient Temperature Under Bias
Test Condition
Min
Max
Unit
TBIAS
–55
125
°C
Storage Temperature
TSTG
–65
150
°C
Voltage on VDD
VDD
GND–0.3
4.0
V
Voltage on I/O pins or RSTb
VIN
VDD > 2.2 V
GND–0.3
5.8
V
VDD <= 2.2 V
GND–0.3
VDD + 3.6
V
Total Current Sunk into Supply Pin
IVDD
—
400
mA
Total Current Sourced out of Ground
Pin
IGND
400
—
mA
Current Sourced or Sunk by Any I/O
Pin or RSTb
IIO
-100
100
mA
Maximum Total Current through all
Port Pins
IIOTOT
—
200
mA
Operating Junction Temperature
TJ
–40
105
°C
Exposure to maximum rating conditions for extended periods may affect device reliability.
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EFM8SB2 Data Sheet
Electrical Specifications
4.4 Typical Performance Curves
Figure 4.1. Typical Operating Supply Current (full supply voltage range)
Figure 4.2. Typical VOH Curves
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EFM8SB2 Data Sheet
Electrical Specifications
Figure 4.3. Typical VOL Curves
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EFM8SB2 Data Sheet
Typical Connection Diagrams
5. Typical Connection Diagrams
5.1 Power
Figure 5.1 Power Connection Diagram on page 22 shows a typical connection diagram for the power pins of the EFM8SB2 devices.
1.8-3.6 V (in)
1 µF and 0.1 µF bypass
capacitors required for
the power pins placed
as close to the pins as
possible.
VDD
EFM8SB2
Device
GND
Figure 5.1. Power Connection Diagram
5.2 Other Connections
Other components or connections may be required to meet the system-level requirements. Application Note AN203: "8-bit MCU Printed
Circuit Board Design Notes" contains detailed information on these connections. Application Notes can be accessed on the Silicon
Labs website (www.silabs.com/8bit-appnotes).
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EFM8SB2 Data Sheet
Pin Definitions
6. Pin Definitions
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
32
31
30
29
28
27
26
25
6.1 EFM8SB2x-QFN32 Pin Definitions
N/C
1
24
P1.0
GND
2
23
P1.1
VDD
3
22
P1.2
N/C
4
21
P1.3
N/C
5
20
P1.4
RSTb / C2CK
6
19
P1.5
P2.7 / C2D
7
18
P1.6
17
P1.7
32 pin QFN
(Top View)
GND
15
16
P2.0
14
P2.2
P2.1
13
P2.3
11
P2.5
12
10
XTAL3
P2.4
9
8
XTAL4
P2.6
Figure 6.1. EFM8SB2x-QFN32 Pinout
Table 6.1. Pin Definitions for EFM8SB2x-QFN32
Pin
Pin Name
Description
1
N/C
No Connection
2
GND
Ground
3
VDD
Supply Power Input
4
N/C
No Connection
Number
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Additional Digital
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Analog Functions
Rev. 1.1 | 23
EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
5
N/C
No Connection
6
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.7 /
Multifunction I/O /
C2D
C2 Debug Data
P2.6
Multifunction I/O
Crossbar Capability
Additional Digital
Functions
Analog Functions
Yes
EMIF_WRb
ADC0.22
Number
7
8
CMP0P.11
CMP1P.11
9
XTAL4
RTC Crystal
XTAL4
10
XTAL3
RTC Crystal
XTAL3
11
P2.5
Multifunction I/O
Yes
EMIF_RDb
ADC0.21
CMP0N.10
CMP1N.10
12
P2.4
Multifunction I/O
Yes
EMIF_ALE
ADC0.20
CMP0P.10
CMP1P.10
13
P2.3
Multifunction I/O
Yes
EMIF_A11
ADC0.19
CMP0N.9
CMP1N.9
14
P2.2
Multifunction I/O
Yes
EMIF_A10
ADC0.18
CMP0P.9
CMP1P.9
15
P2.1
Multifunction I/O
Yes
EMIF_A9
ADC0.17
CMP0N.8
CMP1N.8
16
P2.0
Multifunction I/O
Yes
EMIF_A8
ADC0.16
CMP0P.8
CMP1P.8
17
P1.7
Multifunction I/O
Yes
P1MAT.7
ADC0.15
EMIF_AD7
CMP0N.7
CMP1N.7
18
P1.6
Multifunction I/O
Yes
P1MAT.6
ADC0.14
EMIF_AD6
CMP0P.7
CMP1P.7
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EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P1.5
Multifunction I/O
Yes
P1MAT.5
ADC0.13
EMIF_AD5
CMP0N.6
Number
19
CMP1N.6
20
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
EMIF_AD4
CMP0P.6
CMP1P.6
21
22
23
24
25
P1.3
P1.2
P1.1
P1.0
P0.7
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
Yes
Yes
P1MAT.3
ADC0.11
SPI1_NSS
CMP0N.5
EMIF_AD3
CMP1N.5
P1MAT.2
ADC0.10
SPI1_MOSI
CMP0P.5
EMIF_AD2
CMP1P.5
P1MAT.1
ADC0.9
SPI1_MISO
CMP0N.4
EMIF_AD1
CMP1N.4
P1MAT.0
ADC0.8
SPI1_SCK
CMP0P.4
EMIF_AD0
CMP1P.4
P0MAT.7
ADC0.7
INT0.7
IREF0
INT1.7
CMP0N.3
CMP1N.3
26
P0.6
Multifunction I/O
Yes
P0MAT.6
ADC0.6
CNVSTR
CMP0P.3
INT0.6
CMP1P.3
INT1.6
27
28
29
P0.5
P0.4
P0.3
Multifunction I/O
Multifunction I/O
Multifunction I/O
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Yes
Yes
Yes
P0MAT.5
ADC0.5
INT0.5
CMP0N.2
INT1.5
CMP1N.2
P0MAT.4
ADC0.4
INT0.4
CMP0P.2
INT1.4
CMP1P.2
P0MAT.3
ADC0.3
EXTCLK
XTAL2
INT0.3
CMP0N.1
INT1.3
CMP1N.1
Rev. 1.1 | 25
EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.2
Multifunction I/O
Yes
P0MAT.2
ADC0.2
INT0.2
CMP0P.1
INT1.2
CMP1P.1
Number
30
XTAL1
31
P0.1
Multifunction I/O
Yes
P0MAT.1
ADC0.1
INT0.1
AGND
INT1.1
CMP0N.0
CMP1N.0
32
P0.0
Multifunction I/O
Yes
P0MAT.0
ADC0.0
INT0.0
CMP0P.0
INT1.0
CMP1P.0
VREF
Center
GND
Ground
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Rev. 1.1 | 26
EFM8SB2 Data Sheet
Pin Definitions
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
24
23
22
21
20
19
6.2 EFM8SB2x-QFN24 Pin Definitions
N/C
1
18
P0.6
GND
2
17
P0.7
VDD
3
16
P1.0
N/C
4
15
P1.1
N/C
5
14
P1.2
13
P1.3
24 pin QFN
(Top View)
GND
11
P1.5
12
10
P1.6
P1.4
9
XTAL3
XTAL4
P2.7 / C2D
8
6
7
RSTb / C2CK
Figure 6.2. EFM8SB2x-QFN24 Pinout
Table 6.2. Pin Definitions for EFM8SB2x-QFN24
Pin
Pin Name
Description
1
N/C
No Connection
2
GND
Ground
3
VDD
Supply Power Input
4
N/C
No Connection
5
N/C
No Connection
Number
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Crossbar Capability
Additional Digital
Functions
Analog Functions
Rev. 1.1 | 27
EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.7 /
Multifunction I/O /
C2D
C2 Debug Data
8
XTAL4
RTC Crystal
XTAL4
9
XTAL3
RTC Crystal
XTAL3
10
P1.6
Multifunction I/O
Number
6
7
Additional Digital
Functions
Yes
Analog Functions
ADC0.14
CMP0P.7
CMP1P.7
11
P1.5
Multifunction I/O
Yes
P1MAT.5
ADC0.13
CMP0N.6
CMP1N.6
12
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
CMP0P.6
CMP1P.6
13
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
SPI1_NSS
CMP0N.5
CMP1N.5
14
P1.2
Multifunction I/O
Yes
P1MAT.2
ADC0.10
SPI1_MOSI
CMP0P.5
CMP1P.5
15
P1.1
Multifunction I/O
Yes
P1MAT.1
ADC0.9
SPI1_MISO
CMP0N.4
CMP1N.4
16
P1.0
Multifunction I/O
Yes
P1MAT.0
ADC0.8
SPI1_SCK
CMP0P.4
CMP1P.4
17
P0.7
Multifunction I/O
Yes
P0MAT.7
ADC0.7
INT0.7
IREF0
INT1.7
CMP0N.3
CMP1N.3
18
P0.6
Multifunction I/O
Yes
P0MAT.6
ADC0.6
CNVSTR
CMP0P.3
INT0.6
CMP1P.3
INT1.6
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EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.5
Multifunction I/O
Yes
P0MAT.5
ADC0.5
INT0.5
CMP0N.2
INT1.5
CMP1N.2
P0MAT.4
ADC0.4
INT0.4
CMP0P.2
INT1.4
CMP1P.2
P0MAT.3
ADC0.3
EXTCLK
XTAL2
INT0.3
CMP0N.1
INT1.3
CMP1N.1
P0MAT.2
ADC0.2
INT0.2
CMP0P.1
INT1.2
CMP1P.1
Number
19
20
21
22
P0.4
P0.3
P0.2
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
XTAL1
23
P0.1
Multifunction I/O
Yes
P0MAT.1
ADC0.1
INT0.1
AGND
INT1.1
CMP0N.0
CMP1N.0
24
P0.0
Multifunction I/O
Yes
P0MAT.0
ADC0.0
INT0.0
CMP0P.0
INT1.0
CMP1P.0
VREF
Center
GND
Ground
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EFM8SB2 Data Sheet
Pin Definitions
P0.4
P0.5
P0.6
P0.7
28
27
25
P0.3
29
26
P0.2
30
31
P0.0
P0.1
32
6.3 EFM8SB2x-QFP32 Pin Definitions
N/C
GND
1
24
2
23
P1.0
P1.1
VDD
3
22
P1.2
N/C
4
21
P1.3
N/C
5
20
P1.4
RSTb / C2CK
6
19
P1.5
P2.7 / C2D
7
18
P1.6
P2.6
8
17
P1.7
13
14
P2.3
P2.2
P2.1
P2.0
16
12
P2.4
15
11
P2.5
10
XTAL4
XTAL3
9
32 Pin QFP
Figure 6.3. EFM8SB2x-QFP32 Pinout
Table 6.3. Pin Definitions for EFM8SB2x-QFP32
Pin
Pin Name
Description
1
N/C
No Connection
2
GND
Ground
3
VDD
Supply Power Input
4
N/C
No Connection
5
N/C
No Connection
6
RSTb /
Active-low Reset /
C2CK
C2 Debug Clock
P2.7 /
Multifunction I/O /
C2D
C2 Debug Data
Number
7
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Crossbar Capability
Additional Digital
Functions
Analog Functions
Rev. 1.1 | 30
EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P2.6
Multifunction I/O
Yes
EMIF_WRb
ADC0.22
Number
8
CMP0P.11
CMP1P.11
9
XTAL4
RTC Crystal
XTAL4
10
XTAL3
RTC Crystal
XTAL3
11
P2.5
Multifunction I/O
Yes
EMIF_RDb
ADC0.21
CMP0N.10
CMP1N.10
12
P2.4
Multifunction I/O
Yes
EMIF_ALE
ADC0.20
CMP0P.10
CMP1P.10
13
P2.3
Multifunction I/O
Yes
EMIF_A11
ADC0.19
CMP0N.9
CMP1N.9
14
P2.2
Multifunction I/O
Yes
EMIF_A10
ADC0.18
CMP0P.9
CMP1P.9
15
P2.1
Multifunction I/O
Yes
EMIF_A9
ADC0.17
CMP0N.8
CMP1N.8
16
P2.0
Multifunction I/O
Yes
EMIF_A8
ADC0.16
CMP0P.8
CMP1P.8
17
P1.7
Multifunction I/O
Yes
P1MAT.7
ADC0.15
EMIF_AD7
CMP0N.7
CMP1N.7
18
P1.6
Multifunction I/O
Yes
P1MAT.6
ADC0.14
EMIF_AD6
CMP0P.7
CMP1P.7
19
P1.5
Multifunction I/O
Yes
P1MAT.5
ADC0.13
EMIF_AD5
CMP0N.6
CMP1N.6
20
P1.4
Multifunction I/O
Yes
P1MAT.4
ADC0.12
EMIF_AD4
CMP0P.6
CMP1P.6
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EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P1.3
Multifunction I/O
Yes
P1MAT.3
ADC0.11
SPI1_NSS
CMP0N.5
EMIF_AD3
CMP1N.5
P1MAT.2
ADC0.10
SPI1_MOSI
CMP0P.5
EMIF_AD2
CMP1P.5
P1MAT.1
ADC0.9
SPI1_MISO
CMP0N.4
EMIF_AD1
CMP1N.4
P1MAT.0
ADC0.8
SPI1_SCK
CMP0P.4
EMIF_AD0
CMP1P.4
P0MAT.7
ADC0.7
INT0.7
IREF0
INT1.7
CMP0N.3
Number
21
22
23
24
25
P1.2
P1.1
P1.0
P0.7
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
Yes
CMP1N.3
26
P0.6
Multifunction I/O
Yes
P0MAT.6
ADC0.6
CNVSTR
CMP0P.3
INT0.6
CMP1P.3
INT1.6
27
28
29
30
P0.5
P0.4
P0.3
P0.2
Multifunction I/O
Multifunction I/O
Multifunction I/O
Multifunction I/O
Yes
Yes
Yes
Yes
P0MAT.5
ADC0.5
INT0.5
CMP0N.2
INT1.5
CMP1N.2
P0MAT.4
ADC0.4
INT0.4
CMP0P.2
INT1.4
CMP1P.2
P0MAT.3
ADC0.3
EXTCLK
XTAL2
INT0.3
CMP0N.1
INT1.3
CMP1N.1
P0MAT.2
ADC0.2
INT0.2
CMP0P.1
INT1.2
CMP1P.1
XTAL1
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Rev. 1.1 | 32
EFM8SB2 Data Sheet
Pin Definitions
Pin
Pin Name
Description
Crossbar Capability
Additional Digital
Functions
Analog Functions
P0.1
Multifunction I/O
Yes
P0MAT.1
ADC0.1
INT0.1
AGND
INT1.1
CMP0N.0
Number
31
CMP1N.0
32
P0.0
Multifunction I/O
Yes
P0MAT.0
ADC0.0
INT0.0
CMP0P.0
INT1.0
CMP1P.0
VREF
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Rev. 1.1 | 33
EFM8SB2 Data Sheet
QFN32 Package Specifications
7. QFN32 Package Specifications
7.1 QFN32 Package Dimensions
Figure 7.1. QFN32 Package Drawing
Table 7.1. QFN32 Package Dimensions
Dimension
Min
Typ
Max
A
0.80
0.90
1.00
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
5.00 BSC
3.20
3.30
e
0.50 BSC
E
5.00 BSC
3.40
E2
3.20
3.30
3.40
L
0.30
0.40
0.50
L1
0.00
—
0.15
aaa
—
—
0.15
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Rev. 1.1 | 34
EFM8SB2 Data Sheet
QFN32 Package Specifications
Dimension
Min
Typ
Max
bbb
—
—
0.10
ddd
—
—
0.05
eee
—
—
0.08
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation VHHD except for custom features D2, E2, and L which
are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.1 | 35
EFM8SB2 Data Sheet
QFN32 Package Specifications
7.2 QFN32 PCB Land Pattern
Figure 7.2. QFN32 PCB Land Pattern Drawing
Table 7.2. QFN32 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
4.80
4.90
C2
4.80
4.90
E
0.50 BSC
X1
0.20
0.30
X2
3.20
3.40
Y1
0.75
0.85
Y2
3.20
3.40
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 3 x 3 array of 1.0 mm x 1.0 mm openings on a 1.2 mm pitch should be used for the center pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8SB2 Data Sheet
QFN32 Package Specifications
7.3 QFN32 Package Marking
EFM8
PPPPPPPP
TTTTTT
YYWW #
Figure 7.3. QFN32 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.1 | 37
EFM8SB2 Data Sheet
QFN24 Package Specifications
8. QFN24 Package Specifications
8.1 QFN24 Package Dimensions
Figure 8.1. QFN24 Package Drawing
Table 8.1. QFN24 Package Dimensions
Dimension
Min
Typ
Max
A
0.70
0.75
0.80
A1
0.00
0.02
0.05
b
0.18
0.25
0.30
D
D2
4.00 BSC
2.55
2.70
e
0.50 BSC
E
4.00 BSC
2.80
E2
2.55
2.70
2.80
L
0.30
0.40
0.50
L1
0.00
—
0.15
aaa
—
—
0.15
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Rev. 1.1 | 38
EFM8SB2 Data Sheet
QFN24 Package Specifications
Dimension
Min
Typ
Max
bbb
—
—
0.10
ddd
—
—
0.05
eee
—
—
0.08
Z
—
0.24
—
Y
—
0.18
—
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Solid State Outline MO-220, variation WGGD except for custom features D2, E2, Z, Y, and L
which are toleranced per supplier designation.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.1 | 39
EFM8SB2 Data Sheet
QFN24 Package Specifications
8.2 QFN24 PCB Land Pattern
Figure 8.2. QFN24 PCB Land Pattern Drawing
Table 8.2. QFN24 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
3.90
4.00
C2
3.90
4.00
E
0.50 BSC
X1
0.20
0.30
X2
2.70
2.80
Y1
0.65
0.75
Y2
2.70
2.80
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Rev. 1.1 | 40
EFM8SB2 Data Sheet
QFN24 Package Specifications
Dimension
Min
Max
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A 2 x 2 array of 1.10 mm x 1.10 mm openings on 1.30 mm pitch should be used for the center ground pad.
8. A No-Clean, Type-3 solder paste is recommended.
9. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components.
8.3 QFN24 Package Marking
PPPPPPPP
TTTTTT
YYWW #
Figure 8.3. QFN24 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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EFM8SB2 Data Sheet
QFP32 Package Specifications
9. QFP32 Package Specifications
9.1 QFP32 Package Dimensions
Figure 9.1. QFP32 Package Drawing
Table 9.1. QFP32 Package Dimensions
Dimension
Min
Typ
Max
A
—
—
1.60
A1
0.05
—
0.15
A2
1.35
1.40
1.45
b
0.30
0.37
0.45
D
9.00 BSC
D1
7.00 BSC
e
0.80 BSC
E
9.00 BSC
E1
7.00 BSC
L
aaa
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0.45
0.60
0.75
0.20
Rev. 1.1 | 42
EFM8SB2 Data Sheet
QFP32 Package Specifications
Dimension
Min
Typ
bbb
0.20
ccc
0.10
ddd
0.20
theta
0°
Max
3.5°
7°
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC outline MS-026, variation BBA.
4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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Rev. 1.1 | 43
EFM8SB2 Data Sheet
QFP32 Package Specifications
9.2 QFP32 PCB Land Pattern
Figure 9.2. QFP32 PCB Land Pattern Drawing
Table 9.2. QFP32 PCB Land Pattern Dimensions
Dimension
Min
Max
C1
8.40
8.50
C2
8.40
8.50
E
0.80 BSC
X1
0.40
0.50
Y1
1.25
1.35
Note:
1. All dimensions shown are in millimeters (mm) unless otherwise noted.
2. This Land Pattern Design is based on the IPC-7351 guidelines.
3. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 µm
minimum, all the way around the pad.
4. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release.
5. The stencil thickness should be 0.125 mm (5 mils).
6. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads.
7. A No-Clean, Type-3 solder paste is recommended.
8. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components.
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EFM8SB2 Data Sheet
QFP32 Package Specifications
9.3 QFP32 Package Marking
EFM8
PPPPPPPP
TTTTTT
YYWW #
Figure 9.3. QFP32 Package Marking
The package marking consists of:
• PPPPPPPP – The part number designation.
• TTTTTT – A trace or manufacturing code.
• YY – The last 2 digits of the assembly year.
• WW – The 2-digit workweek when the device was assembled.
• # – The device revision (A, B, etc.).
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Rev. 1.1 | 45
Table of Contents
1. Feature List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
3. System Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1 Introduction.
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. 4
3.2 Power
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3.3 I/O.
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. 5
3.4 Clocking .
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3.5 Counters/Timers and PWM .
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3.6 Communications and Other Digital Peripherals .
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3.7 Analog .
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3.9 Debugging .
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3.10 Bootloader
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4. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .
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4.1 Electrical Characteristics .
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4.2 Thermal Conditions .
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.19
4.3 Absolute Maximum Ratings .
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4.4 Typical Performance Curves .
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5. Typical Connection Diagrams . . . . . . . . . . . . . . . . . . . . . . . .
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5.1 Power
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5.2 Other Connections .
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6. Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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6.1 EFM8SB2x-QFN32 Pin Definitions .
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6.2 EFM8SB2x-QFN24 Pin Definitions .
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6.3 EFM8SB2x-QFP32 Pin Definitions .
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7. QFN32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
34
7.1 QFN32 Package Dimensions .
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7.2 QFN32 PCB Land Pattern .
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7.3 QFN32 Package Marking .
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8. QFN24 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
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8.1 QFN24 Package Dimensions .
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8.2 QFN24 PCB Land Pattern .
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8.3 QFN24 Package Marking .
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9. QFP32 Package Specifications. . . . . . . . . . . . . . . . . . . . . . . .
42
9.1 QFP32 Package Dimensions .
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.42
Table of Contents
46
9.2 QFP32 PCB Land Pattern .
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9.3 QFP32 Package Marking .
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.45
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
46
Table of Contents
47
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