Technical Data Sheet

STM32L151xD STM32L152xD
Ultra-low-power 32-bit MCU ARM® Cortex®-M3, 384KB Flash,
48KB SRAM, 12KB EEPROM, LCD, USB, ADC, DAC, memory I/F
Datasheet - production data
Features
• Ultra-low-power platform
– 1.65 V to 3.6 V power supply
– -40°C to 105°C temperature range
– 305 nA Standby mode (3 wakeup pins)
– 1.15 µA Standby mode + RTC
– 0.475 µA Stop mode (16 wakeup lines)
– 1.35 µA Stop mode + RTC
– 11 µA Low-power run mode
– 230 µA/MHz Run mode
– 10 nA ultra-low I/O leakage
– 8 µs wakeup time
• Core: ARM® Cortex®-M3 32-bit CPU
– From 32 kHz up to 32 MHz max
– 33.3 DMIPS peak (Dhrystone 2.1)
– Memory protection unit
• Up to 34 capacitive sensing channels
• CRC calculation unit, 96-bit unique ID
• Reset and supply management
– Low-power, ultrasafe BOR (brownout reset)
with 5 selectable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
• Clock sources
– 1 to 24 MHz crystal oscillator
– 32 kHz oscillator for RTC with calibration
– High Speed Internal 16 MHz factorytrimmed RC (+/- 1%)
– Internal low-power 37 kHz RC
– Internal multispeed low-power 65 kHz to
4.2 MHz
– PLL for CPU clock and USB (48 MHz)
• Pre-programmed bootloader
– USB and USART supported
• Serial wire debug, JTAG and trace
April 2015
This is information on a product in full production.
LQFP144 (20 × 20 mm)
LQFP100 (14 × 14 mm)
LQFP64 (10 × 10 mm)
UFBGA132
(7 × 7 mm)
WLCSP64
(0.400 mm pitch)
• Up to 116 fast I/Os (102 I/Os 5V tolerant), all
mappable on 16 external interrupt vectors
• Memories
– 384 KB Flash with ECC (with 2 banks of
192 KB enabling Rww capability)
– 48 KB RAM
– 12 KB of true EEPROM with ECC
– 128 Byte backup register
– Memory interface controller supporting
SRAM, PSRAM and NOR Flash
• LCD driver (except STM32L151xD devices) up
to 8x40 segments, contrast adjustment,
blinking mode, step-up converter
• Rich analog peripherals (down to 1.8V)
– 3x operational amplifiers
– 12-bit ADC 1 Msps up to 40 channels
– 12-bit DAC 2 ch with output buffers
– 2x ultra-low-power-comparators
(window mode and wakeup capability)
• DMA controller 12x channels
• 12x peripheral communication interfaces
– 1x USB 2.0 (internal 48 MHz PLL)
– 5x USART
– 3x SPI 16 Mbits/s (2x SPI with I2S)
– 2x I2C (SMBus/PMBus)
– 1x SDIO interface
• 11x timers: 1x 32-bit, 6x 16-bit with up to 4
IC/OC/PWM channels, 2x 16-bit basic timers,
2x watchdog timers (independent and window)
Table 1. Device summary
Reference
Part number
STM32L151xD
STM32L151QD, STM32L151RD,
STM32L151VD, STM32L151ZD
STM32L152xD
STM32L152QD, STM32L152RD,
STM32L152VD, STM32L152ZD
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Contents
STM32L151xD STM32L152xD
Contents
1
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3
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2.1
Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2.2
Ultra-low-power device continuum . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.1
Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.2
Shared peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2.3
Common system strategy. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.2.4
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1
Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2
ARM® Cortex®-M3 core with MPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3
Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.1
Power supply schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.2
Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.3.3
Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.3.4
Boot modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.4
Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5
Low-power real-time clock and backup registers . . . . . . . . . . . . . . . . . . . 25
3.6
GPIOs (general-purpose inputs/outputs) . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.7
Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.8
FSMC (flexible static memory controller) . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.9
DMA (direct memory access) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.10
LCD (liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11
ADC (analog-to-digital converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.1
Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.11.2
Internal voltage reference (VREFINT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.12
DAC (digital-to-analog converter) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.13
Operational amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
3.14
Ultra-low-power comparators and reference voltage . . . . . . . . . . . . . . . . 29
3.15
System configuration controller and routing interface . . . . . . . . . . . . . . . 30
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3.16
Touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.17
Timers and watchdogs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.18
3.17.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.17.2
Basic timers (TIM6 and TIM7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.17.3
SysTick timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.17.4
Independent watchdog (IWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.17.5
Window watchdog (WWDG) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18.1
I²C bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18.2
Universal synchronous/asynchronous receiver transmitter (USART) . . 32
3.18.3
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.18.4
Inter-integrated sound (I2S) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.18.5
SDIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.18.6
Universal serial bus (USB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.19
CRC (cyclic redundancy check) calculation unit . . . . . . . . . . . . . . . . . . . 33
3.20
Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.20.1
Serial wire JTAG debug port (SWJ-DP) . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.20.2
Embedded Trace Macrocell™ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
4
Pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
5
Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1
Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.1
Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.2
Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.3
Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.4
Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.5
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
6.1.6
Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
6.1.7
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.1.8
Current consumption measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
6.2
Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
6.3
Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
6.3.1
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
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STM32L151xD STM32L152xD
6.3.2
Embedded reset and power control block characteristics . . . . . . . . . . . 64
6.3.3
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6.3.4
Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
6.3.5
Wakeup time from low-power mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
6.3.6
External clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
6.3.7
Internal clock source characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
6.3.8
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.9
Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
6.3.10
FSMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
6.3.11
EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
6.3.12
Electrical sensitivity characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
6.3.13
I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
6.3.14
I/O port characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
6.3.15
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
6.3.16
TIM timer characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
6.3.17
Communications interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
6.3.18
SDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
6.3.19
12-bit ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
6.3.20
DAC electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
6.3.21
Operational amplifier characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 126
6.3.22
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.23
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
6.3.24
LCD controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.1
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
7.2
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
7.3
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
7.4
UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid
array package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
7.5
WLCSP64, 0.4 mm pitch wafer level chip scale package information . . 143
7.6
Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
7.6.1
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Reference document . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
9
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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List of tables
STM32L151xD STM32L152xD
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Table 32.
Table 33.
Table 34.
Table 35.
Table 36.
Table 37.
Table 38.
Table 39.
Table 40.
Table 41.
Table 42.
Table 43.
Table 44.
Table 45.
Table 46.
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Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ultra-low-power STM32L151xD and STM32L152xD device features
and peripheral counts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Functionalities depending on the operating power supply range . . . . . . . . . . . . . . . . . . . . 17
CPU frequency range depending on dynamic voltage scaling . . . . . . . . . . . . . . . . . . . . . . 18
Functionalities depending on the working mode (from Run/active down to
standby) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Timer feature comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Legend/abbreviations used in the pinout table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
STM32L151xD and STM32L152xD pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Alternate function input/output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 64
Embedded internal reference voltage calibration values . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Embedded internal reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Current consumption in Run mode, code with data processing running from Flash. . . . . . 68
Current consumption in Run mode, code with data processing running from RAM . . . . . . 69
Current consumption in Sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Current consumption in Low-power run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Current consumption in Low-power sleep mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Typical and maximum current consumptions in Stop mode . . . . . . . . . . . . . . . . . . . . . . . . 73
Typical and maximum current consumptions in Standby mode . . . . . . . . . . . . . . . . . . . . . 75
Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76
Low-power mode wakeup timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
High-speed external user clock characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Low-speed external user clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
LSE oscillator characteristics (fLSE = 32.768 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
MSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PLL characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Flash memory and data EEPROM characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Flash memory and data EEPROM endurance and retention . . . . . . . . . . . . . . . . . . . . . . . 89
Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings . . . . . . . . . . . . . . . . . . 91
Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . 92
Asynchronous multiplexed PSRAM/NOR read timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Asynchronous multiplexed PSRAM/NOR write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 99
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
EMS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
EMI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
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Table 47.
Table 48.
Table 49.
Table 50.
Table 51.
Table 52.
Table 53.
Table 54.
Table 55.
Table 56.
Table 57.
Table 58.
Table 59.
Table 60.
Table 61.
Table 62.
Table 63.
Table 64.
Table 65.
Table 66.
Table 67.
Table 68.
Table 69.
Table 70.
Table 71.
Table 72.
Table 73.
Table 74.
Table 75.
Table 76.
Table 77.
Table 78.
Table 79.
Table 80.
Table 81.
Table 82.
List of tables
ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Output voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
I/O AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
TIMx characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
I2C characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V). . . . . . . . . . . . . . . . . . . . . . . 111
SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
USB startup time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
USB DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
USB: full speed electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
I2S characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
SDIO characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
ADC clock frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
ADC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Maximum source impedance RAIN max . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Operational amplifier characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Temperature sensor calibration values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Temperature sensor characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
LCD controller characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical data . . . . . . . 132
LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical data . . . . . . . 134
LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data. . . . . . . . . . 137
UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
WLCSP64, 0.4 mm pitch wafer level chip scale package mechanical data . . . . . . . . . . . 143
WLCSP64, 0.4 mm pitch package recommended PCB design rules . . . . . . . . . . . . . . . . 144
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
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7
List of figures
STM32L151xD STM32L152xD
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Figure 10.
Figure 11.
Figure 12.
Figure 13.
Figure 14.
Figure 15.
Figure 16.
Figure 17.
Figure 18.
Figure 19.
Figure 20.
Figure 21.
Figure 22.
Figure 23.
Figure 24.
Figure 25.
Figure 26.
Figure 27.
Figure 28.
Figure 29.
Figure 30.
Figure 31.
Figure 32.
Figure 33.
Figure 34.
Figure 35.
Figure 36.
Figure 37.
Figure 38.
Figure 39.
Figure 40.
Figure 41.
Figure 42.
Figure 43.
Figure 44.
Figure 45.
8/154
Ultra-low-power STM32L151xD and STM32L152xD block diagram . . . . . . . . . . . . . . . . . 15
Clock tree . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
STM32L15xZD LQFP144 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
STM32L15xQD UFBGA132 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
STM32L15xVD LQFP100 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
STM32L15xRD LQFP64 pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
STM32L15xRD WLCSP64 ballout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Power supply scheme. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Optional LCD power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Current consumption measurement scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
High-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Low-speed external clock source AC timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Typical application with a 32.768 kHz crystal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms . . . . . . . . . . . . . . . 90
Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms . . . . . . . . . . . . . . . 91
Asynchronous multiplexed PSRAM/NOR read waveforms. . . . . . . . . . . . . . . . . . . . . . . . . 92
Asynchronous multiplexed PSRAM/NOR write waveforms . . . . . . . . . . . . . . . . . . . . . . . . 93
Synchronous multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Synchronous multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Synchronous non-multiplexed NOR/PSRAM read timings . . . . . . . . . . . . . . . . . . . . . . . . . 99
Synchronous non-multiplexed PSRAM write timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
I/O AC characteristics definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Recommended NRST pin protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
I2C bus AC waveforms and measurement circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
SPI timing diagram - slave mode and CPHA = 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI timing diagram - slave mode and CPHA = 1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
SPI timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
USB timings: definition of data signal rise and fall time . . . . . . . . . . . . . . . . . . . . . . . . . . 115
I2S slave timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
I2S master timing diagram (Philips protocol)(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
SDIO timings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
ADC accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
12-bit buffered /non-buffered DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 131
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package top view example . . . . . . 133
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline . . . . . . . . . . . . . . . 134
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view example . . . . . . 136
DocID022027 Rev 10
STM32L151xD STM32L152xD
Figure 46.
Figure 47.
Figure 48.
Figure 49.
Figure 50.
Figure 51.
Figure 52.
Figure 53.
Figure 54.
Figure 55.
Figure 56.
List of figures
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline . . . . . . . . . . . . . . . . . 137
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example . . . . . . . . . 139
UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package outline . . . . 140
UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
top view example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
WLCSP64, 0.4 mm pitch wafer level chip scale package outline . . . . . . . . . . . . . . . . . . . 143
WLCSP64, 0.4 mm pitch wafer level chip scale package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
WLCSP64, 0.4 mm pitch wafer level chip scale package top view example . . . . . . . . . . 145
Thermal resistance suffix 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
Thermal resistance suffix 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147
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9
Introduction
1
STM32L151xD STM32L152xD
Introduction
This datasheet provides the ordering information and mechanical device characteristics of
the STM32L151xD and STM32L152xD ultra-low-power ARM® Cortex®-M3 based
microcontroller product line.
STM32L151xD and STM32L152xD microcontrollers feature 384 Kbytes of Flash memory.
The ultra-low-power STM32L151xD and STM32L152xD family includes devices in 5
different package types: from 64 pins to 144 pins. Depending on the device chosen,
different sets of peripherals are included, the description below gives an overview of the
complete range of peripherals proposed in this family.
These features make the ultra-low-power STM32L151xD and STM32L152xD
microcontroller family suitable for a wide range of applications:
•
Medical and handheld equipment
•
Application control and user interface
•
PC peripherals, gaming, GPS and sport equipment
•
Alarm systems, wired and wireless sensors, video intercom
•
Utility metering
This STM32L151xD and STM32L152xD datasheet should be read in conjunction with the
STM32L1xxxx reference manual (RM0038). The application note “Getting started with
STM32L1xxxx hardware development” (AN3216) gives a hardware implementation
overview. Both documents are available from the STMicroelectronics website www.st.com.
For information on the ARM® Cortex®-M3 core please refer to the ARM® Cortex®-M3
technical reference manual, available from the www.arm.com website. Figure 1 shows the
general block diagram of the device family.
10/154
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STM32L151xD STM32L152xD
2
Description
Description
The ultra-low-power STM32L151xD and STM32L152xD devices incorporate the
connectivity power of the universal serial bus (USB) with the high-performance ARM®
Cortex®-M3 32-bit RISC core operating at a frequency of 32 MHz (33.3 DMIPS), a memory
protection unit (MPU), high-speed embedded memories (Flash memory up to 384 Kbytes
and RAM up to 48 Kbytes), a flexible static memory controller (FSMC) interface (for devices
with packages of 100 pins and more) and an extensive range of enhanced I/Os and
peripherals connected to two APB buses.
The STM32L151xD and STM32L152xD devices offer three operational amplifiers, one 12bit ADC, two DACs, two ultra-low-power comparators, one general-purpose 32-bit timer, six
general-purpose 16-bit timers and two basic timers, which can be used as time bases.
Moreover, the STM32L151xD and STM32L152xD devices contain standard and advanced
communication interfaces: up to two I2Cs, three SPIs, two I2S, one SDIO, three USARTs,
two UARTs, and an USB. The STM32L151xD and STM32L152xD devices offer up to
34 capacitive sensing channels to simply add a touch sensing functionality to any
application.
They also include a real-time clock and a set of backup registers that remain powered in
Standby mode.
Finally, the integrated LCD controller (except STM32L151xD devices) has a built-in LCD
voltage generator that allows to drive up to 8 multiplexed LCDs with the contrast
independent of the supply voltage.
The ultra-low-power STM32L151xD and STM32L152xD devices operate from a 1.8 to 3.6 V
power supply (down to 1.65 V at power down) with BOR and from a 1.65 to 3.6 V power
supply without BOR option. They are available in the -40 to +85 °C and -40 to +105 °C
temperature ranges. A comprehensive set of power-saving modes allows the design of lowpower applications.
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58
Description
2.1
STM32L151xD STM32L152xD
Device overview
Table 2. Ultra-low-power STM32L151xD and STM32L152xD device features
and peripheral counts
Peripheral
STM32L15xRD
STM32L15xVD
STM32L15xQD
Flash (Kbytes)
384
Data EEPROM (Kbytes)
12
RAM (Kbytes)
48
FSMC
Timers
No
multiplexed only
1
Generalpurpose
6
Basic
2
3/(2)
I2C
2
USART
5
USB
1
SDIO
1
GPIOs
51
83
Operation amplifiers
12-bit synchronized ADC
Number of channels
LCD (STM32L152xx devices
only)
COM x SEG
1
21
1
25
1
40
1
40
1
1
4x32 or 8x28
4x44 or 8x40
2
23
Max. CPU frequency
Operating voltage
115
2
2
Comparators
Capacitive sensing channels
109
3
12-bit DAC
Number of channels
12/154
Yes
32 bit
SPI/(I2S)
Communication
interfaces
STM32L15xZD
33
34
32 MHz
1.8 V to 3.6 V (down to 1.65 V at power-down) with BOR option
1.65 V to 3.6 V without BOR option
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STM32L151xD STM32L152xD
Description
Table 2. Ultra-low-power STM32L151xD and STM32L152xD device features
and peripheral counts (continued)
Peripheral
Operating temperatures
STM32L15xVD
STM32L15xQD
STM32L15xZD
Ambient operating temperature: -40 °C to 85 °C / -40 °C to 105 °C
Junction temperature: –40 to + 110 °C
LQFP64,
WLCSP64
Packages
2.2
STM32L15xRD
LQFP100
UFBGA132
LQFP144
Ultra-low-power device continuum
The ultra-low-power family offers a large choice of cores and features. From proprietary 8bit to up to Cortex-M3, including the Cortex-M0+, the STM32Lx series are the best choice to
answer your needs, in terms of ultra-low-power features. The STM32 Ultra-low-power series
are the best fit, for instance, for gas/water meter, keyboard/mouse or fitness and healthcare,
wearable applications. Several built-in features like LCD drivers, dual-bank
memory, Low-power run mode, op-amp, AES 128-bit, DAC, USB crystal-less and many
others will clearly allow to build very cost-optimized applications by reducing BOM.
Note:
STMicroelectronics as a reliable and long-term manufacturer ensures as much as possible
the pin-to-pin compatibility between any STM8Lxxxxx and STM32Lxxxxx devices and
between any of the STM32Lx and STM32Fx series. Thanks to this unprecedented
scalability, your old applications can be upgraded to respond to the latest market features
and efficiency demand.
2.2.1
Performance
All families incorporate highly energy-efficient cores with both Harvard architecture and
pipelined execution: advanced STM8 core for STM8L families and ARM Cortex-M3 core for
STM32L family. In addition specific care for the design architecture has been taken to
optimize the mA/DMIPS and mA/MHz ratios.
This allows the ultra-low-power performance to range from 5 up to 33.3 DMIPs.
2.2.2
Shared peripherals
STM8L15xxx, STM32L15xxx and STM32L162xx share identical peripherals which ensure a
very easy migration from one family to another:
•
Analog peripherals: ADC, DAC and comparators
•
Digital peripherals: RTC and some communication interfaces
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58
Description
2.2.3
STM32L151xD STM32L152xD
Common system strategy.
To offer flexibility and optimize performance, the STM8L15xxx, STM32L15xxx and
STM32L162xx family uses a common architecture:
2.2.4
•
Same power supply range from 1.65 V to 3.6 V
•
Architecture optimized to reach ultra-low consumption both in low-power modes and
Run mode
•
Fast startup strategy from low-power modes
•
Flexible system clock
•
Ultrasafe reset: same reset strategy including power-on reset, power-down reset,
brownout reset and programmable voltage detector
Features
ST ultra-low-power continuum also lies in feature compatibility:
14/154
•
More than 15 packages with pin count from 20 to 144 pins and size down to 3 x 3 mm
•
Memory density ranging from 2 to 512 Kbytes
DocID022027 Rev 10
STM32L151xD STM32L152xD
Functional overview
Figure 1. Ultra-low-power STM32L151xD and STM32L152xD block diagram
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58
Functional overview
3.1
STM32L151xD STM32L152xD
Low-power modes
The ultra-low-power STM32L151xD and STM32L152xD devices support dynamic voltage
scaling to optimize its power consumption in run mode. The voltage from the internal lowdrop regulator that supplies the logic can be adjusted according to the system’s maximum
operating frequency and the external voltage supply.
There are three power consumption ranges:
•
Range 1 (VDD range limited to 1.71 V - 3.6 V), with the CPU running at up to 32 MHz
•
Range 2 (full VDD range), with a maximum CPU frequency of 16 MHz
•
Range 3 (full VDD range), with a maximum CPU frequency limited to 4 MHz (generated
only with the multispeed internal RC oscillator clock source)
Seven low-power modes are provided to achieve the best compromise between low-power
consumption, short startup time and available wakeup sources:
•
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs. Sleep mode power consumption at
16 MHz is about 1 mA with all peripherals off.
•
Low-power run mode
This mode is achieved with the multispeed internal (MSI) RC oscillator set to the
minimum clock (131 kHz), execution from SRAM or Flash memory, and internal
regulator in low-power mode to minimize the regulator's operating current. In low-power
run mode, the clock frequency and the number of enabled peripherals are both limited.
•
Low-power sleep mode
This mode is achieved by entering Sleep mode with the internal voltage regulator in
Low-power mode to minimize the regulator’s operating current. In Low-power sleep
mode, both the clock frequency and the number of enabled peripherals are limited; a
typical example would be to have a timer running at 32 kHz.
When wakeup is triggered by an event or an interrupt, the system reverts to the run
mode with the regulator on.
•
Stop mode with RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents and real time clock. All clocks in the VCORE domain are stopped, the
PLL, MSI RC, HSI RC and HSE crystal oscillators are disabled. The LSE or LSI is still
running. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on), it can
be the RTC alarm(s), the USB wakeup, the RTC tamper events, the RTC timestamp
event or the RTC wakeup.
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STM32L151xD STM32L152xD
•
Functional overview
Stop mode without RTC
Stop mode achieves the lowest power consumption while retaining the RAM and
register contents. All clocks are stopped, the PLL, MSI RC, HSI and LSI RC, LSE and
HSE crystal oscillators are disabled. The voltage regulator is in the low-power mode.
The device can be woken up from Stop mode by any of the EXTI line, in 8 µs. The EXTI
line source can be one of the 16 external lines. It can be the PVD output, the
Comparator 1 event or Comparator 2 event (if internal reference voltage is on). It can
also be wakened by the USB wakeup.
•
Standby mode with RTC
Standby mode is used to achieve the lowest power consumption and real time clock.
The internal voltage regulator is switched off so that the entire VCORE domain is
powered off. The PLL, MSI RC, HSI RC and HSE crystal oscillators are also switched
off. The LSE or LSI is still running. After entering Standby mode, the RAM and register
contents are lost except for registers in the Standby circuitry (wakeup logic, IWDG,
RTC, LSI, LSE Crystal 32K osc, RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin), an IWDG
reset, a rising edge on one of the three WKUP pins, RTC alarm (Alarm A or Alarm B),
RTC tamper event, RTC timestamp event or RTC Wakeup event occurs.
•
Standby mode without RTC
Standby mode is used to achieve the lowest power consumption. The internal voltage
regulator is switched off so that the entire VCORE domain is powered off. The PLL, MSI
RC, HSI and LSI RC, HSE and LSE crystal oscillators are also switched off. After
entering Standby mode, the RAM and register contents are lost except for registers in
the Standby circuitry (wakeup logic, IWDG, RTC, LSI, LSE Crystal 32K osc,
RCC_CSR).
The device exits Standby mode in 60 µs when an external reset (NRST pin) or a rising
edge on one of the three WKUP pin occurs.
Note:
The RTC, the IWDG, and the corresponding clock sources are not stopped automatically by
entering Stop or Standby mode.
Table 3. Functionalities depending on the operating power supply range
Functionalities depending on the operating power supply range
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage
scaling range
I/O operation
VDD= VDDA = 1.65 to 1.71 V
Not functional
Not functional
Range 2 or
Range 3
Degraded speed
performance
Not functional
Not functional
Range 1, Range 2
or Range 3
Degraded speed
performance
Conversion time up
to 500 Ksps
Not functional
Range 1, Range 2
or
Range 3
Degraded speed
performance
VDD=VDDA= 1.71 to 1.8 V(1)
VDD=VDDA= 1.8 to 2.0 V(1)
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Functional overview
STM32L151xD STM32L152xD
Table 3. Functionalities depending on the operating power supply range (continued)
Functionalities depending on the operating power supply range
Operating power supply
range
DAC and ADC
operation
USB
Dynamic voltage
scaling range
I/O operation
VDD=VDDA = 2.0 to 2.4 V
Conversion time up
to 500 Ksps
Functional(2)
Range 1, Range 2
or Range 3
Full speed operation
VDD=VDDA = 2.4 to 3.6 V
Conversion time up
to 1 Msps
Functional(2)
Range 1, Range 2
or Range 3
Full speed operation
1. CPU frequency changes from initial to final must respect “FCPU initial < 4*FCPU final” to limit VCORE drop due to current
consumption peak when frequency increases. It must also respect 5 µs delay between two changes. For example to switch
from 4.2 MHz to 32 MHz, you can switch from 4.2 MHz to 16 MHz, wait 5 µs, then switch from 16 MHz to 32 MHz.
2. Should be USB compliant from I/O voltage standpoint, the minimum VDD is 3.0 V.
Table 4. CPU frequency range depending on dynamic voltage scaling
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CPU frequency range
Dynamic voltage scaling range
16 MHz to 32 MHz (1ws)
32 kHz to 16 MHz (0ws)
Range 1
8 MHz to 16 MHz (1ws)
32 kHz to 8 MHz (0ws)
Range 2
2.1MHz to 4.2 MHz (1ws)
32 kHz to 2.1 MHz (0ws)
Range 3
DocID022027 Rev 10
STM32L151xD STM32L152xD
Functional overview
Table 5. Functionalities depending on the working mode (from Run/active down to
standby)
Standby
Run/Active
Sleep
CPU
Y
--
Y
--
--
--
--
--
Flash
Y
Y
Y
Y
--
--
--
--
RAM
Y
Y
Y
Y
Y
--
--
--
Backup Registers
Y
Y
Y
Y
Y
--
Y
--
EEPROM
Y
Y
Y
Y
Y
--
--
--
Brown-out rest
(BOR)
Y
Y
Y
Y
Y
Y
Y
--
DMA
Y
Y
Y
Y
--
--
--
--
Programmable
Voltage Detector
(PVD)
Y
Y
Y
Y
Y
Y
Y
--
Power On Reset
(POR)
Y
Y
Y
Y
Y
Y
Y
--
Power Down Rest
(PDR)
Y
Y
Y
Y
Y
--
Y
--
High Speed
Internal (HSI)
Y
Y
--
--
--
--
--
--
High Speed
External (HSE)
Y
Y
--
--
--
--
--
--
Low Speed Internal
(LSI)
Y
Y
Y
Y
Y
--
--
--
Low Speed
External (LSE)
Y
Y
Y
Y
Y
--
--
--
Multi-Speed
Internal (MSI)
Y
Y
Y
Y
--
--
--
--
Inter-Connect
Controller
Y
Y
Y
Y
--
--
--
--
RTC
Y
Y
Y
Y
Y
Y
Y
--
RTC Tamper
Y
Y
Y
Y
Y
Y
Y
Y
Auto WakeUp
(AWU)
Y
Y
Y
Y
Y
Y
Y
Y
LCD
Y
Y
Y
Y
Y
--
--
--
USB
Y
Y
--
--
--
Y
--
--
--
--
Ips
Lowpower
Sleep
Stop
Lowpower
Run
Wakeup
capability
Wakeup
capability
USART
Y
Y
Y
Y
Y
(1)
SPI
Y
Y
Y
Y
--
--
--
--
I2C
Y
Y
Y
Y
--
(1)
--
--
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58
Functional overview
STM32L151xD STM32L152xD
Table 5. Functionalities depending on the working mode (from Run/active down to
standby) (continued)
Standby
Run/Active
Sleep
ADC
Y
Y
--
--
--
--
--
--
DAC
Y
Y
Y
Y
Y
--
--
--
Tempsensor
Y
Y
Y
Y
Y
--
--
--
OP amp
Y
Y
Y
Y
Y
--
--
--
Comparators
Y
Y
Y
Y
Y
Y
--
--
16-bit and 32-bit
Timers
Y
Y
Y
Y
--
--
--
--
IWDG
Y
Y
Y
Y
Y
Y
Y
Y
WWDG
Y
Y
Y
Y
--
--
--
--
Touch sensing
Y
Y
--
--
--
--
--
--
Systic Timer
Y
Y
Y
Y
--
--
--
GPIOs
Y
Y
Y
Y
Y
--
3 pins
0 µs
0.4 µs
3 µs
46 µs
Ips
Wakeup time to
Run mode
Consumption
VDD=1.8 to 3.6 V
(Typ)
Down to 230
µA/MHz (from
Flash)
Down to 43
µA/MHz (from
Flash)
Down to
11 µA
Lowpower
Sleep
Stop
Lowpower
Run
Down to
4.4 µA
Wakeup
capability
Y
Wakeup
capability
< 8 µs
58 µs
0.475 µA
(no RTC)
VDD=1.8V
0.305 µA
(no RTC)
VDD=1.8V
1.1 µA
(with RTC)
VDD=1.8V
0.82 µA
(with RTC)
VDD=1.8V
0.475 µA
(no RTC)
VDD=3.0V
0.305 µA
(no RTC)
VDD=3.0V
1.35 µA
(with RTC)
VDD=3.0V
1.15 µA
(with RTC)
VDD=3.0V
1. The startup on communication line wakes the CPU which was made possible by an EXTI, this induces a delay before
entering run mode.
3.2
ARM® Cortex®-M3 core with MPU
The ARM® Cortex®-M3 processor is the industry leading processor for embedded systems.
It has been developed to provide a low-cost platform that meets the needs of MCU
implementation, with a reduced pin count and low-power consumption, while delivering
outstanding computational performance and an advanced system response to interrupts.
The ARM® Cortex®-M3 32-bit RISC processor features exceptional code-efficiency,
delivering the high-performance expected from an ARM core in the memory size usually
associated with 8- and 16-bit devices.
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Functional overview
The memory protection unit (MPU) improves system reliability by defining the memory
attributes (such as read/write access permissions) for different memory regions. It provides
up to eight different regions and an optional predefined background region.
Owing to its embedded ARM core, the STM32L151xD and STM32L152xD devices are
compatible with all ARM tools and software.
Nested vectored interrupt controller (NVIC)
The ultra-low-power STM32L151xD and STM32L152xD devices embed a nested vectored
interrupt controller able to handle up to 56 maskable interrupt channels (not including the 16
interrupt lines of ARM® Cortex®-M3) and 16 priority levels.
•
Closely coupled NVIC gives low-latency interrupt processing
•
Interrupt entry vector table address passed directly to the core
•
Closely coupled NVIC core interface
•
Allows early processing of interrupts
•
Processing of late arriving, higher-priority interrupts
•
Support for tail-chaining
•
Processor state automatically saved
•
Interrupt entry restored on interrupt exit with no instruction overhead
This hardware block provides flexible interrupt management features with minimal interrupt
latency.
3.3
Reset and supply management
3.3.1
Power supply schemes
3.3.2
•
VDD = 1.65 to 3.6 V: external power supply for I/Os and the internal regulator. Provided
externally through VDD pins.
•
VSSA, VDDA = 1.65 to 3.6 V: external analog power supplies for ADC, reset blocks, RCs
and PLL (minimum voltage to be applied to VDDA is 1.8 V when the ADC is used). VDDA
and VSSA must be connected to VDD and VSS, respectively.
Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR) that can be coupled with a brownout reset (BOR) circuitry.
The device exists in two versions:
•
The version with BOR activated at power-on operates between 1.8 V and 3.6 V.
•
The other version without BOR operates between 1.65 V and 3.6 V.
After the VDD threshold is reached (1.65 V or 1.8 V depending on the BOR which is active or
not at power-on), the option byte loading process starts, either to confirm or modify default
thresholds, or to disable the BOR permanently: in this case, the VDD min value becomes
1.65 V (whatever the version, BOR active or not, at power-on).
When BOR is active at power-on, it ensures proper operation starting from 1.8 V whatever
the power ramp-up phase before it reaches 1.8 V. When BOR is not active at power-up, the
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58
Functional overview
STM32L151xD STM32L152xD
power ramp-up should guarantee that 1.65 V is reached on VDD at least 1 ms after it exits
the POR area.
Five BOR thresholds are available through option bytes, starting from 1.8 V to 3 V. To
reduce the power consumption in Stop mode, it is possible to automatically switch off the
internal reference voltage (VREFINT) in Stop mode. The device remains in reset mode when
VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any external
reset circuit.
Note:
The start-up time at power-on is typically 3.3 ms when BOR is active at power-up, the startup time at power-on can be decreased down to 1 ms typically for devices with BOR inactive
at power-up.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt can be generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine can then generate
a warning message and/or put the MCU into a safe state. The PVD is enabled by software.
3.3.3
Voltage regulator
The regulator has three operation modes: main (MR), low-power (LPR) and power down.
3.3.4
•
MR is used in Run mode (nominal regulation)
•
LPR is used in the Low-power run, Low-power sleep and Stop modes
•
Power down is used in Standby mode. The regulator output is high impedance, the
kernel circuitry is powered down, inducing zero consumption but the contents of the
registers and RAM are lost except for the standby circuitry (wakeup logic, IWDG, RTC,
LSI, LSE crystal 32K osc, RCC_CSR).
Boot modes
At startup, boot pins are used to select one of three boot options:
•
Boot from Flash memory
•
Boot from System memory
•
Boot from embedded RAM
The boot loader is located in System memory. It is used to reprogram the Flash memory by
using USART1, USART2 or USB. See Application note “STM32 microcontroller system
memory boot mode” (AN2606) for details.
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3.4
Functional overview
Clock management
The clock controller distributes the clocks coming from different oscillators to the core and
the peripherals. It also manages clock gating for low-power modes and ensures clock
robustness. It features:
•
Clock prescaler: to get the best trade-off between speed and current consumption, the
clock frequency to the CPU and peripherals can be adjusted by a programmable
prescaler.
•
Safe clock switching: clock sources can be changed safely on the fly in run mode
through a configuration register.
•
Clock management: to reduce power consumption, the clock controller can stop the
clock to the core, individual peripherals or memory.
•
System clock source: three different clock sources can be used to drive the master
clock SYSCLK:
•
–
1-24 MHz high-speed external crystal (HSE), that can supply a PLL
–
16 MHz high-speed internal RC oscillator (HSI), trimmable by software, that can
supply a PLL
–
Multispeed internal RC oscillator (MSI), trimmable by software, able to generate 7
frequencies (65 kHz, 131 kHz, 262 kHz, 524 kHz, 1.05 MHz, 2.1 MHz, 4.2 MHz).
When a 32.768 kHz clock source is available in the system (LSE), the MSI
frequency can be trimmed by software down to a ±0.5% accuracy.
Auxiliary clock source: two ultra-low-power clock sources that can be used to drive
the LCD controller and the real-time clock:
–
32.768 kHz low-speed external crystal (LSE)
–
37 kHz low-speed internal RC (LSI), also used to drive the independent watchdog.
The LSI clock can be measured using the high-speed internal RC oscillator for
greater precision.
•
RTC and LCD clock sources: the LSI, LSE or HSE sources can be chosen to clock
the RTC and the LCD, whatever the system clock.
•
USB clock source: the embedded PLL has a dedicated 48 MHz clock output to supply
the USB interface.
•
Startup clock: after reset, the microcontroller restarts by default with an internal 2 MHz
clock (MSI). The prescaler ratio and clock source can be changed by the application
program as soon as the code execution starts.
•
Clock security system (CSS): this feature can be enabled by software. If a HSE clock
failure occurs, the master clock is automatically switched to HSI and a software
interrupt is generated if enabled.
•
Clock-out capability (MCO: microcontroller clock output): it outputs one of the
internal clocks for external use by the application.
Several prescalers allow the configuration of the AHB frequency, each APB (APB1 and
APB2) domains. The maximum frequency of the AHB and the APB domains is 32 MHz. See
Figure 2 for details on the clock tree.
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Functional overview
STM32L151xD STM32L152xD
Figure 2. Clock tree
3TANDBYSUPPLIEDVOLTAGEDOMAIN
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-36
1. For the USB function to be available, both HSE and PLL must be enabled, with the CPU running at either
24 MHz or 32 MHz.
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STM32L151xD STM32L152xD
3.5
Functional overview
Low-power real-time clock and backup registers
The real-time clock (RTC) is an independent BCD timer/counter. Dedicated registers contain
the sub-second, second, minute, hour (12/24 hour), week day, date, month, year, in BCD
(binary-coded decimal) format. Correction for 28, 29 (leap year), 30, and 31 day of the
month are made automatically. The RTC provides two programmable alarms and
programmable periodic interrupts with wakeup from Stop and Standby modes.
The programmable wakeup time ranges from 120 µs to 36 hours.
The RTC can be calibrated with an external 512 Hz output, and a digital compensation
circuit helps reduce drift due to crystal deviation.
The RTC can also be automatically corrected with a 50/60Hz stable powerline.
The RTC calendar can be updated on the fly down to sub second precision, which enables
network system synchronization.
A time stamp can record an external event occurrence, and generates an interrupt.
There are thirty-two 32-bit backup registers provided to store 128 bytes of user application
data. They are cleared in case of tamper detection.
Three pins can be used to detect tamper events. A change on one of these pins can reset
backup register and generate an interrupt. To prevent false tamper event, like ESD event,
these three tamper inputs can be digitally filtered.
3.6
GPIOs (general-purpose inputs/outputs)
Each of the GPIO pins can be configured by software as output (push-pull or open-drain), as
input (with or without pull-up or pull-down) or as peripheral alternate function. Most of the
GPIO pins are shared with digital or analog alternate functions, and can be individually
remapped using dedicated AFIO registers. All GPIOs are high current capable. The
alternate function configuration of I/Os can be locked if needed following a specific
sequence in order to avoid spurious writing to the I/O registers. The I/O controller is
connected to the AHB with a toggling speed of up to 16 MHz.
External interrupt/event controller (EXTI)
The external interrupt/event controller consists of 24 edge detector lines used to generate
interrupt/event requests. Each line can be individually configured to select the trigger event
(rising edge, falling edge, both) and can be masked independently. A pending register
maintains the status of the interrupt requests. The EXTI can detect an external line with a
pulse width shorter than the Internal APB2 clock period. Up to 115 GPIOs can be connected
to the 16 external interrupt lines. The 8 other lines are connected to RTC, PVD, USB,
comparator events or capacitive sensing acquisition.
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3.7
STM32L151xD STM32L152xD
Memories
The STM32L151xD and STM32L152xD devices have the following features:
•
48 Kbytes of embedded RAM accessed (read/write) at CPU clock speed with 0 wait
states. With the enhanced bus matrix, operating the RAM does not lead to any
performance penalty during accesses to the system bus (AHB and APB buses).
•
The non-volatile memory is divided into three arrays:
–
384 Kbytes of embedded Flash program memory
–
12 Kbytes of data EEPROM
–
Options bytes
Flash program and data EEPROM are divided into two banks, this enables writing in
one bank while running code or reading data in the other bank.
The options bytes are used to write-protect or read-out protect the memory (with 4 KB
granularity) and/or readout-protect the whole memory with the following options:
–
Level 0: no readout protection
–
Level 1: memory readout protection, the Flash memory cannot be read from or
written to if either debug features are connected or boot in RAM is selected
–
Level 2: chip readout protection, debug features (ARM Cortex-M3 JTAG and serial
wire) and boot in RAM selection disabled (JTAG fuse)
The whole non-volatile memory embeds the error correction code (ECC) feature.
3.8
FSMC (flexible static memory controller)
The FSMC supports the following modes: SRAM, PSRAM, NOR/OneNAND Flash.
Functionality overview:
3.9
•
Up to 26 bit address bus
•
Up to 16-bit data bus
•
Write FIFO
•
Burst mode
•
Code execution from external memory
•
Four chip select signals
•
Up to 32 MHz external access
DMA (direct memory access)
The flexible 12-channel, general-purpose DMA is able to manage memory-to-memory,
peripheral-to-memory and memory-to-peripheral transfers. The DMA controller supports
circular buffer management, avoiding the generation of interrupts when the controller
reaches the end of the buffer.
Each channel is connected to dedicated hardware DMA requests, with software trigger
support for each channel. Configuration is done by software and transfer sizes between
source and destination are independent.
The DMA can be used with the main peripherals: SPI, I2C, USART, SDIO, general-purpose
timers, DAC and ADC.
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3.10
Functional overview
LCD (liquid crystal display)
The LCD drives up to 8 common terminals and 44 segment terminals to drive up to 320
pixels.
3.11
•
Internal step-up converter to guarantee functionality and contrast control irrespective of
VDD. This converter can be deactivated, in which case the VLCD pin is used to provide
the voltage to the LCD
•
Supports static, 1/2, 1/3, 1/4 and 1/8 duty
•
Supports static, 1/2, 1/3 and 1/4 bias
•
Phase inversion to reduce power consumption and EMI
•
Up to 8 pixels can be programmed to blink
•
Unneeded segments and common pins can be used as general I/O pins
•
LCD RAM can be updated at any time owing to a double-buffer
•
The LCD controller can operate in Stop mode
ADC (analog-to-digital converter)
A 12-bit analog-to-digital converters is embedded into STM32L151xD and STM32L152xD
devices with up to 40 external channels, performing conversions in single-shot or scan
mode. In scan mode, automatic conversion is performed on a selected group of analog
inputs with up to 28 external channels in a group.
The ADC can be served by the DMA controller.
An analog watchdog feature allows very precise monitoring of the converted voltage of one,
some or all scanned channels. An interrupt is generated when the converted voltage is
outside the programmed thresholds.
The events generated by the general-purpose timers (TIMx) can be internally connected to
the ADC start triggers, to allow the application to synchronize A/D conversions and timers.
An injection mode allows high priority conversions to be done by interrupting a scan mode
which runs in as a background task.
The ADC includes a specific low-power mode. The converter is able to operate at maximum
speed even if the CPU is operating at a very low frequency and has an auto-shutdown
function. The ADC’s runtime and analog front-end current consumption are thus minimized
whatever the MCU operating mode.
3.11.1
Temperature sensor
The temperature sensor (TS) generates a voltage VSENSE that varies linearly with
temperature.
The temperature sensor is internally connected to the ADC_IN16 input channel which is
used to convert the sensor output voltage into a digital value.
The sensor provides good linearity but it has to be calibrated to obtain good overall
accuracy of the temperature measurement. As the offset of the temperature sensor varies
from chip to chip due to process variation, the uncalibrated internal temperature sensor is
suitable for applications that detect temperature changes only.
To improve the accuracy of the temperature sensor measurement, each device is
individually factory-calibrated by ST. The temperature sensor factory calibration data are
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STM32L151xD STM32L152xD
stored by ST in the system memory area, accessible in read-only mode. See Table 69:
Temperature sensor calibration values.
3.11.2
Internal voltage reference (VREFINT)
The internal voltage reference (VREFINT) provides a stable (bandgap) voltage output for the
ADC and Comparators. VREFINT is internally connected to the ADC_IN17 input channel. It
enables accurate monitoring of the VDD value (when no external voltage, VREF+, is
available for ADC). The precise voltage of VREFINT is individually measured for each part by
ST during production test and stored in the system memory area. It is accessible in readonly mode. See Table 15: Embedded internal reference voltage calibration values.
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3.12
Functional overview
DAC (digital-to-analog converter)
The two 12-bit buffered DAC channels can be used to convert two digital signals into two
analog voltage signal outputs. The chosen design structure is composed of integrated
resistor strings and an amplifier in non-inverting configuration.
This dual digital Interface supports the following features:
•
Two DAC converters: one for each output channel
•
8-bit or 12-bit monotonic output
•
Left or right data alignment in 12-bit mode
•
Synchronized update capability
•
Noise-wave generation
•
Triangular-wave generation
•
Dual DAC channels, independent or simultaneous conversions
•
DMA capability for each channel (including the underrun interrupt)
•
External triggers for conversion
•
Input reference voltage VREF+
Eight DAC trigger inputs are used in the STM32L151xD and STM32L152xD devices. The
DAC channels are triggered through the timer update outputs that are also connected to
different DMA channels.
3.13
Operational amplifier
The STM32L151xD and STM32L152xD devices embed three operational amplifiers with
external or internal follower routing capability (or even amplifier and filter capability with
external components). When one operational amplifier is selected, one external ADC
channel is used to enable output measurement.
The operational amplifiers feature:
3.14
•
Low input bias current
•
Low offset voltage
•
Low-power mode
•
Rail-to-rail input
Ultra-low-power comparators and reference voltage
The STM32L151xD and STM32L152xD devices embed two comparators sharing the same
current bias and reference voltage. The reference voltage can be internal or external
(coming from an I/O).
•
One comparator with fixed threshold
•
One comparator with rail-to-rail inputs, fast or slow mode. The threshold can be one of
the following:
–
DAC output
–
External I/O
–
Internal reference voltage (VREFINT) or a sub-multiple (1/4, 1/2, 3/4)
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Both comparators can wake up from Stop mode, and be combined into a window
comparator.
The internal reference voltage is available externally via a low-power / low-current output
buffer (driving current capability of 1 µA typical).
3.15
System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports.
The highly flexible routing interface allows the application firmware to control the routing of
different I/Os to the TIM2, TIM3 and TIM4 timer input captures. It also controls the routing of
internal analog signals to ADC1, COMP1 and COMP2 and the internal reference voltage
VREFINT.
3.16
Touch sensing
The STM32L151xD and STM32L152xD devices provide a simple solution for adding
capacitive sensing functionality to any application. These devices offer up to 34 capacitive
sensing channels distributed over 11 analog I/O groups. Both software and timer capacitive
sensing acquisition modes are supported.
Capacitive sensing technology is able to detect the presence of a finger near a sensor which
is protected from direct touch by a dielectric (glass, plastic...). The capacitive variation
introduced by the finger (or any conductive object) is measured using a proven
implementation based on a surface charge transfer acquisition principle. It consists of
charging the sensor capacitance and then transferring a part of the accumulated charges
into a sampling capacitor until the voltage across this capacitor has reached a specific
threshold. The capacitive sensing acquisition only requires few external components to
operate. This acquisition is managed directly by the GPIOs, timers and analog I/O groups
(see Section 3.15: System configuration controller and routing interface).
Reliable touch sensing functionality can be quickly and easily implemented using the free
STM32L1xx STMTouch touch sensing firmware library.
3.17
Timers and watchdogs
The ultra-low-power STM32L151xD and STM32L152xD devices include seven generalpurpose timers, two basic timers, and two watchdog timers.
Table 6 compares the features of the general-purpose and basic timers.
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Table 6. Timer feature comparison
DMA
Capture/compare Complementary
request
channels
outputs
generation
Timer
Counter
resolution
Counter type
Prescaler factor
TIM2,
TIM3,
TIM4
16-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM5
32-bit
Up, down,
up/down
Any integer between
1 and 65536
Yes
4
No
TIM9
16-bit
Up, down,
up/down
Any integer between
1 and 65536
No
2
No
TIM10,
TIM11
16-bit
Up
Any integer between
1 and 65536
No
1
No
TIM6,
TIM7
16-bit
Up
Any integer between
1 and 65536
Yes
0
No
3.17.1
General-purpose timers (TIM2, TIM3, TIM4, TIM5, TIM9, TIM10 and
TIM11)
There are seven synchronizable general-purpose timers embedded in the STM32L151xD
and STM32L152xD devices (see Table 6 for differences).
TIM2, TIM3, TIM4, TIM5
TIM2, TIM3, TIM4 are based on 16-bit auto-reload up/down counter. TIM5 is based on a 32bit auto-reload up/down counter. They include a 16-bit prescaler. They feature four
independent channels each for input capture/output compare, PWM or one-pulse mode
output. This gives up to 16 input captures/output compares/PWMs on the largest packages.
TIM2, TIM3, TIM4, TIM5 general-purpose timers can work together or with the TIM10,
TIM11 and TIM9 general-purpose timers via the Timer Link feature for synchronization or
event chaining. Their counter can be frozen in debug mode. Any of the general-purpose
timers can be used to generate PWM outputs.
TIM2, TIM3, TIM4, TIM5 all have independent DMA request generation.
These timers are capable of handling quadrature (incremental) encoder signals and the
digital outputs from 1 to 3 hall-effect sensors.
TIM10, TIM11 and TIM9
TIM10 and TIM11 are based on a 16-bit auto-reload upcounter. TIM9 is based on a 16-bit
auto-reload up/down counter. They include a 16-bit prescaler. TIM10 and TIM11 feature one
independent channel, whereas TIM9 has two independent channels for input capture/output
compare, PWM or one-pulse mode output. They can be synchronized with the TIM2, TIM3,
TIM4, TIM5 full-featured general-purpose timers.
They can also be used as simple time bases and be clocked by the LSE clock source
(32.768 kHz) to provide time bases independent from the main CPU clock.
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3.17.2
STM32L151xD STM32L152xD
Basic timers (TIM6 and TIM7)
These timers are mainly used for DAC trigger generation. They can also be used as generic
16-bit time bases.
3.17.3
SysTick timer
This timer is dedicated to the OS, but could also be used as a standard downcounter. It is
based on a 24-bit downcounter with autoreload capability and a programmable clock
source. It features a maskable system interrupt generation when the counter reaches 0.
3.17.4
Independent watchdog (IWDG)
The independent watchdog is based on a 12-bit downcounter and 8-bit prescaler. It is
clocked from an independent 37 kHz internal RC and, as it operates independently of the
main clock, it can operate in Stop and Standby modes. It can be used either as a watchdog
to reset the device when a problem occurs, or as a free-running timer for application timeout
management. It is hardware- or software-configurable through the option bytes. The counter
can be frozen in debug mode.
3.17.5
Window watchdog (WWDG)
The window watchdog is based on a 7-bit downcounter that can be set as free-running. It
can be used as a watchdog to reset the device when a problem occurs. It is clocked from
the main clock. It has an early warning interrupt capability and the counter can be frozen in
debug mode.
3.18
Communication interfaces
3.18.1
I²C bus
Up to two I²C bus interfaces can operate in multimaster and slave modes. They can support
standard and fast modes.
They support dual slave addressing (7-bit only) and both 7- and 10-bit addressing in master
mode. A hardware CRC generation/verification is embedded.
They can be served by DMA and they support SM Bus 2.0/PM Bus.
3.18.2
Universal synchronous/asynchronous receiver transmitter (USART)
The three USART and two UART interfaces are able to communicate at speeds of up to 4
Mbit/s. They support IrDA SIR ENDEC and have LIN Master/Slave capability. The three
USARTs provide hardware management of the CTS and RTS signals and are ISO 7816
compliant.
All USART/UART interfaces can be served by the DMA controller.
3.18.3
Serial peripheral interface (SPI)
Up to three SPIs are able to communicate at up to 16 Mbits/s in slave and master modes in
full-duplex and half-duplex communication modes. The 3-bit prescaler gives 8 master mode
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frequencies and the frame is configurable to 8 bits or 16 bits. The hardware CRC
generation/verification supports basic SD Card/MMC modes.
The SPIs can be served by the DMA controller.
3.18.4
Inter-integrated sound (I2S)
Two standard I2S interfaces (multiplexed with SPI2 and SPI3) are available. They can
operate in master or slave mode, and can be configured to operate with a 16-/32-bit
resolution as input or output channels. Audio sampling frequencies from 8 kHz up to 192
kHz are supported. When either or both of the I2S interfaces is/are configured in master
mode, the master clock can be output to the external DAC/CODEC at 256 times the
sampling frequency.
The I2Ss can be served by the DMA controller.
3.18.5
SDIO
An SD/SDIO/MMC host interface is available, that supports MultiMediaCard System
Specification Version 4.2 in three different databus modes: 1-bit (default), 4-bit and 8-bit.
The interface allows data transfer at up to 24 MHz in 8-bit mode, and is compliant with the
SD Memory Card Specification Version 2.0.
The SDIO Card Specification Version 2.0 is also supported with two different databus
modes: 1-bit (default) and 4-bit.
The current version supports only one SD/SDIO/MMC4.2 card at any one time and a stack
of MMC4.1 or previous.
In addition to SD/SDIO/MMC, this interface is fully compliant with the CE-ATA digital
protocol Rev1.1.
3.18.6
Universal serial bus (USB)
The STM32L151xD and STM32L152xD devices embed a USB device peripheral
compatible with the USB full-speed 12 Mbit/s. The USB interface implements a full-speed
(12 Mbit/s) function interface. It has software-configurable endpoint setting and supports
suspend/resume. The dedicated 48 MHz clock is generated from the internal main PLL (the
clock source must use a HSE crystal oscillator).
3.19
CRC (cyclic redundancy check) calculation unit
The CRC (cyclic redundancy check) calculation unit is used to get a CRC code from a 32-bit
data word and a fixed generator polynomial.
Among other applications, CRC-based techniques are used to verify data transmission or
storage integrity. In the scope of the EN/IEC 60335-1 standard, they offer a means of
verifying the Flash memory integrity. The CRC calculation unit helps compute a signature of
the software during runtime, to be compared with a reference signature generated at linktime and stored at a given memory location.
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STM32L151xD STM32L152xD
3.20
Development support
3.20.1
Serial wire JTAG debug port (SWJ-DP)
The ARM SWJ-DP interface is embedded, and is a combined JTAG and serial wire debug
port that enables either a serial wire debug or a JTAG probe to be connected to the target.
The JTAG JTMS and JTCK pins are shared with SWDAT and SWCLK, respectively, and a
specific sequence on the JTMS pin is used to switch between JTAG-DP and SW-DP.
The JTAG port can be permanently disabled with a JTAG fuse.
3.20.2
Embedded Trace Macrocell™
The ARM® Embedded Trace Macrocell provides a greater visibility of the instruction and
data flow inside the CPU core by streaming compressed data at a very high rate from the
STM32L151xD and STM32L152xD device through a small number of ETM pins to an
external hardware trace port analyzer (TPA) device. The TPA is connected to a host
computer using USB, Ethernet, or any other high-speed channel. Real-time instruction and
data flow activity can be recorded and then formatted for display on the host computer
running debugger software. TPA hardware is commercially available from common
development tool vendors. It operates with third party debugger software tools.
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Pin descriptions
Pin descriptions
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Pin descriptions
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Figure 4. STM32L15xQD UFBGA132 ballout
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Pin descriptions
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Pin descriptions
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Pin descriptions
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Pin descriptions
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Table 7. Legend/abbreviations used in the pinout table
Name
Abbreviation
Definition
Unless otherwise specified in brackets below the pin name, the pin function
during and after reset is the same as the actual pin name
Pin name
S
Supply pin
I
Input only pin
I/O
Input / output pin
FT
5 V tolerant I/O
TC
Standard 3.3 V I/O
B
Dedicated BOOT0 pin
RST
Bidirectional reset pin with embedded weak pull-up resistor
Pin type
I/O structure
Unless otherwise specified by a note, all I/Os are set as floating inputs during
and after reset
Notes
Alternate
Functions selected through GPIOx_AFR registers
functions
Pin
functions
Additional
Functions directly selected/enabled through peripheral registers
functions
Table 8. STM32L151xD and STM32L152xD pin definitions
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP64
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after reset)
1
B2
1
-
-
PE2
I/O
FT
PE2
TIM3_ETR/LCD_SEG38/
TRACECLK/FSMC_A23
-
2
A1
2
-
-
PE3
I/O
FT
PE3
TIM3_CH1/LCD_SEG39/
TRACED0/FSMC_A19
-
3
B1
3
-
-
PE4
I/O
FT
PE4
TIM3_CH2/TRACED1
/FSMC_A20
-
4
C2
4
-
-
PE5
I/O
FT
PE5
TIM9_CH1/TRACED2
/FSMC_A21
-
5
D2
5
-
-
PE6WKUP3
I/O
FT
PE6
TIM9_CH2/TRACED3
WKUP3/
RTC_TAMP3
6
E2
6
1
C6
VLCD(3)
S
-
VLCD
-
-
40/154
Pin name
DocID022027 Rev 10
Alternate functions
Additional
functions
STM32L151xD STM32L152xD
Pin descriptions
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
I / O structure
Pin name
Pin Type(1)
WLCSP64
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
Pins
Main
function(2)
(after reset)
Alternate functions
Additional
functions
I/O
FT
PC13
-
WKUP2/
RTC_TAMP1/
RTC_TS/
RTC_OUT
B8
PC14I/O
OSC32_IN(4)
TC
PC14
-
OSC32_IN
4
B7
PC15I/O
OSC32_OUT
TC
PC15
-
OSC32_OUT
-
-
-
PF0
I/O
FT
PF0
FSMC_A0
-
D5
-
-
-
PF1
I/O
FT
PF1
FSMC_A1
-
12
D4
-
-
-
PF2
I/O
FT
PF2
FSMC_A2
-
13
E4
-
-
-
PF3
I/O
FT
PF3
FSMC_A3
-
14
F3
-
-
-
PF4
I/O
FT
PF4
FSMC_A4
-
15
F4
-
-
-
PF5
I/O
FT
PF5
FSMC_A5
-
16
F2
10
-
-
VSS_5
S
-
VSS_5
-
-
17
G2
11
-
-
VDD_5
S
-
VDD_5
-
-
18
G3
-
-
-
PF6
I/O
FT
PF6
TIM5_CH1/TIM5_ETR
ADC_IN27
19
G4
-
-
-
PF7
I/O
FT
PF7
TIM5_CH2
ADC_IN28/
COMP1_INP
20
H4
-
-
-
PF8
I/O
FT
PF8
TIM5_CH3
ADC_IN29/
COMP1_INP
21
J6
-
-
-
PF9
I/O
FT
PF9
TIM5_CH4
ADC_IN30/
COMP1_INP
22
-
-
-
-
PF10
I/O
FT
PF10
-
ADC_IN31/
COMP1_INP
23
F1
12
5
D8
PH0OSC_IN(5)
I/O
TC
PH0
-
OSC_IN
24
G1
13
6
D7
PH1I/O
OSC_OUT(5)
TC
PH1
-
OSC_OUT
25
H2
14
7
C7
NRST
NRST
-
-
26
H1
15
8
E8
PC0
PC0
LCD_SEG18
ADC_IN10/
COMP1_INP
7
C1
7
2
C8
8
D1
8
3
9
E1
9
10
D6
11
PC13WKUP2
I/O RST
I/O
FT
DocID022027 Rev 10
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58
Pin descriptions
STM32L151xD STM32L152xD
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP64
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after reset)
27
J2
16
9
F8
PC1
I/O
FT
PC1
LCD_SEG19
ADC_IN11/
COMP1_INP
OPAMP3_VINP
28
-
17
10 D6
PC2
I/O
FT
PC2
LCD_SEG20
ADC_IN12/
COMP1_INP
OPAMP3_VINM
-
J3
-
-
-
PC2
I/O
FT
PC2
LCD_SEG20
ADC_IN12/
COMP1_INP
-
K1
-
-
-
OPAMP3_VI
NM
I
-
OPAMP3
_VINM
-
-
29
K2
18
11 F7
PC3
I/O
TC
PC3
LCD_SEG21
ADC_IN13/
COMP1_INP/
OPAMP3_VOUT
30
J1
19
12 E7
VSSA
S
-
VSSA
-
-
31
-
20
-
-
VREF-
S
-
VREF-
-
-
32
L1
21
-
-
VREF+
S
-
VREF+
-
-
33
M1
22
VDDA
S
-
VDDA
-
WKUP1/
RTC_TAMP2/
ADC_IN0/
COMP1_INP
13 G8
Pin name
Alternate functions
Additional
functions
34
L2
23
14 F6 PA0-WKUP1 I/O
FT
PA0
TIM2_CH1_ETR/
TIM5_CH1/ USART2_CTS
35
M2
24
15 E6
PA1
I/O
FT
PA1
TIM2_CH2/TIM5_CH2/
USART2_RTS/
LCD_SEG0
ADC_IN1/
COMP1_INP/
OPAMP1_VINP
36
-
25
16 H8
PA2
I/O
FT
PA2
TIM2_CH3/TIM5_CH3/
TIM9_CH1/
USART2_TX/LCD_SEG1
ADC_IN2/
COMP1_INP/
OPAMP1_VINM
-
K3
-
-
-
PA2
I/O
FT
PA2
TIM2_CH3/TIM5_CH3/
TIM9_CH1/
USART2_TX/LCD_SEG1
ADC_IN2/
COMP1_INP
-
M3
-
-
-
OPAMP1_VI
NM
I
TC
OPAMP1_
VINM
-
-
37
L3
26
PA3
I/O
TC
PA3
TIM2_CH4/TIM5_CH4/
TIM9_CH2/
USART2_RX/LCD_SEG2
ADC_IN3/
COMP1_INP/
OPAMP1_VOUT
42/154
17 G7
DocID022027 Rev 10
STM32L151xD STM32L152xD
Pin descriptions
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
Pins
UFBGA132
LQFP100
LQFP64
Pin Type(1)
I / O structure
Main
function(2)
(after reset)
38
-
27
18 F5
VSS_4
S
-
VSS_4
-
-
39
-
28
19 G6
VDD_4
S
-
VDD_4
-
-
40
J4
29
20 H7
PA4
I/O
TC
PA4
SPI1_NSS/SPI3_NSS/
I2S3_WS/USART2_CK
ADC_IN4/
DAC_OUT1/
COMP1_INP
41
K4
30
21 E5
PA5
I/O
TC
PA5
TIM2_CH1_ETR/
SPI1_SCK
ADC_IN5/
DAC_OUT2/
COMP1_INP
42
L4
31
22 G5
PA6
I/O
FT
PA6
TIM3_CH1/TIM10_CH1/
SPI1_MISO/
LCD_SEG3
ADC_IN6/
COMP1_INP/
OPAMP2_VINP
43
-
32
23 G4
PA7
I/O
FT
PA7
TIM3_CH2/TIM11_CH1/
SPI1_MOSI/
LCD_SEG4
ADC_IN7/
COMP1_INP/
OPAMP2_VINM
-
J5
-
-
-
PA7
I/O
FT
PA7
TIM3_CH2/TIM11_CH1/
SPI1_MOSI/
LCD_SEG4
ADC_IN7/
COMP1_INP
-
M4
-
-
-
OPAMP2_VI
NM
I
TC
OPAMP2_V
INM
-
-
44
K5
33
24 H6
PC4
I/O
FT
PC4
LCD_SEG22
ADC_IN14/
COMP1_INP
45
L5
34
25 H5
PC5
I/O
FT
PC5
LCD_SEG23
ADC_IN15/
COMP1_INP
WLCSP64
LQFP144
Pin functions
Pin name
Alternate functions
Additional
functions
46
M5
35
26 H4
PB0
I/O
TC
PB0
TIM3_CH3/LCD_SEG5
ADC_IN8/
COMP1_INP/
OPAMP2_VOUT/
VREF_OUT
47
M6
36
27 F4
PB1
I/O
FT
PB1
TIM3_CH4/LCD_SEG6
ADC_IN9/
COMP1_INP/
VREF_OUT
48
L6
37
28 H3
PB2
I/O
FT
PB2/
BOOT1
BOOT1
ADC_IN0b
49
K6
-
-
-
PF11
I/O
FT
PF11
-
ADC_IN1b
50
J7
-
-
-
PF12
I/O
FT
PF12
FSMC_A6
ADC_IN2b
51
E3
-
-
-
VSS_6
S
-
VSS_6
-
-
DocID022027 Rev 10
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58
Pin descriptions
STM32L151xD STM32L152xD
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP64
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after reset)
52
H3
-
-
-
VDD_6
S
-
VDD_6
-
-
53
K7
-
-
-
PF13
I/O
FT
PF13
FSMC_A7
ADC_IN3b
54
J8
-
-
-
PF14
I/O
FT
PF14
FSMC_A8
ADC_IN6b
55
J9
-
-
-
PF15
I/O
FT
PF15
FSMC_A9
ADC_IN7b
56
H9
-
-
-
PG0
I/O
FT
PG0
FSMC_A10
ADC_IN8b
57
G9
-
-
-
PG1
I/O
FT
PG1
FSMC_A11
ADC_IN9b
58
M7
38
-
-
PE7
I/O
TC
PE7
FSMC_D4
ADC_IN22/
COMP1_INP
59
L7
39
-
-
PE8
I/O
TC
PE8
FSMC_D5
ADC_IN23/
COMP1_INP
60
M8
40
-
-
PE9
I/O
TC
PE9
TIM2_CH1_ETR /FSMC_D6
ADC_IN24/
COMP1_INP
61
-
-
-
-
VSS_7
S
-
VSS_7
-
-
62
-
-
-
-
VDD_7
S
-
VDD_7
-
-
63
L8
41
-
-
PE10
I/O
TC
PE10
TIM2_CH2/FSMC_D7
ADC_IN25/
COMP1_INP
64
M9
42
-
-
PE11
I/O
FT
PE11
TIM2_CH3/FSMC_D8
-
65
L9
43
-
-
PE12
I/O
FT
PE12
TIM2_CH4/SPI1_NSS
/FSMC_D9
-
66
M10 44
-
-
PE13
I/O
FT
PE13
SPI1_SCK/FSMC_D10
-
67
M11
45
-
-
PE14
I/O
FT
PE14
SPI1_MISO/FSMC_D11
-
68
M12 46
-
-
PE15
I/O
FT
PE15
SPI1_MOSI/FSMC_D12
-
69
L10
47
29 G3
PB10
I/O
FT
PB10
TIM2_CH3/I2C2_SCL/
USART3_TX/
LCD_SEG10
-
70
L11
48
30 F3
PB11
I/O
FT
PB11
TIM2_CH4/ I2C2_SDA/
USART3_RX/ LCD_SEG11
-
71
F12
49
31 H2
VSS_1
S
-
VSS_1
-
-
72
G12
50
32 H1
VDD_1
S
-
VDD_1
-
-
73
L12
51
33 G2
PB12
I/O
FT
PB12
TIM10_CH1/I2C2_SMBA/
SPI2_NSS/ I2S2_WS/
USART3_CK/ LCD_SEG12
ADC_IN18/
COMP1_INP
44/154
Pin name
DocID022027 Rev 10
Alternate functions
Additional
functions
STM32L151xD STM32L152xD
Pin descriptions
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
I / O structure
Pin name
Pin Type(1)
WLCSP64
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
Pins
Main
function(2)
(after reset)
Alternate functions
Additional
functions
ADC_IN19/
COMP1_INP
74
K12
52
34 G1
PB13
I/O
FT
PB13
TIM9_CH1/SPI2_SCK/
I2S2_CK/
USART3_CTS/
LCD_SEG13
75
K11
53
35 F2
PB14
I/O
FT
PB14
TIM9_CH2/SPI2_MISO/
USART3_RTS/
LCD_SEG14
ADC_IN20/
COMP1_INP
76
K10
54
36 F1
PB15
I/O
FT
PB15
TIM11_CH1/SPI2_MOSI/
I2S2_SD/
LCD_SEG15
ADC_IN21/
COMP1_INP/
RTC_REFIN
77
K9
55
-
-
PD8
I/O
FT
PD8
USART3_TX/LCD_SEG28/
FSMC_D13
-
78
K8
56
-
-
PD9
I/O
FT
PD9
USART3_RX/LCD_SEG29/
FSMC_D14
-
79
J12
57
-
-
PD10
I/O
FT
PD10
USART3_CK/LCD_SEG30/
FSMC_D15
-
80
J11
58
-
-
PD11
I/O
FT
PD11
USART3_CTS/LCD_SEG31
/FSMC_A16
-
81
J10
59
-
-
PD12
I/O
FT
PD12
TIM4_CH1/USART3_RTS/
LCD_SEG32/
FSMC_A17
-
82
H12
60
-
-
PD13
I/O
FT
PD13
TIM4_CH2/LCD_SEG33/
FSMC_A18
-
83
-
-
-
-
VSS_8
S
-
VSS_8
-
-
84
-
-
-
-
VDD_8
S
-
VDD_8
-
-
85
H11
61
-
-
PD14
I/O
FT
PD14
TIM4_CH3/LCD_SEG34/
FSMC_D0
-
86
H10
62
-
-
PD15
I/O
FT
PD15
TIM4_CH4/LCD_SEG35
/FSMC_D1
-
87
G10
-
-
-
PG2
I/O
FT
PG2
FSMC_A12
ADC_IN10b
88
F9
-
-
-
PG3
I/O
FT
PG3
FSMC_A13
ADC_IN11b
89
F10
-
-
-
PG4
I/O
FT
PG4
FSMC_A14
ADC_IN12b
90
E9
-
-
-
PG5
I/O
FT
PG5
FSMC_A15
-
91
-
-
-
-
PG6
I/O
FT
PG6
-
-
DocID022027 Rev 10
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58
Pin descriptions
STM32L151xD STM32L152xD
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP64
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after reset)
92
-
-
-
-
PG7
I/O
FT
PG7
-
-
93
-
-
-
-
PG8
I/O
FT
PG8
-
-
94
F6
-
-
-
VSS_9
S
VSS_9
-
-
95
G6
-
-
-
VDD_9
S
VDD_9
-
-
96
E12
63
37 E1
PC6
I/O
FT
PC6
TIM3_CH1/I2S2_MCK/
LCD_SEG24/SDIO_D6
-
97
E11
64
38 E2
PC7
I/O
FT
PC7
TIM3_CH2/I2S3_MCK/
LCD_SEG25/SDIO_D7
-
98
E10
65
39 E3
PC8
I/O
FT
PC8
TIM3_CH3/LCD_SEG26/
SDIO_D0
-
99
D12
66
40 D1
PC9
I/O
FT
PC9
TIM3_CH4/LCD_SEG27/
SDIO_D1
-
100 D11
67
41 E4
PA8
I/O
FT
PA8
USART1_CK/MCO/
LCD_COM0
-
101 D10
68
42 D2
PA9
I/O
FT
PA9
USART1_TX / LCD_COM1
-
102 C12
69
43 D3
PA10
I/O
FT
PA10
USART1_RX / LCD_COM2
-
103 B12
70
44 C1
PA11
I/O
FT
PA11
USART1_CTS/ SPI1_MISO
USB_DM
104 A12
71
45 C2
PA12
I/O
FT
PA12
USART1_RTS/ SPI1_MOSI
USB_DP
105 A11
72
46 D4
PA13
I/O
FT
JTMSSWDIO
JTMS-SWDIO
-
106 C11
73
PH2
I/O
FT
PH2
FSMC_A22
-
107 F11
74
47 B1
VSS_2
S
-
VSS_2
-
-
108 G11
75
48 A1
VDD_2
S
-
VDD_2
-
-
109 A10
76
49 B2
PA14
I/O
FT
JTCKSWCLK
JTCK-SWCLK
-
JTDI
TIM2_CH1_ETR/
SPI1_NSS/SPI3_NSS/
I2S3_WS/LCD_SEG17/
JTDI
-
110
46/154
A9
77
-
-
50 C3
Pin name
PA15
I/O
FT
DocID022027 Rev 10
Alternate functions
Additional
functions
STM32L151xD STM32L152xD
Pin descriptions
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
111 B11
112 C10
78
79
51 A2
52 B3
113 B10
80
114
C9
81
-
115
B9
82
-
PC10
PC11
I/O
I/O
I / O structure
Pin name
Pin Type(1)
WLCSP64
Pin functions
LQFP64
LQFP100
UFBGA132
LQFP144
Pins
FT
FT
Main
function(2)
(after reset)
Alternate functions
Additional
functions
PC10
SPI3_SCK/I2S3_CK/
USART3_TX/UART4_TX/
LCD_SEG28/LCD_SEG40/
LCD_COM4/
SDIO_D2
-
PC11
SPI3_MISO/USART3_RX/
UART4_RX/
LCD_SEG29/LCD_SEG41/
LCD_COM5/
SDIO_D3
-
-
PC12
I/O
FT
PC12
SPI3_MOSI/I2S3_SD/
USART3_CK/
UART5_TX/LCD_SEG30/
LCD_SEG42/
LCD_COM6/SDIO_CK
-
PD0
I/O
FT
PD0
TIM9_CH1/SPI2_NSS/
I2S2_WS/ FSMC_D2
-
-
PD1
I/O
FT
PD1
SPI2_SCK/I2S2_CK
/FSMC_D3
-
-
53 C4
PD2
I/O
FT
PD2
TIM3_ETR/
UART5_RX/LCD_SEG31/
LCD_SEG43/LCD_COM7/
SDIO_CMD
-
PD3
I/O
FT
PD3
SPI2_MISO/USART2_CTS/
FSMC_CLK
-
-
-
PD4
I/O
FT
PD4
SPI2_MOSI/I2S2_SD/
USART2_RTS/
FSMC_NOE
-
86
-
-
PD5
I/O
FT
PD5
USART2_TX/FSMC_NWE
-
F7
-
-
-
VSS_10
S
-
VSS_10
-
-
121
G7
-
-
-
VDD_10
S
-
VDD_10
-
-
122
B6
87
-
-
PD6
I/O
FT
PD6
USART2_RX
/FSMC_NWAIT
-
123
A5
88
-
-
PD7
I/O
FT
PD7
TIM9_CH2/USART2_CK
/FSMC_NE1
-
124
D9
-
-
-
PG9
I/O
FT
PG9
FSMC_NE2
-
116
C8
83
54 A3
117
B8
84
-
118
B7
85
119
A6
120
DocID022027 Rev 10
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58
Pin descriptions
STM32L151xD STM32L152xD
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
Pins
LQFP144
UFBGA132
LQFP100
LQFP64
WLCSP64
Pin Type(1)
I / O structure
Pin functions
Main
function(2)
(after reset)
125
D8
-
-
-
PG10
I/O
FT
PG10
FSMC_NE3
-
126
-
-
-
-
PG11
I/O
FT
PG11
-
-
127
D7
-
-
-
PG12
I/O
FT
PG12
FSMC_NE4
-
128
C7
-
-
-
PG13
I/O
FT
PG13
FSMC_A24
-
129
C6
-
-
-
PG14
I/O
FT
PG14
FSMC_A25
-
130
-
-
-
-
VSS_11
S
-
VSS_11
-
-
131
-
-
-
-
VDD_11
S
-
VDD_11
-
-
132
-
-
-
-
PG15
I/O
FT
PG15
-
-
133
A8
89
55 A4
PB3
I/O
FT
JTDO
TIM2_CH2/SPI1_SCK/
SPI3_SCK/ I2S3_CK/
LCD_SEG7/JTDO
COMP2_INM
134
A7
90
56 B4
PB4
I/O
FT
NJTRST
TIM3_CH1/SPI1_MISO/
SPI3_MISO/
LCD_SEG8/NJTRST
COMP2_INP
COMP2_INP
Pin name
Alternate functions
Additional
functions
135
C5
91
57 A5
PB5
I/O
FT
PB5
TIM3_CH2/I2C1_SMBA/
SPI1_MOSI/
SPI3_MOSI/
I2S3_SD/LCD_SEG9
136
B5
92
58 B5
PB6
I/O
FT
PB6
TIM4_CH1/I2C1_SCL/
USART1_TX/
COMP2_INP
137
B4
93
59 C5
PB7
I/O
FT
PB7
TIM4_CH2/I2C1_SDA/
USART1_RX/FSMC_NADV
COMP2_INP/
PVD_IN
138
A4
94
60 A6
BOOT0
I
B
BOOT0
-
-
139
A3
95
61 D5
PB8
I/O
FT
PB8
TIM4_CH3/TIM10_CH1/
I2C1_SCL/
LCD_SEG16/SDIO_D4
-
140
B3
96
62 B6
PB9
I/O
FT
PB9
TIM4_CH4/
TIM11_CH1/I2C1_SDA/
LCD_COM3/ SDIO_D5
-
141
C3
97
-
-
PE0
I/O
FT
PE0
TIM4_ETR/TIM10_CH1/
LCD_SEG36/FSMC_NBL0
-
142
A2
98
-
-
PE1
I/O
FT
PE1
TIM11_CH1/LCD_SEG37
/FSMC_NBL1
-
48/154
DocID022027 Rev 10
STM32L151xD STM32L152xD
Pin descriptions
Table 8. STM32L151xD and STM32L152xD pin definitions (continued)
Pins
UFBGA132
LQFP100
LQFP64
Pin Type(1)
I / O structure
Main
function(2)
(after reset)
143
D3
99
63 A7
VSS_3
S
-
VSS_3
-
-
144
C4
100 64 A8
VDD_3
S
-
VDD_3
-
-
WLCSP64
LQFP144
Pin functions
Pin name
Alternate functions
Additional
functions
1. I = input, O = output, S = supply.
2. Function availability depends on the chosen device.
3. Applicable to STM32L152xD devices only. In STM32L151xD devices, this pin should be connected to VDD.
4. The PC14 and PC15 I/Os are only configured as OSC32_IN/OSC32_OUT when the LSE oscillator is ON (by setting the
LSEON bit in the RCC_CSR register). The LSE oscillator pins OSC32_IN/OSC32_OUT can be used as general-purpose
PH0/PH1 I/Os, respectively, when the LSE oscillator is off (after reset, the LSE oscillator is off). The LSE has priority over
the GPIO function. For more details, refer to Using the OSC32_IN/OSC32_OUT pins as GPIO PC14/PC15 port pins
section in the STM32L151xx, STM32L152xx and STM32L162xx reference manual (RM0038).
5. The PH0 and PH1 I/Os are only configured as OSC_IN/OSC_OUT when the HSE oscillator is ON (by setting the HSEON
bit in the RCC_CR register). The HSE oscillator pins OSC_IN/OSC_OUT can be used as general-purpose PH0/PH1 I/Os,
respectively, when the HSE oscillator is off ( after reset, the HSE oscillator is off ). The HSE has priority over the GPIO
function.
DocID022027 Rev 10
49/154
58
Table 9. Alternate function input/output
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
SYSTEM
Alternate function
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
USART1/2/3 UART4/5
LCD
FSMC/
SDIO
CPRI
BOOT0
BOOT0
-
-
-
-
-
-
-
-
-
-
-
NRST
NRST
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
DocID022027 Rev 10
-
TIM2_CH1_ETR TIM5_CH1
-
-
-
-
USART2_CTS
-
-
-
TIMx_IC1
PA1
-
TIM2_CH2
TIM5_CH2
-
-
-
-
USART2_RTS
-
SEG0
-
TIMx_IC2
EVENT
OUT
PA2
-
TIM2_CH3
TIM5_CH3 TIM9_CH1
-
-
-
USART2_TX
-
SEG1
-
TIMx_IC3
EVENT
OUT
PA3
-
TIM2_CH4
TIM5_CH4 TIM9_CH2
-
-
-
USART2_RX
-
SEG2
-
TIMx_IC4
EVENT
OUT
PA4
-
-
-
-
-
SPI1_NSS
SPI3_NSS
USART2_CK
I2S3_WS
-
-
-
TIMx_IC1
EVENT
OUT
PA5
-
TIM2_CH1_ETR
-
-
-
SPI1_SCK
-
-
-
-
-
TIMx_IC2
EVENT
OUT
PA6
-
-
TIM3_CH1 TIM10_ CH1
-
SPI1_MISO
-
-
-
SEG3
-
TIMx_IC3
EVENT
OUT
PA7
-
-
TIM3_CH2 TIM11_ CH1
-
SPI1_MOSI
-
-
-
SEG4
-
TIMx_IC4
EVENT
OUT
MCO
-
-
-
-
-
-
USART1_CK
-
COM0
-
TIMx_IC1
EVENT
OUT
PA9
-
-
-
-
-
-
-
USART1_TX
-
COM1
-
TIMx_IC2
EVENT
OUT
PA10
-
-
-
-
-
-
-
USART1_RX
-
COM2
-
TIMx_IC3
EVENT
OUT
PA11
-
-
-
-
-
SPI1_MISO
USART1_CTS
-
-
-
TIMx_IC4
EVENT
OUT
STM32L151xD STM32L152xD
PA0-WKUP1
EVENT
OUT
PA8
Pin descriptions
50/154
Alternate functions
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PA12
-
-
-
-
-
SPI1_MOSI
-
PA13
JTMS-SWDIO
-
-
-
-
-
-
PA14
JTCK-SWCLK
-
-
-
-
-
PA15
JTDI
TIM2_CH1_ETR
-
-
-
SPI1_NSS
DocID022027 Rev 10
LCD
FSMC/
SDIO
-
-
-
TIMx_IC1
EVENT
OUT
-
-
-
-
TIMx_IC2
EVENT
OUT
-
-
-
-
-
TIMx_IC3
EVEN
TOUT
SPI3_NSS
I2S3_WS
-
-
SEG17
-
TIMx_IC4
EVEN
TOUT
-
-
SEG5
-
-
EVEN
TOUT
USART1/2/3 UART4/5
USART1_RTS
PB0
-
-
TIM3_CH3
-
-
-
PB1
-
-
TIM3_CH4
-
-
-
-
-
-
SEG6
-
-
EVENT
OUT
PB2
BOOT1
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
PB3
JTDO
-
-
-
SPI1_SCK
SPI3_SCK
I2S3_CK
-
-
SEG7
-
-
EVENT
OUT
PB4
NJTRST
-
TIM3_CH1
-
-
SPI1_MISO SPI3_MISO
-
-
SEG8
-
-
EVENT
OUT
SPI1_MOSI
SPI3_MOSI
I2S3_SD
-
-
SEG9
-
-
EVENT
OUT
TIM2_CH2
-
-
TIM3_CH2
-
I2C1_
SMBA
PB6
-
-
TIM4_CH1
-
I2C1_SCL
-
-
USART1_TX
-
-
-
-
EVENT
OUT
PB7
-
-
TIM4_CH2
-
I2C1_SDA
-
-
USART1_RX
-
-
NADV
-
EVENT
OUT
PB8
-
-
TIM4_CH3 TIM10_CH1 I2C1_SCL
-
-
-
-
SEG16
SDIO_D4
-
EVENT
OUT
PB9
-
-
TIM4_CH4 TIM11_CH1 I2C1_SDA
-
-
-
-
COM3
SDIO_D5
-
EVENT
OUT
PB10
-
-
-
-
SEG10
-
-
EVENT
OUT
TIM2_CH3
-
-
I2C2_SCL
USART3_TX
Pin descriptions
51/154
PB5
STM32L151xD STM32L152xD
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
FSMC/
SDIO
CPRI
SYSTEM
Alternate function
SYSTEM
TIM2
TIM2_CH4
TIM3/4/5
TIM9/
10/11
-
-
I2C1/2
I2C2_SDA
SPI1/2
SPI3
USART1/2/3 UART4/5
LCD
-
-
USART3_RX
-
SEG11
-
-
EVENT
OUT
DocID022027 Rev 10
-
PB12
-
-
-
TIM10_CH1 I2C2_SMBA
SPI2_NSS
I2S2_WS
-
USART3_CK
-
SEG12
-
-
EVENT
OUT
PB13
-
-
-
TIM9_CH1
-
SPI2_SCK
I2S2_CK
-
USART3_CTS
-
SEG13
-
-
EVENT
OUT
PB14
-
-
-
TIM9_CH2
-
SPI2_MISO
-
USART3_RTS
-
SEG14
-
-
EVENT
OUT
PB15
-
-
-
TIM11_CH1
-
SPI2_MOSI
I2S2_SD
-
-
-
SEG15
-
-
EVENT
OUT
PC0
-
-
-
-
-
-
-
-
SEG18
-
TIMx_IC1
EVENT
OUT
PC1
-
-
-
-
-
-
-
-
-
SEG19
-
TIMx_IC2
EVENT
OUT
PC2
-
-
-
-
-
-
-
-
-
SEG20
-
TIMx_IC3
EVENT
OUT
PC3
-
-
-
-
-
-
-
-
-
SEG21
-
TIMx_IC4
EVENT
OUT
PC4
-
-
-
-
-
-
-
-
-
SEG22
-
TIMx_IC1
EVENT
OUT
PC5
-
-
-
-
-
-
-
-
-
SEG23
-
TIMx_IC2
EVENT
OUT
PC6
-
-
TIM3_CH1
-
-
-
-
-
SEG24
SDIO_D6
TIMx_IC3
EVENT
OUT
PC7
-
-
TIM3_CH2
-
-
-
I2S3_MCK
-
-
SEG25
SDIO_D7
TIMx_IC4
EVENT
OUT
PC8
-
-
TIM3_CH3
-
-
-
-
-
-
SEG26
SDIO_D0
TIMx_IC1
EVENT
OUT
PC9
-
-
TIM3_CH4
-
-
-
-
-
-
SEG27
SDIO_D1
TIMx_IC2
EVENT
OUT
I2S2_MCK
STM32L151xD STM32L152xD
PB11
Pin descriptions
52/154
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
DocID022027 Rev 10
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
PC10
-
-
-
-
-
-
SPI3_SCK
USART3_TX
I2S3_CK
UART4_TX
COM4/
SEG28/
SEG40
SDIO_D2
TIMx_IC3
EVENT
OUT
PC11
-
-
-
-
-
-
SPI3_MISO USART3_RX
UART4_RX
COM5/
SEG29
/SEG41
SDIO_D3
TIMx_IC4
EVENT
OUT
PC12
-
-
-
-
-
-
SPI3_MOSI
USART3_CK
I2S3_SD
UART5_TX
COM6/
SEG30/
SEG42
SDIO_CK
TIMx_IC1
EVENT
OUT
PC13-WKUP2
-
-
-
-
-
-
-
-
-
-
-
TIMx_IC2
EVENT
OUT
PC14 OSC32_IN
-
-
-
-
-
-
-
-
-
-
-
TIMx_IC3
EVENT
OUT
PC15 OSC32_OUT
-
-
-
-
-
-
-
-
-
-
-
TIMx_IC4
EVENT
OUT
PD0
-
-
-
PD1
-
-
-
PD2
-
-
PD3
-
PD4
SPI3
USART1/2/3 UART4/5
LCD
FSMC/
SDIO
SPI2_NSS
I2S2_WS
-
-
-
-
D2 /DA2
TIMx_IC1
EVENT
OUT
-
-
SPI2 SCK
I2S2_CK
-
-
-
-
D3 /DA3
TIMx_IC2
EVENT
OUT
TIM3_ETR
-
-
-
-
-
UART5_RX
SDIO_
CMD
TIMx_IC3
EVENT
OUT
-
-
-
-
SPI2_MISO -
USART2_CTS
-
-
CLK
TIMx_IC4
EVENT
OUT
-
-
-
-
-
SPI2_MOSI
I2S2_SD
USART2_RTS
-
-
NOE
TIMx_IC1
EVENT
OUT
PD5
-
-
-
-
-
-
-
USART2_TX
-
-
NWE
TIMx_IC2
EVENT
OUT
PD6
-
-
-
-
-
-
-
USART2_RX
-
-
NWAIT
TIMx_IC3
EVENT
OUT
PD7
-
-
-
-
-
-
USART2_CK
-
-
NE1
TIMx_IC4
EVENT
OUT
TIM9_CH2
COM7/
SEG31/
SEG43
Pin descriptions
53/154
-
TIM9_CH1
STM32L151xD STM32L152xD
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
DocID022027 Rev 10
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PD8
-
-
-
-
-
-
-
USART3_TX
-
SEG28
D13/DA13
TIMx_IC1
EVENT
OUT
PD9
-
-
-
-
-
-
-
USART3_RX
-
SEG29
D14/DA14
TIMx_IC2
EVENT
OUT
PD10
-
-
-
-
-
-
-
USART3_CK
-
SEG30
D15/DA15
TIMx_IC3
EVENT
OUT
PD11
-
-
-
-
-
-
-
USART3_CTS
-
SEG31
A16
TIMx_IC4
EVENT
OUT
PD12
-
-
TIM4_CH1
-
-
-
-
USART3_RTS
-
SEG32
A17
TIMx_IC1
EVENT
OUT
PD13
-
-
TIM4_CH2
-
-
-
-
-
-
SEG33
A18
TIMx_IC2
EVENT
OUT
PD14
-
-
TIM4_CH3
-
-
-
-
-
-
SEG34
D0/DA0
TIMx_IC3
EVENT
OUT
PD15
-
-
TIM4_CH4
-
-
-
-
-
-
SEG35
D1/DA1
TIMx_IC4
EVENT
OUT
PE0
-
-
TIM4_ETR TIM10_CH1
-
-
-
-
-
SEG36
NBL0
TIMx_IC1
EVENT
OUT
PE1
-
-
-
TIM11_CH1
-
-
-
-
-
SEG37
NBL1
TIMx_IC2
EVENT
OUT
USART1/2/3 UART4/5
LCD
FSMC/
SDIO
PE2
TRACECK
-
TIM3_ETR
-
-
-
-
-
-
SEG 38
A23
TIMx_IC3
EVENT
OUT
PE3
TRACED0
-
TIM3_CH1
-
-
-
-
-
-
SEG 39
A19
TIMx_IC4
EVENT
OUT
PE4
TRACED1
-
TIM3_CH2
-
-
-
-
-
-
-
A20
TIMx_IC1
EVENT
OUT
PE5
TRACED2
-
-
TIM9_CH1
-
-
-
-
-
-
A21
TIMx_IC2
EVENT
OUT
PE6-WKUP3
TRACED3
-
-
TIM9_CH2
-
-
-
-
-
-
TIMx_IC3
EVENT
OUT
-
STM32L151xD STM32L152xD
SYSTEM
Pin descriptions
54/154
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
DocID022027 Rev 10
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PE7
-
-
-
-
-
-
-
-
-
-
D4/DA4
TIMx_IC4
EVENT
OUT
PE8
-
-
-
-
-
-
-
-
-
-
D5/DA5
TIMx_IC1
EVENT
OUT
PE9
-
TIM2_CH1_ETR
-
-
-
-
-
-
-
-
D6/DA6
TIMx_IC2
EVENT
OUT
PE10
-
TIM2_CH2
-
-
-
-
-
-
-
-
D7/DA7
TIMx_IC3
EVENT
OUT
PE11
-
TIM2_CH3
-
-
-
-
-
-
-
-
D8/DA8
TIMx_IC4
EVENT
OUT
PE12
-
TIM2_CH4
-
-
-
SPI1_NSS
-
-
-
-
D9/DA9
TIMx_IC1
EVENT
OUT
PE13
-
-
-
-
-
SPI1_SCK
-
-
-
-
D10/DA10
TIMx_IC2
EVENT
OUT
PE14
-
-
-
-
-
SPI1_MISO
-
-
-
-
D11/DA11
TIMx_IC3
EVENT
OUT
PE15
-
-
-
-
-
SPI1_MOSI
-
-
-
-
D12/DA12
TIMx_IC4
EVENT
OUT
PF0
-
-
-
-
-
-
-
-
-
-
A0
-
EVENT
OUT
PF1
-
-
-
-
-
-
-
-
-
-
A1
-
EVENT
OUT
PF2
-
-
-
-
-
-
-
-
-
-
A2
-
EVENT
OUT
PF3
-
-
-
-
-
-
-
-
-
-
A3
-
EVENT
OUT
PF4
-
-
-
-
-
-
-
-
-
-
A4
-
EVENT
OUT
PF5
-
-
-
-
-
-
-
-
-
-
A5
-
EVENT
OUT
USART1/2/3 UART4/5
LCD
FSMC/
SDIO
Pin descriptions
55/154
SYSTEM
STM32L151xD STM32L152xD
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
SYSTEM
Alternate function
DocID022027 Rev 10
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PF6
-
-
TIM5_ETR
-
-
-
-
-
PF7
-
-
TIM5_CH2
-
-
-
-
PF8
-
-
TIM5_CH3
-
-
-
PF9
-
-
TIM5_CH4
-
-
PF10
-
-
-
-
PF11
-
-
-
PF12
-
-
PF13
-
PF14
FSMC/
SDIO
CPRI
-
-
-
-
EVENT
OUT
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
A6
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
A7
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
A8
-
EVENT
OUT
PF15
-
-
-
-
-
-
-
-
-
-
A9
-
EVENT
OUT
PG0
-
-
-
-
-
-
-
-
-
-
A10
-
EVENT
OUT
PG1
-
-
-
-
-
-
-
-
-
-
A11
-
EVENT
OUT
PG2
-
-
-
-
-
-
-
-
-
-
A12
-
EVENT
OUT
PG3
-
-
-
-
-
-
-
-
-
-
A13
-
EVENT
OUT
PG4
-
-
-
-
-
-
-
-
-
-
A14
-
EVENT
OUT
STM32L151xD STM32L152xD
LCD
USART1/2/3 UART4/5
Pin descriptions
56/154
Table 9. Alternate function input/output (continued)
Digital alternate function number
AFIO0
AFIO1
AFIO2
AFIO3
AFIO4
AFIO5
Port name
AFIO6
AFIO7
AFIO8 .. AFIO11 AFIO12 ..
AFIO14
AFIO15
CPRI
SYSTEM
Alternate function
DocID022027 Rev 10
SYSTEM
TIM2
TIM3/4/5
TIM9/
10/11
I2C1/2
SPI1/2
SPI3
PG5
-
-
-
-
-
-
-
-
-
-
PG6
-
-
-
-
-
-
-
-
-
-
PG7
-
-
-
-
-
-
-
-
-
PG8
-
-
-
-
-
-
-
-
PG9
-
-
-
-
-
-
-
PG10
-
-
-
-
-
-
PG11
-
-
-
-
-
PG12
-
-
-
-
PG13
-
-
-
PG14
-
-
PG15
-
PH0OSC_IN
USART1/2/3 UART4/5
LCD
FSMC/
SDIO
EVENT
OUT
-
-
EVENT
OUT
-
-
-
EVENT
OUT
-
-
-
-
EVENT
OUT
-
-
-
NE2
-
EVENT
OUT
-
-
-
-
NE3
-
EVENT
OUT
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
NE4
-
EVENT
OUT
-
-
-
-
-
-
-
A24
-
EVENT
OUT
-
-
-
-
-
-
-
-
A25
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
EVENT
OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
PH1OSC_OUT
-
-
-
-
-
-
-
-
-
-
-
-
-
PH2
-
-
-
-
-
-
-
-
-
-
-
-
-
A22
57/154
Pin descriptions
-
A15
STM32L151xD STM32L152xD
Table 9. Alternate function input/output (continued)
Memory mapping
5
STM32L151xD STM32L152xD
Memory mapping
Figure 8. Memory map
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58/154
DocID022027 Rev 10
STM32L151xD STM32L152xD
Electrical characteristics
6
Electrical characteristics
6.1
Parameter conditions
Unless otherwise specified, all voltages are referenced to VSS.
6.1.1
Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA = 25 °C and TA = TAmax (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production. Based on
characterization, the minimum and maximum values refer to sample tests and represent the
mean value plus or minus three times the standard deviation (mean ±3σ).
6.1.2
Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3.6 V (for the
1.65 V ≤VDD ≤3.6 V voltage range). They are given only as design guidelines and are not
tested.
Typical ADC accuracy values are determined by characterization of a batch of samples from
a standard diffusion lot over the full temperature range, where 95% of the devices have an
error less than or equal to the value indicated (mean ±2σ).
6.1.3
Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
6.1.4
Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 9.
6.1.5
Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 10.
Figure 9. Pin loading conditions
Figure 10. Pin input voltage
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DocID022027 Rev 10
DLG
59/154
130
Electrical characteristics
6.1.6
STM32L151xD STM32L152xD
Power supply scheme
Figure 11. Power supply scheme
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069
DocID022027 Rev 10
STM32L151xD STM32L152xD
6.1.7
Electrical characteristics
Optional LCD power supply scheme
Figure 12. Optional LCD power supply scheme
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1. Option 1: LCD power supply is provided by a dedicated VLCD supply source, VSEL switch is open.
2. Option 2: LCD power supply is provided by the internal step-up converter, VSEL switch is closed, an
external capacitance is needed for correct behavior of this converter.
6.1.8
Current consumption measurement
Figure 13. Current consumption measurement scheme
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DocID022027 Rev 10
61/154
130
Electrical characteristics
6.2
STM32L151xD STM32L152xD
Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 10: Voltage characteristics,
Table 11: Current characteristics, and Table 12: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only and functional operation of
the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods may affect device reliability.
Table 10. Voltage characteristics
Symbol
VDD–VSS
VIN(2)
Ratings
Min
Max
–0.3
4.0
Input voltage on five-volt tolerant pin
VSS −0.3
VDD+4.0
Input voltage on any other pin
VSS − 0.3
4.0
External main supply voltage
(including VDDA and VDD)(1)
|ΔVDDx|
Variations between different VDD power pins
-
50
|VSSX − VSS|
Variations between all different ground pins
-
50
VREF+ –VDDA
Allowed voltage difference for VREF+ > VDDA
-
0.4
Electrostatic discharge voltage
(human body model)
see Section 6.3.12
VESD(HBM)
Unit
V
mV
V
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2.
VIN maximum must always be respected. Refer to Table 11 for maximum allowed injected current values.
Table 11. Current characteristics
Symbol
IVDD(Σ)
IVSS(Σ)
(2)
Ratings
Max.
Total current into sum of all VDD_x power lines (source)(1)
100
(sink)(1)
100
Total current out of sum of all VSS_x ground lines
IVDD(PIN)
Maximum current into each VDD_x power pin
(source)(1)
70
IVSS(PIN)
Maximum current out of each VSS_x ground pin (sink)(1)
-70
Output current sunk by any I/O and control pin
25
IIO
ΣIIO(PIN)
IINJ(PIN) (3)
ΣIINJ(PIN)
Output current sourced by any I/O and control pin
- 25
Total output current sunk by sum of all IOs and control pins
(2)
Total output current sourced by sum of all IOs and control pins(2)
Injected current on five-volt tolerant I/O(4), RST and B pins
Injected current on any other pin
(5)
Unit
mA
60
-60
-5/+0
±5
(6)
Total injected current (sum of all I/O and control pins)
± 25
1. All main power (VDD, VDDA) and ground (VSS, VSSA) pins must always be connected to the external power supply, in the
permitted range.
2. This current consumption must be correctly distributed over all I/Os and control pins. The total output current must not be
sunk/sourced between two consecutive power supply pins referring to high pin count LQFP packages.
3. Negative injection disturbs the analog performance of the device. See note in Section 6.3.19.
4. Positive current injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must never be
exceeded. Refer to Table 10 for maximum allowed input voltage values.
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STM32L151xD STM32L152xD
Electrical characteristics
5. A positive injection is induced by VIN > VDD while a negative injection is induced by VIN < VSS. IINJ(PIN) must never be
exceeded. Refer to Table 10: Voltage characteristics for the maximum allowed input voltage values.
6. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the positive and
negative injected currents (instantaneous values).
Table 12. Thermal characteristics
Symbol
TSTG
TJ
Ratings
Storage temperature range
Maximum junction temperature
6.3
Operating conditions
6.3.1
General operating conditions
Value
Unit
–65 to +150
°C
150
°C
Table 13. General operating conditions
Symbol
Parameter
Conditions
Min
Max
fHCLK
Internal AHB clock frequency
-
0
32
fPCLK1
Internal APB1 clock frequency
-
0
32
fPCLK2
Internal APB2 clock frequency
-
0
32
BOR detector disabled
1.65
3.6
BOR detector enabled, at
power on
1.8
3.6
BOR detector disabled, after
power on
1.65
3.6
1.65
3.6
1.8
3.6
FT pins; 2.0 V ≤VDD
-0.3
5.5(3)
FT pins; VDD < 2.0 V
-0.3
5.25(3)
0
5.5
-0.3
VDD+0.3
LQFP144 package
-
500
LQFP100 package
-
465
LQFP64 package
-
435
UFBGA132
-
333
-
435
–40
85
–40
105
VDD
(1)
VDDA
VIN
Standard operating voltage
Analog operating voltage
(ADC and DAC not used)
Analog operating voltage
(ADC or DAC used)
I/O input voltage
Must be the same voltage as
VDD(2)
BOOT0 pin
Any other pin
PD
Power dissipation at TA = 85 °C for
suffix 6 or TA = 105 °C for suffix 7(4)
WLCSP64 package
TA
Ambient temperature for 6 suffix version Maximum power
dissipation(5)
Ambient temperature for 7 suffix version Maximum power dissipation
DocID022027 Rev 10
Unit
MHz
V
V
V
mW
°C
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Electrical characteristics
STM32L151xD STM32L152xD
Table 13. General operating conditions (continued)
Symbol
TJ
Parameter
Junction temperature range
Conditions
Min
Max
6 suffix version
–40
105
7 suffix version
–40
110
Unit
°C
1. When the ADC is used, refer to Table 64: ADC characteristics.
2. It is recommended to power VDD and VDDA from the same source. A maximum difference of 300 mV between VDD and
VDDA can be tolerated during power-up .
3. To sustain a voltage higher than VDD+0.3V, the internal pull-up/pull-down resistors must be disabled.
4. If TA is lower, higher PD values are allowed as long as TJ does not exceed TJ max (see Table 80: Thermal characteristics
on page 146).
5. In low-power dissipation state, TA can be extended to -40°C to 105°C temperature range as long as TJ does not exceed TJ
max (see Table 80: Thermal characteristics on page 146).
6.3.2
Embedded reset and power control block characteristics
The parameters given in the following table are derived from the tests performed under the
conditions summarized in Table 13.
Table 14. Embedded reset and power control block characteristics
Symbol
Parameter
VDD rise time rate
tVDD(1)
VDD fall time rate
TRSTTEMPO(1)
Reset temporization
VPOR/PDR
Power on/power down reset
threshold
VBOR0
Brown-out reset threshold 0
VBOR1
Brown-out reset threshold 1
VBOR2
Brown-out reset threshold 2
64/154
Conditions
Min
Typ
Max
BOR detector enabled
0
-
∞
BOR detector disabled
0
-
1000
BOR detector enabled
20
-
∞
BOR detector disabled
0
-
1000
VDD rising, BOR enabled
-
2
3.3
0.4
0.7
1.6
Falling edge
1
1.5
1.65
Rising edge
1.3
1.5
1.65
Falling edge
1.67
1.7
1.74
Rising edge
1.69
1.76
1.8
Falling edge
1.87
1.93
1.97
Rising edge
1.96
2.03
2.07
Falling edge
2.22
2.30
2.35
Rising edge
2.31
2.41
2.44
VDD rising, BOR disabled(2)
DocID022027 Rev 10
Unit
µs/V
ms
V
STM32L151xD STM32L152xD
Electrical characteristics
Table 14. Embedded reset and power control block characteristics (continued)
Symbol
Parameter
Conditions
VBOR3
Brown-out reset threshold 3
VBOR4
Brown-out reset threshold 4
VPVD0
Programmable voltage detector
threshold 0
VPVD1
PVD threshold 1
VPVD2
PVD threshold 2
VPVD3
PVD threshold 3
VPVD4
PVD threshold 4
VPVD5
PVD threshold 5
VPVD6
PVD threshold 6
Vhyst
Hysteresis voltage
Min
Typ
Max
Falling edge
2.45
2.55
2.6
Rising edge
2.54
2.66
2.7
Falling edge
2.68
2.8
2.85
Rising edge
2.78
2.9
2.95
Falling edge
1.8
1.85
1.88
Rising edge
1.88
1.94
1.99
Falling edge
1.98
2.04
2.09
Rising edge
2.08
2.14
2.18
Falling edge
2.20
2.24
2.28
Rising edge
2.28
2.34
2.38
Falling edge
2.39
2.44
2.48
Rising edge
2.47
2.54
2.58
Falling edge
2.57
2.64
2.69
Rising edge
2.68
2.74
2.79
Falling edge
2.77
2.83
2.88
Rising edge
2.87
2.94
2.99
Falling edge
2.97
3.05
3.09
Rising edge
3.08
3.15
3.20
BOR0 threshold
-
40
-
All BOR and PVD
thresholds excepting BOR0
-
100
-
Unit
V
mV
1. Guaranteed by characterization results, not tested in production.
2. Valid for device version without BOR at power up. Please see option “D” in Ordering information scheme for more details.
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Electrical characteristics
6.3.3
STM32L151xD STM32L152xD
Embedded internal reference voltage
The parameters given in Table 16 are based on characterization results, unless otherwise
specified.
Table 15. Embedded internal reference voltage calibration values
Calibration value name
Description
Raw data acquired at
temperature of 30 °C ±5 °C
VDDA= 3 V ±10 mV
VREFINT_CAL
Memory address
0x1FF8 00F8 - 0x1FF8 00F9
Table 16. Embedded internal reference voltage
Symbol
VREFINT out
Parameter
(1)
Conditions
Internal reference voltage
Min
Typ
– 40 °C < TJ < +110 °C 1.202 1.224
Max
Unit
1.242
V
Internal reference current
consumption
-
-
1.4
2.3
µA
TVREFINT
Internal reference startup time
-
-
2
3
ms
VVREF_MEAS
VDDA and VREF+ voltage during
VREFINT factory measure
-
2.99
3
3.01
V
AVREF_MEAS
Including uncertainties
Accuracy of factory-measured VREF
due to ADC and
(2)
value
VDDA/VREF+ values
-
-
±5
mV
TCoeff(3)
Temperature coefficient
–40 °C < TJ < +110 °C
-
25
100
ppm/°
C
ACoeff(3)
Long-term stability
1000 hours, T= 25 °C
-
-
1000
ppm
VDDCoeff(3)
Voltage coefficient
3.0 V < VDDA < 3.6 V
-
-
2000
ppm/V
TS_vrefint(3)
ADC sampling time when reading
the internal reference voltage
-
4
-
-
µs
TADC_BUF(3) (4)
Startup time of reference voltage
buffer for ADC
-
-
-
10
µs
IBUF_ADC(3)
Consumption of reference voltage
buffer for ADC
-
-
13.5
25
µA
IVREF_OUT(3)
VREF_OUT output current (5)
-
-
-
1
µA
CVREF_OUT(3)
VREF_OUT output load
-
-
-
50
pF
Consumption of reference voltage
buffer for VREF_OUT and COMP
-
-
730
1200
nA
VREFINT_DIV1(3)
1/4 reference voltage
-
24
25
26
VREFINT_DIV2(3)
1/2 reference voltage
-
49
50
51
VREFINT_DIV3(3)
3/4 reference voltage
-
74
75
76
IREFINT
ILPBUF(3)
1. Guaranteed by test in production.
2. The internal VREF value is individually measured in production and stored in dedicated EEPROM bytes.
3. Guaranteed by characterization results, not tested in production.
4. Shortest sampling time can be determined in the application by multiple iterations.
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VREFIN
T
STM32L151xD STM32L152xD
Electrical characteristics
5. To guarantee less than 1% VREF_OUT deviation.
6.3.4
Supply current characteristics
The current consumption is a function of several parameters and factors such as the
operating voltage, temperature, I/O pin loading, device software configuration, operating
frequencies, I/O pin switching rate, program location in memory and executed binary code.
The current consumption is measured as described in Figure 13: Current consumption
measurement scheme.
All Run-mode current consumption measurements given in this section are performed with a
reduced code that gives a consumption equivalent to the Dhrystone 2.1 code, unless
otherwise specified. The current consumption values are derived from tests performed
under ambient temperature TA = 25 °C and VDD supply voltage conditions summarized in
Table 13: General operating conditions, unless otherwise specified.
The MCU is placed under the following conditions:
•
All I/O pins are configured in analog input mode
•
All peripherals are disabled except when explicitly mentioned.
•
The Flash memory access time, 64-bit access and prefetch is adjusted depending on
fHCLK frequency and voltage range to provide the best CPU performance.
•
When the peripherals are enabled fAPB1 = fAPB2 = fAHB.
•
When PLL is ON, the PLL inputs are equal to HSI = 16 MHz (if internal clock is used) or
HSE = 16 MHz (if HSE bypass mode is used).
•
The HSE user clock applied to OSCI_IN input follows the characteristic specified in
Table 26: High-speed external user clock characteristics.
•
For maximum current consumption VDD = VDDA = 3.6 V is applied to all supply pins.
•
For typical current consumption VDD = VDDA = 3.0 V is applied to all supply pins if not
specified otherwise.
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Electrical characteristics
STM32L151xD STM32L152xD
Table 17. Current consumption in Run mode, code with data processing running from Flash
Symbol
Parameter
Conditions
Typ
1
290
500
2
505
750
4
955
1200
4
1.15
1.6
8
2.3
2.9
16
4.25
5.2
Range3,
VCORE=1.2 V
VOS[1:0]=11
Range2,
fHSE = fHCLK up to 16MHz,
included fHSE = fHCLK/2 above VCORE=1.5 V
16 MHz (PLL ON)(2)
VOS[1:0]=10
IDD (Run
from
Flash)
Supply current in
Run mode code
executed from Flash
HSI clock source (16 MHz)
MSI clock, 65 kHZ
MSI clock, 524 kHZ
MSI clock, 4.2 MHZ
(1)
Range1,
VCORE=1.8 V
VOS[1:0]=01
8
2.65
3.5
16
5.35
6.5
32
10.5
12
Range2,
VCORE=1.5 V
VOS[1:0]=10
16
4.35
5.2
Range1,
VCORE=1.8 V
VOS[1:0]=01
32
10.5
12.3
0.065
46
130
0.524
160
250
4.2
965
1200
Range3,
VCORE=1.2 V
VOS[1:0]=11
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Max
fHCLK
[MHz]
DocID022027 Rev 10
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μA
mA
μA
STM32L151xD STM32L152xD
Electrical characteristics
Table 18. Current consumption in Run mode, code with data processing running from RAM
Symbol
Parameter
Conditions
Range3,
VCORE=1.2 V
VOS[1:0]=11
fHSE = fHCLK up to 16 MHz,
Range2,
included fHSE = fHCLK/2 above VCORE=1.5 V
16MHz (PLL ON)(1)
VOS[1:0]=10
IDD (Run
from RAM)
Supply current in
Run mode code
executed from
RAM
HSI clock source (16 MHz)
MSI clock, 65 kHZ
MSI clock, 524 kHZ
MSI clock, 4.2 MHZ
fHCLK
Typ
Max
1
230
470
2
415
780
4
800
1200
4
0.935
1.5
8
1.9
3
16
3.75
5
Range1,
VCORE=1.8 V
VOS[1:0]=01
8
2.25
3.5
16
4.45
5.55
32
9.05
10.9
Range2,
VCORE=1.5 V
VOS[1:0]=10
16
3.75
4.8
Range1,
VCORE=1.8 V
VOS[1:0]=01
32
8.95
11.7
0.065
43.5
100
0.524
135
215
4.2
835
1100
Range3,
VCORE=1.2 V
VOS[1:0]=11
Unit
μA
mA
μA
1. Oscillator bypassed (HSEBYP = 1 in RCC_CR register).
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Table 19. Current consumption in Sleep mode
Symbol
Parameter
Conditions
Typ
1
58
220
2
96
300
4
170
380
4
210
500
8
400
700
16
810
1100
Range3,
Vcore=1.2 V
VOS[1:0]=11
fHSE = fHCLK up to 16 MHz, Range2,
Vcore=1.5 V
included fHSE = fHCLK/2
above 16 MHz (PLL ON)(2) VOS[1:0]=10
Supply current in
Sleep mode, code
executed from
RAM, Flash
switched OFF
HSI clock source (16 MHz)
MSI clock, 65 kHZ
MSI clock, 524 kHZ
MSI clock, 4.2 MHZ
IDD(SLEEP)
8
485
800
16
955
1250
32
2100
2700
Range2,
Vcore=1.5 V
VOS[1:0]=10
16
835
1100
Range1,
Vcore=1.8 V
VOS[1:0]=01
32
2100
2700
0.065
18.5
72
0.524
37
92
4.2
180
273
1
75
250
2
115
300
4
200
380
4
230
500
8
430
700
16
840
1120
Range3,
Vcore=1.2 V
VOS[1:0]=11
fHSE = fHCLK up to 16 MHz, Range2,
included fHSE = fHCLK/2
Vcore=1.5 V
above 16MHz (PLL ON)(2) VOS[1:0]=10
HSI clock source (16 MHz)
MSI clock, 65 kHZ
MSI clock, 524 kHZ
MSI clock, 4.2 MHZ
Range1,
Vcore=1.8 V
VOS[1:0]=01
8
500
800
16
980
1300
32
2100
2700
Range2,
Vcore=1.5 V
VOS[1:0]=10
16
860
1160
Range1,
Vcore=1.8 V
VOS[1:0]=01
32
2150
2800
0.065
33,5
90
0.524
53
110
4.2
200
290
Range3,
Vcore=1.2 V
VOS[1:0]=11
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
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(1)
Range1,
Vcore=1.8 V
VOS[1:0]=01
Range3,
Vcore=1.2 V
VOS[1:0]=11
Supply current in
Sleep mode, Flash
switched ON
Max
fHCLK
DocID022027 Rev 10
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μA
STM32L151xD STM32L152xD
Electrical characteristics
2. Oscillator bypassed (HSEBYP = 1 in RCC_CR register)
Table 20. Current consumption in Low-power run mode
Symbol
Parameter
All
peripherals
OFF, code
executed
from RAM,
Flash
switched
OFF, VDD
from 1.65 V
to 3.6 V
IDD (LP
Run)
Typ
Max(1)
TA = -40 °C to 25 °C
11
14
TA = 85 °C
26
32
TA = 105 °C
53
72
TA =-40 °C to 25 °C
18
21
TA = 85 °C
33
40
TA = 105 °C
60
78
TA = -40 °C to 25 °C
36
41
TA = 55 °C
39
44
TA = 85 °C
50
58
TA = 105 °C
78
95
TA = -40 °C to 25 °C
36
40.5
TA = 85 °C
53
60
TA = 105 °C
81
100
TA = -40 °C to 25 °C
44
49
TA = 85 °C
61
67
TA = 105 °C
89
107
TA = -40 °C to 25 °C
64
71
TA = 55 °C
68
73
TA = 85 °C
80
88
TA = 105 °C
101
110
-
200
Conditions
Supply
current in
Low-power
run mode
MSI clock, 65 kHz
fHCLK = 32 kHz
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz
fHCLK = 131 kHz
MSI clock, 65 kHz
fHCLK = 32 kHz
All
peripherals
OFF, code
executed
from Flash,
VDD from
1.65 V to
3.6 V
Max allowed
VDD from
IDD max current in
1.65 V to
(LP Run) Low-power
3.6 V
run mode
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz
fHCLK = 131 kHz
-
-
Unit
µA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
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Table 21. Current consumption in Low-power sleep mode
Symbol
Parameter
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash OFF
MSI clock, 65 kHz
fHCLK = 32 kHz
Flash ON
All peripherals
OFF, VDD from
1.65 V to 3.6 V
IDD
(LP Sleep)
Typ
Max(1)
TA = -40 °C to 25 °C
4.4
-
TA = -40 °C to 25 °C
18
21
TA = 85 °C
24
27
TA = 105 °C
35
43
TA = -40 °C to 25 °C
18.6
21
TA = 85 °C
24.5
28
TA = 105 °C
35
42
TA = -40 °C to 25 °C
22
25
23.5
26
28.5
31
TA = 105 °C
39
45
TA = -40 °C to 25 °C
18
20.5
TA = 85 °C
24
27
TA = 105 °C
35
43
TA = -40 °C to 25 °C
18.6
21
TA = 85 °C
24.5
28
TA = 105 °C
35
42
TA = -40 °C to 25 °C
22
25
23.5
26
28.5
31
39
45
-
200
Conditions
MSI clock, 65 kHz
fHCLK = 65 kHz,
Flash ON
MSI clock, 131 kHz T = 55 °C
A
fHCLK = 131 kHz,
TA = 85 °C
Flash ON
Supply
current in
Low-power
sleep mode
MSI clock, 65 kHz
fHCLK = 32 kHz
TIM9 and
USART1
enabled, Flash
ON, VDD from
1.65 V to 3.6 V
MSI clock, 65 kHz
fHCLK = 65 kHz
MSI clock, 131 kHz TA = 55 °C
fHCLK = 131 kHz
TA = 85 °C
TA = 105 °C
IDD max
(LP Sleep)
Max
allowed
VDD from 1.65 V
current in
to 3.6 V
Low-power
sleep mode
-
-
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
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STM32L151xD STM32L152xD
Electrical characteristics
Table 22. Typical and maximum current consumptions in Stop mode
Symbol
Parameter
Conditions
1.1
-
TA = -40°C to 25°C
1.35
4
TA = 55°C
1.95
6
TA= 85°C
4.35
10
TA = 105°C
11.0
23
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
1.65
6
2.1
7
4.7
12
11.0
27
TA = -40°C to 25°C
2.5
10
4.65
11
7.25
16
TA = 105°C
14.0
44
TA = -40°C to 25°C
1.7
-
TA = 55°C
2.15
-
TA= 85°C
4.7
-
TA = 105°C
11.5
-
1.8
-
2.35
-
4.85
-
11.5
-
2.45
-
4.9
-
7.7
-
TA = 105°C
14.5
-
TA = -40°C to 25°C
VDD = 1.8V
1.35
-
TA = -40°C to 25°C
VDD = 3.0V
1.7
-
TA = -40°C to 25°C
VDD = 3.6V
2.0
-
LCD
TA = 55°C
ON (1/8
duty)(3) TA= 85°C
IDD (Stop
with RTC)
Supply current in
Stop mode with RTC
enabled
Max(1) Unit
TA = -40°C to 25°C
VDD = 1.8 V
LCD
OFF
RTC clocked by LSI
or LSE external clock
(32.768kHz),
regulator in LP mode,
HSI and HSE OFF
(no independent
watchdog)
Typ
LCD
OFF
TA = -40°C to 25°C
LCD
TA = 55°C
ON
(static T = 85°C
A
duty)(2)
TA = 105°C
RTC clocked by LSE
external quartz
(32.768kHz),
regulator in LP mode,
TA = -40°C to 25°C
HSI and HSE OFF
LCD
TA = 55°C
(no independent
ON
(1/8
watchdog(4)
duty)(3) TA= 85°C
LCD
OFF
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Table 22. Typical and maximum current consumptions in Stop mode (continued)
Symbol
Parameter
Conditions
Regulator in LP mode, HSI and
HSE OFF, independent
watchdog and LSI enabled
IDD (Stop)
Supply current in
Stop mode (RTC
disabled)
Typ
TA = -40°C to 25°C
1.6
2.2
TA = -40°C to 25°C
0.475
1
0.915
3
3.35
9
10.0
22(5)
2
-
1.45
-
1.45
-
Regulator in LP mode, LSI, HSI T = 55°C
A
and HSE OFF (no independent
TA= 85°C
watchdog)
TA = 105°C
IDD
(WU from
Stop)
MSI = 4.2 MHz
Supply current during
wakeup from Stop
MSI = 1.05 MHz
mode
MSI = 65 kHz(6)
Max(1) Unit
TA = -40°C to 25°C
µA
mA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. LCD enabled with external VLCD, static duty, division ratio = 256, all pixels active, no LCD connected.
3. LCD enabled with external VLCD, 1/8 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
4. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8 pF
loading capacitors.
5. Guaranteed by test in production.
6. When MSI = 64 kHz, the RMS current is measured over the first 15 µs following the wakeup event. For the remaining part
of the wakeup period, the current corresponds the Run mode current.
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Electrical characteristics
Table 23. Typical and maximum current consumptions in Standby mode
Symbol
Parameter
Typ
Max(1)
0.82
-
1.15
1.9
1.15
2.2
TA= 85 °C
1.65
4
TA = 105 °C
2.75
8.3(2)
TA = -40 °C to 25 °C
VDD = 1.8 V
1.05
-
TA = -40 °C to 25 °C
1.35
-
TA = 55 °C
1.55
-
TA= 85 °C
2.1
-
TA = 105 °C
3.3
-
1
1.7
0.305
0.6
0.365
0.9
0.66
2.75
TA = 105 °C
2
7(2)
TA = -40 °C to 25 °C
1
-
Conditions
TA = -40 °C to 25 °C
VDD = 1.8 V
T = -40 °C to 25 °C
RTC clocked by LSI (no A
independent watchdog) TA = 55 °C
IDD
(Standby
with RTC)
Supply current in
Standby mode with RTC
enabled
RTC clocked by LSE
external quartz (no
independent
watchdog)(3)
Independent watchdog
TA = -40 °C to 25 °C
and LSI enabled
IDD
(Standby)
IDD
(WU from
Standby)
Supply current in
Standby mode (RTC
disabled)
Supply current during
wakeup time from
Standby mode
TA = -40 °C to 25 °C
Independent watchdog TA = 55 °C
and LSI OFF
TA = 85 °C
-
Unit
µA
mA
1. Guaranteed by characterization results, not tested in production, unless otherwise specified.
2. Guaranteed by test in production.
3. Based on characterization done with a 32.768 kHz crystal (MC306-G-06Q-32.768, manufacturer JFVNY) with two 6.8pF
loading capacitors.
On-chip peripheral current consumption
The current consumption of the on-chip peripherals is given in the following table. The MCU
is placed under the following conditions:
•
all I/O pins are in input mode with a static value at VDD or VSS (no load)
•
all peripherals are disabled unless otherwise mentioned
•
the given value is calculated by measuring the current consumption
–
with all peripherals clocked off
–
with only one peripheral clocked on
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Table 24. Peripheral current consumption(1)
a
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
Low-power
sleep and
run
TIM2
14.3
12.1
9.5
12.1
TIM3
13.8
11.7
9.2
11.7
TIM4
13.2
11.1
8.7
11.1
TIM5
17.7
14.9
11.8
14.9
TIM6
4.8
4.0
3.0
4.0
TIM7
4.7
3.9
3.0
3.9
LCD
5.0
4.1
3.3
4.1
WWDG
3.5
2.9
2.3
2.9
SPI2
8.9
7.4
5.8
7.4
SPI3
7.3
6.0
4.8
6.0
USART2
9.4
7.7
6.1
7.7
USART3
9.4
7.6
6.0
7.6
UART4
10.1
8.4
6.7
8.4
UART5
9.5
7.9
6.3
7.9
I2C1
8.9
7.4
5.8
7.4
I2C2
7.9
6.4
5.1
6.4
USB
21.2
18.0
14.3
18.0
PWR
4.0
3.2
2.5
3.2
DAC
6.3
5.5
4.4
5.5
COMP
4.9
3.9
3.2
3.9
Peripheral
APB1
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STM32L151xD STM32L152xD
Electrical characteristics
Table 24. Peripheral current consumption(1) (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
Low-power
sleep and
run
SYSCFG &
RI
3.5
2.9
2.4
2.9
TIM9
9.0
7.4
5.8
7.4
TIM10
7.1
5.8
4.6
5.8
TIM11
6.5
5.3
4.3
5.3
ADC
11.0
9.1
7.2
9.1
SDIO
28.4
24.2
19.1
24.2
SPI1
5.1
4.2
3.3
4.2
USART1
9.4
7.8
6.1
7.8
GPIOA
7.3
6.1
4.8
6.1
GPIOB
7.5
6.1
4.8
6.1
GPIOC
8.2
6.8
5.3
6.8
GPIOD
8.7
7.1
5.7
7.1
GPIOE
7.6
6.2
4.9
6.2
GPIOF
7.7
6.3
5.0
6.3
GPIOG
8.4
7.0
5.4
7.0
GPIOH
1.8
1.3
1.1
1.3
CRC
0.8
0.6
0.4
0.6
FLASH
26.3
19.3
18.3
-(3)
DMA1
19.0
16.0
12.8
16.0
DMA2
17.0
14.5
11.5
14.5
FSMC
16.0
13.4
10.6
13.4
310
246
217
226.7
Peripheral
APB2
(2)
AHB
All enabled
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Table 24. Peripheral current consumption(1) (continued)
Typical consumption, VDD = 3.0 V, TA = 25 °C
Peripheral
Range 1,
VCORE=
1.8 V
VOS[1:0] =
01
Range 2,
VCORE=
1.5 V
VOS[1:0] =
10
Range 3,
VCORE=
1.2 V
VOS[1:0] =
11
IDD (RTC)
0.4
IDD (LCD)
3.1
IDD (ADC)(4)
1450
IDD (DAC)(5)
340
IDD (COMP1)
0.16
IDD (COMP2)
IDD (PVD / BOR)
Slow mode
2
Fast mode
5
(6)
Low-power
sleep and
run
Unit
µA
2.6
IDD (IWDG)
0.25
1. Data based on differential IDD measurement between all peripherals OFF an one peripheral with clock
enabled, in the following conditions: fHCLK = 32 MHz (range 1), fHCLK = 16 MHz (range 2), fHCLK = 4 MHz
(range 3), fHCLK = 64kHz (Low-power run/sleep), fAPB1 = fHCLK, fAPB2 = fHCLK, default prescaler value for
each peripheral. The CPU is in Sleep mode in both cases. No I/O pins toggling. Not tested in production.
2. HSI oscillator is OFF for this measure.
3. In Low-power sleep and run mode, the Flash memory must always be in power-down mode.
4. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC
conversion (HSI consumption not included).
5. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC
conversion of VDD/2. DAC is in buffered mode, output is left floating.
6. Including supply current of internal reference voltage.
6.3.5
Wakeup time from low-power mode
The wakeup times given in the following table are measured with the MSI RC oscillator. The
clock source used to wake up the device depends on the current operating mode:
•
Sleep mode: the clock source is the clock that was set before entering Sleep mode
•
Stop mode: the clock source is the MSI oscillator in the range configured before
entering Stop mode
•
Standby mode: the clock source is the MSI oscillator running at 2.1 MHz
All timings are derived from tests performed under the conditions summarized in Table 13.
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Table 25. Low-power mode wakeup timings
Symbol
Parameter
tWUSLEEP
Conditions
Wakeup from Sleep mode
tWUSLEEP_LP
tWUSTDBY
Max(1) Unit
fHCLK = 32 MHz
0.4
-
fHCLK = 262 kHz
Flash enabled
46
-
fHCLK = 262 kHz
Flash switched OFF
46
-
fHCLK = fMSI = 4.2 MHz
8.2
-
fHCLK = fMSI = 4.2 MHz
Voltage range 1 and 2
7.7
8.9
fHCLK = fMSI = 4.2 MHz
Voltage range 3
8.2
13.1
fHCLK = fMSI = 2.1 MHz
10.2
13.4
fHCLK = fMSI = 1.05 MHz
16
20
fHCLK = fMSI = 524 kHz
31
37
fHCLK = fMSI = 262 kHz
57
66
fHCLK = fMSI = 131 kHz
112
123
fHCLK = MSI = 65 kHz
221
236
Wakeup from Standby mode
ULP bit = 1 and FWU bit = 1
fHCLK = MSI = 2.1 MHz
58
104
Wakeup from Standby mode
FWU bit = 0
fHCLK = MSI = 2.1 MHz
2.6
3.25
Wakeup from Low-power sleep
mode, fHCLK = 262 kHz
Wakeup from Stop mode,
regulator in Run mode
ULP bit = 1 and FWU bit = 1
tWUSTOP
Typ
Wakeup from Stop mode,
regulator in low-power mode
ULP bit = 1 and FWU bit = 1
µs
ms
1. Guaranteed by characterization, not tested in production, unless otherwise specified
6.3.6
External clock source characteristics
High-speed external user clock generated from an external source
In bypass mode the HSE oscillator is switched off and the input pin is a standard GPIO.The
external clock signal has to respect the I/O characteristics in Section 6.3.13. However, the
recommended clock input waveform is shown in Figure 14.
Table 26. High-speed external user clock characteristics(1)
Symbol
fHSE_ext
Parameter
User external clock source
frequency
Conditions
Min
Typ
Max
Unit
CSS is on or
PLL is used
1
8
32
MHz
CSS is off, PLL
not used
0
8
32
MHz
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Table 26. High-speed external user clock characteristics(1) (continued)
Symbol
Parameter
VHSEH
VHSEL
Conditions
Min
Typ
Max
OSC_IN input pin high level voltage
0.7VDD
-
VDD
OSC_IN input pin low level voltage
VSS
-
0.3VDD
12
-
-
tw(HSEH)
tw(HSEL)
OSC_IN high or low time
tr(HSE)
tf(HSE)
OSC_IN rise or fall time
-
-
20
OSC_IN input capacitance
-
2.6
-
Cin(HSE)
-
Unit
V
ns
pF
1. Guaranteed by design, not tested in production.
Figure 14. High-speed external clock source AC timing diagram
WZ+6(+
9+6(+
9+6(/
WU+6(
WI+6(
WZ+6(/
W
7+6(
069
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Low-speed external user clock generated from an external source
The characteristics given in the following table result from tests performed using a lowspeed external clock source, and under the conditions summarized in Table 13.
Table 27. Low-speed external user clock characteristics(1)
Symbol
Parameter
Conditions
fLSE_ext
User external clock source
frequency
VLSEH
OSC32_IN input pin high level
voltage
VLSEL
OSC32_IN input pin low level
voltage
tw(LSEH)
tw(LSEL)
OSC32_IN high or low time
tr(LSE)
tf(LSE)
OSC32_IN rise or fall time
CIN(LSE)
Min
Typ
Max
Unit
1
32.768
1000
kHz
0.7VDD
-
VDD
V
-
VSS
-
0.3VDD
465
-
ns
OSC32_IN input capacitance
-
-
-
10
-
0.6
-
pF
1. Guaranteed by design, not tested in production
Figure 15. Low-speed external clock source AC timing diagram
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High-speed external clock generated from a crystal/ceramic resonator
The high-speed external (HSE) clock can be supplied with a 1 to 24 MHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 28. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
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STM32L151xD STM32L152xD
Table 28. HSE oscillator characteristics(1)(2)
Symbol
fOSC_IN
Parameter
Conditions
Min Typ
Max
Unit
24
MHz
Oscillator frequency
-
1
RF
Feedback resistor
-
-
200
-
kΩ
C
Recommended load
capacitance versus
equivalent serial
resistance of the crystal
(RS)(3)
RS = 30 Ω
-
20
-
pF
VDD= 3.3 V,
VIN = VSS with 30 pF
load
-
-
3
mA
C = 20 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.7 (stabilized)
C = 10 pF
fOSC = 16 MHz
-
-
2.5 (startup)
0.46 (stabilized)
Startup
3.5
-
-
mA /V
VDD is stabilized
-
1
-
ms
IHSE
IDD(HSE)
gm
tSU(HSE)(4)
HSE driving current
HSE oscillator power
consumption
Oscillator
transconductance
Startup time
mA
1. Resonator characteristics given by the crystal/ceramic resonator manufacturer.
2. Guaranteed by characterization results, not tested in production.
3. The relatively low value of the RF resistor offers a good protection against issues resulting from use in a humid
environment, due to the induced leakage and the bias condition change. However, it is recommended to take this point into
account if the MCU is used in tough humidity conditions.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 8 MHz oscillation is
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
For CL1 and CL2, it is recommended to use high-quality external ceramic capacitors in the
5 pF to 25 pF range (typ.), designed for high-frequency applications, and selected to match
the requirements of the crystal or resonator (see Figure 16). CL1 and CL2 are usually the
same size. The crystal manufacturer typically specifies a load capacitance which is the
series combination of CL1 and CL2. PCB and MCU pin capacitance must be included (10 pF
can be used as a rough estimate of the combined pin and board capacitance) when sizing
CL1 and CL2. Refer to the application note AN2867 “Oscillator design guide for ST
microcontrollers” available from the ST website www.st.com.
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Electrical characteristics
Figure 16. HSE oscillator circuit diagram
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Low-speed external clock generated from a crystal/ceramic resonator
The low-speed external (LSE) clock can be supplied with a 32.768 kHz crystal/ceramic
resonator oscillator. All the information given in this paragraph are based on
characterization results obtained with typical external components specified in Table 29. In
the application, the resonator and the load capacitors have to be placed as close as
possible to the oscillator pins in order to minimize output distortion and startup stabilization
time. Refer to the crystal resonator manufacturer for more details on the resonator
characteristics (frequency, package, accuracy).
Table 29. LSE oscillator characteristics (fLSE = 32.768 kHz)(1)
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
fLSE
Low speed external oscillator
frequency
-
-
32.768
-
kHz
RF
Feedback resistor
-
-
1.2
-
MΩ
C(2)
Recommended load capacitance
versus equivalent serial
resistance of the crystal (RS)(3)
RS = 30 kΩ
-
8
-
pF
ILSE
LSE driving current
VDD = 3.3 V, VIN = VSS
-
-
1.1
µA
VDD = 1.8 V
-
450
-
VDD = 3.0 V
-
600
-
VDD = 3.6V
-
750
-
-
3
-
-
µA/V
VDD is stabilized
-
1
-
s
IDD (LSE)
gm
LSE oscillator current
consumption
Oscillator transconductance
tSU(LSE)(4) Startup time
nA
1. Guaranteed by characterization results, not tested in production.
2. Refer to the note and caution paragraphs below the table, and to the application note AN2867 “Oscillator
design guide for ST microcontrollers”.
3. The oscillator selection can be optimized in terms of supply current using an high quality resonator with
small RS value for example MSIV-TIN32.768kHz. Refer to crystal manufacturer for more details.
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Electrical characteristics
4.
STM32L151xD STM32L152xD
tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized
32.768 kHz oscillation is reached. This value is measured for a standard crystal resonator and it can vary
significantly with the crystal manufacturer.
Note:
For CL1 and CL2, it is recommended to use high-quality ceramic capacitors in the 5 pF to
15 pF range selected to match the requirements of the crystal or resonator (see Figure 17).
CL1 and CL2, are usually the same size. The crystal manufacturer typically specifies a load
capacitance which is the series combination of CL1 and CL2.
Load capacitance CL has the following formula: CL = CL1 x CL2 / (CL1 + CL2) + Cstray where
Cstray is the pin capacitance and board or trace PCB-related capacitance. Typically, it is
between 2 pF and 7 pF.
Caution:
To avoid exceeding the maximum value of CL1 and CL2 (15 pF) it is strongly recommended
to use a resonator with a load capacitance CL ≤7 pF. Never use a resonator with a load
capacitance of 12.5 pF.
Example: if you choose a resonator with a load capacitance of CL = 6 pF and Cstray = 2 pF,
then CL1 = CL2 = 8 pF.
Figure 17. Typical application with a 32.768 kHz crystal
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6.3.7
Electrical characteristics
Internal clock source characteristics
The parameters given in Table 30 are derived from tests performed under the conditions
summarized in Table 13.
High-speed internal (HSI) RC oscillator
Table 30. HSI oscillator characteristics
Symbol
fHSI
TRIM
(1)(2)
Parameter
Conditions
Min
Typ
Max
Unit
Frequency
VDD = 3.0 V
-
16
-
MHz
HSI user-trimmed
resolution
Trimming code is not a multiple of 16
-
± 0.4
0.7
%
Trimming code is a multiple of 16
-
Accuracy of the
ACCHSI(2) factory-calibrated
HSI oscillator
-
± 1.5
%
VDDA = 3.0 V, TA = 25 °C
-1(3)
-
1(3)
%
VDDA = 3.0 V, TA = 0 to 55 °C
-1.5
-
1.5
%
VDDA = 3.0 V, TA = -10 to 70 °C
-2
-
2
%
VDDA = 3.0 V, TA = -10 to 85 °C
-2.5
-
2
%
VDDA = 3.0 V, TA = -10 to 105 °C
-4
-
2
%
VDDA = 1.65 V to 3.6 V
TA = -40 to 105 °C
-4
-
3
%
tSU(HSI)(2)
HSI oscillator
startup time
-
-
3.7
6
µs
IDD(HSI)(2)
HSI oscillator
power consumption
-
-
100
140
µA
1. The trimming step differs depending on the trimming code. It is usually negative on the codes which are
multiples of 16 (0x00, 0x10, 0x20, 0x30...0xE0).
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by test in production.
Low-speed internal (LSI) RC oscillator
Table 31. LSI oscillator characteristics
Symbol
fLSI(1)
DLSI(2)
tsu(LSI)(3)
IDD(LSI)
(3)
Parameter
Min
Typ
Max
Unit
LSI frequency
26
38
56
kHz
LSI oscillator frequency drift
0°C ≤TA ≤ 105°C
-10
-
4
%
LSI oscillator startup time
-
-
200
µs
LSI oscillator power consumption
-
400
510
nA
1. Guaranteed by test in production.
2. This is a deviation for an individual part, once the initial frequency has been measured.
3. Guaranteed by design, not tested in production.
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Multi-speed internal (MSI) RC oscillator
Table 32. MSI oscillator characteristics
Symbol
Condition
Typ
MSI range 0
65.5
-
MSI range 1
131
-
MSI range 2
262
-
MSI range 3
524
-
MSI range 4
1.05
-
MSI range 5
2.1
-
MSI range 6
4.2
-
Frequency error after factory calibration
-
±0.5
-
%
DTEMP(MSI)(1)
MSI oscillator frequency drift
0 °C ≤TA ≤105 °C
-
±3
-
%
DVOLT(MSI)(1)
MSI oscillator frequency drift
1.65 V ≤VDD ≤3.6 V, TA = 25 °C
-
-
2.5
%/V
MSI range 0
0.75
-
MSI range 1
1
-
MSI range 2
1.5
-
MSI range 3
2.5
-
MSI range 4
4.5
-
MSI range 5
8
-
MSI range 6
15
-
MSI range 0
30
-
MSI range 1
20
-
MSI range 2
15
-
MSI range 3
10
-
MSI range 4
6
-
MSI range 5
5
-
MSI range 6,
Voltage range 1
and 2
3.5
-
MSI range 6,
Voltage range 3
5
-
fMSI
ACCMSI
IDD(MSI)(2)
tSU(MSI)
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Parameter
Frequency after factory calibration, done at
VDD= 3.3 V and TA = 25 °C
MSI oscillator power consumption
MSI oscillator startup time
DocID022027 Rev 10
Max Unit
kHz
MHz
µA
µs
STM32L151xD STM32L152xD
Electrical characteristics
Table 32. MSI oscillator characteristics (continued)
Symbol
tSTAB(MSI)(2)
fOVER(MSI)
Parameter
MSI oscillator stabilization time
MSI oscillator frequency overshoot
Condition
Typ
Max Unit
MSI range 0
-
40
MSI range 1
-
20
MSI range 2
-
10
MSI range 3
-
4
MSI range 4
-
2.5
MSI range 5
-
2
MSI range 6,
Voltage range 1
and 2
-
2
MSI range 3,
Voltage range 3
-
3
Any range to
range 5
-
4
Any range to
range 6
-
µs
MHz
6
1. This is a deviation for an individual part, once the initial frequency has been measured.
2. Guaranteed by characterization results, not tested in production.
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Electrical characteristics
6.3.8
STM32L151xD STM32L152xD
PLL characteristics
The parameters given in Table 33 are derived from tests performed under the conditions
summarized in Table 13.
Table 33. PLL characteristics
Value
Symbol
Parameter
Unit
Min
Typ
Max(1)
PLL input clock(2)
2
-
24
MHz
PLL input clock duty cycle
45
-
55
%
fPLL_OUT
PLL output clock
2
-
32
MHz
tLOCK
PLL lock time
PLL input = 16 MHz
PLL VCO = 96 MHz
-
115
160
µs
Jitter
Cycle-to-cycle jitter
-
-
± 600
ps
IDDA(PLL)
Current consumption on VDDA
-
220
450
IDD(PLL)
Current consumption on VDD
-
120
150
fPLL_IN
µA
1. Guaranteed by characterization results, not tested in production.
2. Take care of using the appropriate multiplier factors so as to have PLL input clock values compatible with
the range defined by fPLL_OUT.
6.3.9
Memory characteristics
The characteristics are given at TA = -40 to 105 °C unless otherwise specified.
RAM memory
Table 34. RAM and hardware registers
Symbol
VRM
Parameter
Conditions
Data retention mode(1)
STOP mode (or RESET)
Min
Typ
Max
Unit
1.65
-
-
V
1. Minimum supply voltage without losing data stored in RAM (in Stop mode or under Reset) or in hardware
registers (only in Stop mode).
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Electrical characteristics
Flash memory and data EEPROM
Table 35. Flash memory and data EEPROM characteristics
Symbol
Conditions
Min
Typ
Max(1)
Unit
-
1.65
-
3.6
V
Erasing
-
3.28
3.94
Programming
-
3.28
3.94
Average current during
the whole programming /
erase operation
-
600
900
µA
Maximum current (peak) TA = 25 °C, VDD = 3.6 V
during the whole
programming / erase
operation
-
1.5
2.5
mA
Parameter
VDD
Operating voltage
Read / Write / Erase
tprog
Programming/ erasing
time for byte / word /
double word / half-page
IDD
ms
1. Guaranteed by design, not tested in production.
Table 36. Flash memory and data EEPROM endurance and retention
Value
Symbol
NCYC(2)
Parameter
Cycling (erase / write)
Program memory
Cycling (erase / write)
EEPROM data memory
Data retention (program memory) after
10 kcycles at TA = 85 °C
tRET
(2)
Data retention (EEPROM data memory)
after 300 kcycles at TA = 85 °C
Data retention (program memory) after
10 kcycles at TA = 105 °C
Data retention (EEPROM data memory)
after 300 kcycles at TA = 105 °C
Conditions
TA = -40°C to
105 °C
Min(1) Typ Max
10
-
-
300
-
-
30
-
-
30
-
-
10
-
-
10
-
-
Unit
kcycles
TRET = +85 °C
years
TRET = +105 °C
1. Guaranteed by characterization results, not tested in production.
2. Characterization is done according to JEDEC JESD22-A117.
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Electrical characteristics
6.3.10
STM32L151xD STM32L152xD
FSMC characteristics
Asynchronous waveforms and timings
Figure 18 through Figure 21 represent asynchronous waveforms and Table 37 through
Table 40 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
AddressSetupTime = 0 (AddressSetupTime = 1, for asynchronous multiplexed modes)
•
AddressHoldTime = 1
•
DataSetupTime = 1
Figure 18. Asynchronous non-multiplexed SRAM/PSRAM/NOR read waveforms
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Electrical characteristics
Table 37. Asynchronous non-multiplexed SRAM/PSRAM/NOR read timings(1)
Symbol
Parameter
Min
Max
Unit
THCLK -2
THCLK
ns
0
2
ns
THCLK
THCLK - 1
ns
tw(NE)
FSMC_NE low time
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
tw(NOE)
FSMC_NOE low time
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
0
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
4
ns
th(A_NOE)
Address hold time after FSMC_NOE high
THCLK + 1.5
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0.5
ns
th(BL_NOE)
FSMC_BL hold time after FSMC_NOE high
2*THCLK - 0.5
-
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
THCLK
-
ns
THCLK
-
ns
tsu(Data_NOE) Data to FSMC_NOEx high setup time
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
-
2
ns
tw(NADV)
FSMC_NADV low time
-
THCLK
ns
1. CL = 30 pF.
Figure 19. Asynchronous non-multiplexed SRAM/PSRAM/NOR write waveforms
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Electrical characteristics
STM32L151xD STM32L152xD
Table 38. Asynchronous non-multiplexed SRAM/PSRAM/NOR write timings(1)
Symbol
Parameter
tw(NE)
FSMC_NE low time
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
tw(NWE)
FSMC_NWE low time
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
tv(A_NE)
FSMC_NEx low to FSMC_A valid
th(A_NWE)
Address hold time after FSMC_NWE high
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
tv(Data_NE)
FSMC_NEx low to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
Min
Max
Unit
2*THCLK -3
2*THCLK +2
ns
0.5
1
ns
THCLK - 2
THCLK + 3
ns
THCLK - 2.5
-
ns
-
0
ns
THCLK - 2.5
-
ns
-
0
ns
THCLK - 4
-
ns
-
THCLK
ns
THCLK - 2.5
-
ns
1. CL = 30 pF.
Figure 20. Asynchronous multiplexed PSRAM/NOR read waveforms
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Electrical characteristics
Table 39. Asynchronous multiplexed PSRAM/NOR read timings(1)
Symbol
Parameter
Min
Max
Unit
tw(NE)
FSMC_NE low time
tv(NOE_NE)
FSMC_NEx low to FSMC_NOE low
2*THCLK - 1
2*THCLK
ns
tw(NOE)
FSMC_NOE low time
THCLK - 0.5
THCLK + 0.5
ns
th(NE_NOE)
FSMC_NOE high to FSMC_NE high hold time
0
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
5
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
1.5
2
ns
tw(NADV)
FSMC_NADV low time
THCLK - 0.5
THCLK
ns
th(AD_NADV)
FSMC_AD(address) valid hold time after
FSMC_NADV high
THCLK - 6
-
ns
th(A_NOE)
Address hold time after FSMC_NOE high
2*THCLK - 1
-
ns
th(BL_NOE)
FSMC_BL time after FSMC_NOE high
1.5
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0
ns
tsu(Data_NE)
Data to FSMC_NEx high setup time
THCLK
-
ns
tsu(Data_NOE) Data to FSMC_NOE high setup time
THCLK
-
ns
3*THCLK - 1.5 3*THCLK + 1
ns
th(Data_NE)
Data hold time after FSMC_NEx high
0
-
ns
th(Data_NOE)
Data hold time after FSMC_NOE high
0
-
ns
1. CL = 30 pF.
Figure 21. Asynchronous multiplexed PSRAM/NOR write waveforms
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Electrical characteristics
STM32L151xD STM32L152xD
Table 40. Asynchronous multiplexed PSRAM/NOR write timings(1)
Symbol
Parameter
Max
Unit
4*THCLK - 3
4*THCLK + 2
ns
THCLK
THCLK + 1
ns
tw(NE)
FSMC_NE low time
tv(NWE_NE)
FSMC_NEx low to FSMC_NWE low
tw(NWE)
FSMC_NWE low time
2*THCLK - 2
2*THCLK + 4
ns
th(NE_NWE)
FSMC_NWE high to FSMC_NE high hold time
THCLK - 2.5
-
ns
tv(A_NE)
FSMC_NEx low to FSMC_A valid
-
6
ns
tv(NADV_NE)
FSMC_NEx low to FSMC_NADV low
1.5
2
ns
tw(NADV)
FSMC_NADV low time
THCLK - 4
THCLK + 4
ns
th(AD_NADV)
FSMC_AD (address) valid hold time after
FSMC_NADV high
THCLK - 5
-
ns
th(A_NWE)
Address hold time after FSMC_NWE high
THCLK - 2.5
-
ns
th(BL_NWE)
FSMC_BL hold time after FSMC_NWE high
THCLK - 3
-
ns
tv(BL_NE)
FSMC_NEx low to FSMC_BL valid
-
0.5
ns
-
THCLK + 6
ns
THCLK - 2.5
-
ns
tv(Data_NADV) FSMC_NADV high to Data valid
th(Data_NWE)
Data hold time after FSMC_NWE high
1. CL = 30 pF.
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Electrical characteristics
Synchronous waveforms and timings
Figure 22 through Figure 25 represent synchronous waveforms and Table 42 through
Table 44 provide the corresponding timings. The results shown in these tables are obtained
with the following FSMC configuration:
•
BurstAccessMode = FSMC_BurstAccessMode_Enable;
•
MemoryType = FSMC_MemoryType_CRAM;
•
WriteBurst = FSMC_WriteBurst_Enable;
•
CLKDivision = 1;
•
DataLatency = 1 for NOR Flash; DataLatency = 0 for PSRAM
Figure 22. Synchronous multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
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TD#,+,.%X,
T D#,+,.%X(
&3-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&3-#?.!$6
TD#,+,!)6
TD#,+,!6
&3-#?!;=
TD#,+,./%,
TD#,+,./%(
&3-#?./%
TD#,+,!$)6
TSU!$6#,+(
TD#,+,!$6
&3-#?!$;=
!$;=
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TSU!$6#,+(
$
TSU.7!)46#,+(
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$
TH#,+(.7!)46
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7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
AIG
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Table 41. Synchronous multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Max
Unit
2*THCLK 0.5
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
THCLK +
1.5
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
3
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
3.5
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
0
-
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
-
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
2.5
-
ns
td(CLKL-ADV)
FSMC_CLK low to FSMC_AD[15:0] valid
-
4
ns
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
0
-
ns
tsu(ADV-CLKH)
FSMC_A/D[15:0] valid data before FSMC_CLK high
6
-
ns
th(CLKH-ADV)
FSMC_A/D[15:0] valid data after FSMC_CLK high
4
-
ns
6
-
ns
0
-
ns
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
1. CL = 30 pF.
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STM32L151xD STM32L152xD
Electrical characteristics
Figure 23. Synchronous multiplexed PSRAM write timings
"53452.
TW#,+
TW#,+
&3-#?#,+
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TD#,+,.%X,
TD#,+,.%X(
&3-#?.%X
TD#,+,.!$6,
TD#,+,.!$6(
&3-#?.!$6
TD#,+,!6
TD#,+,!)6
&3-#?!;=
TD#,+,.7%,
TD#,+,.7%(
&3-#?.7%
TD#,+,!$)6
TD#,+,!$6
&3-#?!$;=
TD#,+,$ATA
TD#,+,$ATA
!$;=
$
$
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
TD#,+,.",(
&3-#?.",
AIF
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Electrical characteristics
STM32L151xD STM32L152xD
Table 42. Synchronous multiplexed PSRAM write timings(1)
Symbol
Parameter
Max
Unit
2*THCLK
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
0
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
0
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
0
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
THCLK + 4
-
ns
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
-
0
ns
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
1
-
ns
td(CLKL-ADIV)
FSMC_CLK low to FSMC_AD[15:0] invalid
5
-
ns
td(CLKL-DATA)
FSMC_A/D[15:0] valid after FSMC_CLK low
-
6
ns
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
6
-
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
0
-
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
1
-
ns
1. CL = 30 pF.
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Electrical characteristics
Figure 24. Synchronous non-multiplexed NOR/PSRAM read timings
"53452.
TW#,+
TW#,+
&3-#?#,+
TD#,+,.%X,
TD#,+,.%X(
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TD#,+,.!$6,
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&3-#?.!$6
TD#,+,!)6
TD#,+,!6
&3-#?!;=
TD#,+,./%,
TD#,+,./%(
&3-#?./%
TSU$6#,+(
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TSU$6#,+(
&3-#?$;=
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TSU.7!)46#,+(
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$
TH#,+(.7!)46
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7!)4#&'B7!)40/,B
TSU.7!)46#,+(
T H#,+(.7!)46
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
TH#,+(.7!)46
AIF
Table 43. Synchronous non-multiplexed NOR/PSRAM read timings(1)
Symbol
Parameter
Min
Max
Unit
2*THCLK 0.5
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
0
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
3
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
3.5
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
0
-
ns
td(CLKL-NOEL)
FSMC_CLK low to FSMC_NOE low
-
THCLK + 1
ns
td(CLKL-NOEH)
FSMC_CLK low to FSMC_NOE high
2.5
-
ns
tsu(DV-CLKH)
FSMC_D[15:0] valid data before FSMC_CLK
high
4
-
ns
th(CLKH-DV)
FSMC_D[15:0] valid data after FSMC_CLK high
4
-
ns
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Table 43. Synchronous non-multiplexed NOR/PSRAM read timings(1) (continued)
Symbol
Parameter
Min
Max
Unit
tsu(NWAITV-CLKH) FSMC_NWAIT valid before FSMC_CLK high
6
-
ns
th(CLKH-NWAITV)
0
-
ns
FSMC_NWAIT valid after FSMC_CLK high
1. CL = 30 pF.
Figure 25. Synchronous non-multiplexed PSRAM write timings
TW#,+
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&3-#?#,+
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TD#,+,.%X(
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&3-#?.!$6
TD#,+,!6
TD#,+,!)6
&3-#?!;=
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&3-#?.7%
TD#,+,$ATA
&3-#?$;=
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$
$
&3-#?.7!)4
7!)4#&'B7!)40/,B
TSU.7!)46#,+(
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TH#,+(.7!)46
&3-#?.",
AIG
Table 44. Synchronous non-multiplexed PSRAM write timings(1)
Symbol
100/154
Parameter
Min
Max
Unit
2*THCLK -3
-
ns
tw(CLK)
FSMC_CLK period
td(CLKL-NExL)
FSMC_CLK low to FSMC_NEx low (x = 0...2)
-
0
ns
td(CLKL-NExH)
FSMC_CLK low to FSMC_NEx high (x = 0...2)
1
-
ns
td(CLKL-NADVL)
FSMC_CLK low to FSMC_NADV low
-
5
ns
td(CLKL-NADVH)
FSMC_CLK low to FSMC_NADV high
7
-
ns
td(CLKL-AV)
FSMC_CLK low to FSMC_Ax valid (x = 16...25)
-
0
ns
td(CLKL-AIV)
FSMC_CLK low to FSMC_Ax invalid (x = 16...25)
THCLK + 4
-
ns
td(CLKL-NWEL)
FSMC_CLK low to FSMC_NWE low
-
2
ns
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Electrical characteristics
Table 44. Synchronous non-multiplexed PSRAM write timings(1) (continued)
Symbol
Parameter
Min
Max
Unit
td(CLKL-NWEH)
FSMC_CLK low to FSMC_NWE high
5
-
ns
td(CLKL-DATA)
FSMC_D[15:0] valid data after FSMC_CLK low
-
7
ns
td(CLKL-NBLH)
FSMC_CLK low to FSMC_NBL high
3
-
ns
tsu(NWAITV-CLKH)
FSMC_NWAIT valid before FSMC_CLK high
6
-
ns
th(CLKH-NWAITV)
FSMC_NWAIT valid after FSMC_CLK high
0
-
ns
1. CL = 30 pF.
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Electrical characteristics
6.3.11
STM32L151xD STM32L152xD
EMC characteristics
Susceptibility tests are performed on a sample basis during device characterization.
Functional EMS (electromagnetic susceptibility)
While a simple application is executed on the device (toggling 2 LEDs through I/O ports).
the device is stressed by two electromagnetic events until a failure occurs. The failure is
indicated by the LEDs:
•
Electrostatic discharge (ESD) (positive and negative) is applied to all device pins until
a functional disturbance occurs. This test is compliant with the IEC 61000-4-2 standard.
•
FTB: A Burst of Fast Transient voltage (positive and negative) is applied to VDD and
VSS through a 100 pF capacitor, until a functional disturbance occurs. This test is
compliant with the IEC 61000-4-4 standard.
A device reset allows normal operations to be resumed.
The test results are given in Table 45. They are based on the EMS levels and classes
defined in application note AN1709.
Table 45. EMS characteristics
Symbol
Parameter
Conditions
VFESD
VDD = 3.3 V, LQFP100, TA = +25 °C,
Voltage limits to be applied on any I/O pin to
fHCLK = 32 MHz
induce a functional disturbance
conforms to IEC 61000-4-2
VEFTB
Fast transient voltage burst limits to be
applied through 100 pF on VDD and VSS
pins to induce a functional disturbance
Level/
Class
VDD = 3.3 V, LQFP100, TA = +25
°C,
fHCLK = 32 MHz
conforms to IEC 61000-4-4
2B
4A
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Software recommendations
The software flowchart must include the management of runaway conditions such as:
•
Corrupted program counter
•
Unexpected reset
•
Critical data corruption (control registers...)
Prequalification trials
Most of the common failures (unexpected reset and program counter corruption) can be
reproduced by manually forcing a low state on the NRST pin or the oscillator pins for 1
second.
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Electrical characteristics
To complete these trials, ESD stress can be applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software can be hardened
to prevent unrecoverable errors occurring (see application note AN1015).
Electromagnetic Interference (EMI)
The electromagnetic field emitted by the device are monitored while a simple application is
executed (toggling 2 LEDs through the I/O ports). This emission test is compliant with
IEC 61967-2 standard which specifies the test board and the pin loading.
Table 46. EMI characteristics
Max vs. frequency range
Symbol Parameter
SEMI
6.3.12
Monitored
frequency band
Conditions
VDD = 3.3 V,
TA = 25 °C,
Peak level LQFP100 package
compliant with IEC
61967-2
4 MHz
16 MHz 32 MHz
voltage voltage voltage
range 3 range 2 range 1
0.1 to 30 MHz
3
-6
-5
30 to 130 MHz
18
4
-7
130 MHz to 1GHz
15
5
-7
SAE EMI Level
2.5
2
1
Unit
dBµV
-
Electrical sensitivity characteristics
Based on three different tests (ESD, LU) using specific measurement methods, the device is
stressed in order to determine its performance in terms of electrical sensitivity.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts × (n+1) supply pins). This test
conforms to the JESD22-A114/C101 standard.
Table 47. ESD absolute maximum ratings
Symbol
Ratings
Conditions
Class
Maximum
Unit
value(1)
Electrostatic discharge
VESD(HBM) voltage (human body
model)
TA = +25 °C, conforming to
JESD22-A114
2
2000
V
Electrostatic discharge
VESD(CDM) voltage (charge device
model)
TA = +25 °C, conforming to
ANSI/ESD STM5.3.1.
II
500
V
1. Guaranteed by characterization results, not tested in production.
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Electrical characteristics
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Static latch-up
Two complementary static tests are required on six parts to assess the latch-up
performance:
•
A supply overvoltage is applied to each power supply pin
•
A current injection is applied to each input, output and configurable I/O pin
These tests are compliant with EIA/JESD 78A IC latch-up standard.
Table 48. Electrical sensitivities
Symbol
LU
6.3.13
Parameter
Conditions
Static latch-up class
Class
TA = +105 °C conforming to JESD78A
II level A
I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error above a certain limit (higher
than 5 LSB TUE), out of conventional limits of induced leakage current on adjacent pins (out
of –5 µA/+0 µA range), or other functional failure (for example reset occurrence oscillator
frequency deviation, LCD levels).
The test results are given in the Table 49.
Table 49. I/O current injection susceptibility
Functional susceptibility
Symbol
Description
Injected current on all 5 V tolerant (FT) pins
IINJ
Injected current on BOOT0
Injected current on any other pin
Negative
injection
Positive
injection
-5 (1)
NA
-0
NA
-5
(1)
+5
1. It is recommended to add a Schottky diode (pin to ground) to analog pins which may potentially inject
negative currents.
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STM32L151xD STM32L152xD
6.3.14
Electrical characteristics
I/O port characteristics
General input/output characteristics
Unless otherwise specified, the parameters given in Table 56 are derived from tests
performed under the conditions summarized in Table 13. All I/Os are CMOS and TTL
compliant.
Table 50. I/O static characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
0.3VDD
VIL
Input low level voltage
Standard I/O
VIH
Input high level voltage
FT I/O
0.7 VDD
BOOT0 I/O
Vhys
Ilkg
I/O Schmitt trigger voltage
hysteresis(2)
Input leakage
current(4)
-
(1)
-
-
-
-
-
-
V
Standard I/O
-
10%
VDD(3)
-
VSS ≤VIN ≤VDD
I/Os with LCD
-
-
±50
VSS ≤VIN ≤VDD
I/Os with analog
switches
-
-
±50
VSS ≤VIN ≤VDD
I/Os with analog
switches and LCD
-
-
±50
VSS ≤VIN ≤VDD
I/Os with USB
-
-
±250
VSS ≤VIN ≤VDD
Standard I/Os
-
-
±50
FT I/O
VDD ≤ VIN ≤ 5V
-
-
±10
uA
nA
RPU
Weak pull-up equivalent
resistor(1)(5)
VIN = VSS
30
45
60
kΩ
RPD
Weak pull-down equivalent
resistor(5)
VIN = VDD
30
45
60
kΩ
CIO
I/O pin capacitance
-
-
5
-
pF
1. Guaranteed by test in production
2. Hysteresis voltage between Schmitt trigger switching levels. Guaranteed by characterization results, not
tested in production.
3. With a minimum of 200 mV. Based on characterization, not tested in production.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. Pull-up and pull-down resistors are designed with a true resistance in series with a switchable PMOS/NMOS.
.
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Output driving current
The GPIOs (general purpose input/outputs) can sink or source up to ±8 mA, and sink or
source up to ±20 mA with the non-standard VOL/VOH specifications given in Table 51.
In the user application, the number of I/O pins which can drive current must be limited to
respect the absolute maximum rating specified in Section 6.2:
•
The sum of the currents sourced by all the I/Os on VDD, plus the maximum Run
consumption of the MCU sourced on VDD, cannot exceed the absolute maximum rating
IVDD(Σ) (see Table 11).
•
The sum of the currents sunk by all the I/Os on VSS plus the maximum Run
consumption of the MCU sunk on VSS cannot exceed the absolute maximum rating
IVSS(Σ) (see Table 11).
Output voltage levels
Unless otherwise specified, the parameters given in Table 51 are derived from tests
performed under the conditions summarized in Table 13. All I/Os are CMOS and TTL
compliant.
Table 51. Output voltage characteristics
Symbol
VOL(1)(2)
Parameter
Output low level voltage for an I/O pin
VOH
(2)(3)
Output high level voltage for an I/O pin
VOL
(3)(4)
Output low level voltage for an I/O pin
VOH (3)(4) Output high level voltage for an I/O pin
VOL(1)(4)
VOH
(3)(4)
Conditions
Min
Max
IIO = 8 mA
2.7 V < VDD < 3.6 V
-
0.4
VDD-0.4
-
IIO = 4 mA
1.65 V < VDD < 3.6 V V -0.45
DD
Output low level voltage for an I/O pin
Output high level voltage for an I/O pin
IIO = 20 mA
2.7 V < VDD < 3.6 V
Unit
0.45
-
-
1.3
VDD-1.3
-
1. The IIO current sunk by the device must always respect the absolute maximum rating specified in Table 11
and the sum of IIO (I/O ports and control pins) must not exceed IVSS.
2. Guaranteed by test in production.
3. The IIO current sourced by the device must always respect the absolute maximum rating specified in
Table 11 and the sum of IIO (I/O ports and control pins) must not exceed IVDD.
4. Guaranteed by characterization results, not tested in production.
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Electrical characteristics
Input/output AC characteristics
The definition and values of input/output AC characteristics are given in Figure 26 and
Table 52, respectively.
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under the conditions summarized in Table 13.
Table 52. I/O AC characteristics(1)
OSPEEDRx
[1:0] bit
value(1)
Symbol
Parameter
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
fmax(IO)out
Maximum frequency(3)
tf(IO)out
tr(IO)out
Output rise and fall time
00
01
Fmax(IO)out Maximum frequency(3)
10
tf(IO)out
tr(IO)out
Output rise and fall time
Fmax(IO)out Maximum frequency(3)
11
-
tf(IO)out
tr(IO)out
Output rise and fall time
tEXTIpw
Pulse width of external
signals detected by the
EXTI controller
Min
Max(2)
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
400
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
400
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
625
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
625
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
2
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
1
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
125
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
250
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
10
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
2
CL = 50 pF, VDD = 2.7 V to 3.6 V
-
25
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
125
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
50
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
8
CL = 30 pF, VDD = 2.7 V to 3.6 V
-
5
CL = 50 pF, VDD = 1.65 V to 2.7 V
-
30
Conditions
-
Unit
kHz
ns
MHz
ns
MHz
ns
MHz
ns
8
-
1. The I/O speed is configured using the OSPEEDRx[1:0] bits. Refer to the STM32L151xx, STM32L152xx and STM32L162xx
reference manual for a description of GPIO Port configuration register.
2. Guaranteed by design, not tested in production.
3. The maximum frequency is defined in Figure 26.
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Electrical characteristics
STM32L151xD STM32L152xD
Figure 26. I/O AC characteristics definition
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6.3.15
AIC
NRST pin characteristics
The NRST pin input driver uses CMOS technology. It is connected to a permanent pull-up
resistor, RPU (see Table 53)
Unless otherwise specified, the parameters given in Table 53 are derived from tests
performed under the conditions summarized in Table 13.
Table 53. NRST pin characteristics
Symbol
Parameter
Conditions
Min
Typ
Max
VIL(NRST)(1)
NRST input low level
voltage
-
-
-
0.3 VDD
VIH(NRST)(1)
NRST input high
level voltage
-
0.7 VDD
-
-
VOL(NRST)(1)
NRST output low
level voltage
Unit
V
IOL = 2 mA
2.7 V < VDD < 3.6 V
-
IOL = 1.5 mA
1.65 V < VDD < 2.7 V
-
-
0.4
Vhys(NRST)(1)
NRST Schmitt trigger
voltage hysteresis
-
-
10%VDD(2)
-
mV
RPU
Weak pull-up
equivalent resistor(3)
VIN = VSS
30
45
60
kΩ
VF(NRST)(1)
NRST input filtered
pulse
-
-
-
50
ns
VNF(NRST)(3)
NRST input not
filtered pulse
-
350
-
-
ns
1. Guaranteed by design, not tested in production.
2. With a minimum of 200 mV.
3. The pull-up is designed with a true resistance in series with a switchable PMOS. This PMOS contribution to the series
resistance is around 10%.
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Electrical characteristics
Figure 27. Recommended NRST pin protection
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DLE
1. The reset network protects the device against parasitic resets.
2. The user must ensure that the level on the NRST pin can go below the VIL(NRST) max level specified in
Table 53. Otherwise the reset will not be taken into account by the device.
6.3.16
TIM timer characteristics
The parameters given in the Table 54 are guaranteed by design.
Refer to Section 6.3.14: I/O port characteristics for details on the input/output ction
characteristics (output compare, input capture, external clock, PWM output).
Table 54. TIMx(1) characteristics
Symbol
tres(TIM)
fEXT
ResTIM
tCOUNTER
Parameter
Timer resolution time
Conditions
Min
Max
Unit
-
1
-
tTIMxCLK
fTIMxCLK = 32 MHz
31.25
-
ns
0
fTIMxCLK/2
MHz
0
16
MHz
16
bit
65536
tTIMxCLK
2048
µs
Timer external clock
frequency on CH1 to CH4 f
TIMxCLK = 32 MHz
Timer resolution
-
16-bit counter clock
period when internal clock
is selected (timer’s
prescaler disabled)
-
tMAX_COUNT Maximum possible count
1
fTIMxCLK = 32 MHz 0.0312
-
-
65536 × 65536
tTIMxCLK
fTIMxCLK = 32 MHz
-
134.2
s
1. TIMx is used as a general term to refer to the TIM2, TIM3 and TIM4 timers.
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130
Electrical characteristics
6.3.17
STM32L151xD STM32L152xD
Communications interfaces
I2C interface characteristics
The device I2C interface meets the requirements of the standard I2C communication
protocol with the following restrictions: SDA and SCL are not “true” open-drain I/O pins.
When configured as open-drain, the PMOS connected between the I/O pin and VDD is
disabled, but is still present.
The I2C characteristics are described in Table 55. Refer also to Section 6.3.14: I/O port
characteristics for more details on the input/output ction characteristics (SDA and SCL).
Table 55. I2C characteristics
Symbol
Parameter
Standard mode
I2C(1)(2)
Fast mode I2C(1)(2)
Unit
Min
Max
Min
Max
tw(SCLL)
SCL clock low time
4.7
-
1.3
-
tw(SCLH)
SCL clock high time
4.0
-
0.6
-
tsu(SDA)
SDA setup time
250
-
100
-
th(SDA)
SDA data hold time
-
3450(3)
-
900(3)
tr(SDA)
tr(SCL)
SDA and SCL rise time
-
1000
-
300
tf(SDA)
tf(SCL)
SDA and SCL fall time
-
300
-
300
th(STA)
Start condition hold time
4.0
-
0.6
-
tsu(STA)
Repeated Start condition
setup time
4.7
-
0.6
-
tsu(STO)
Stop condition setup time
4.0
-
0.6
-
μs
tw(STO:STA)
Stop to Start condition time
(bus free)
4.7
-
1.3
-
μs
Cb
Capacitive load for each bus
line
-
400
-
400
pF
tSP
Pulse width of spikes that
are suppressed by the
analog filter
0
50(4)
0
50(4)
ns
µs
ns
µs
1. Guaranteed by design, not tested in production.
2. fPCLK1 must be at least 2 MHz to achieve standard mode I²C frequencies. It must be at least 4 MHz to
achieve fast mode I²C frequencies. It must be a multiple of 10 MHz to reach the 400 kHz maximum I²C fast
mode clock.
3. The maximum Data hold time has only to be met if the interface does not stretch the low period of SCL
signal.
4. The minimum width of the spikes filtered by the analog filter is above tSP(max).
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Electrical characteristics
Figure 28. I2C bus AC waveforms and measurement circuit
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1. RS = series protection resistor.
2. RP = external pull-up resistor.
3. VDD_I2C is the I2C bus power supply.
4. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
Table 56. SCL frequency (fPCLK1= 32 MHz, VDD = VDD_I2C = 3.3 V)(1)(2)
I2C_CCR value
fSCL (kHz)
RP = 4.7 kΩ
400
0x801B
300
0x8024
200
0x8035
100
0x00A0
50
0x0140
20
0x0320
1. RP = External pull-up resistance, fSCL = I2C speed.
2. For speeds around 200 kHz, the tolerance on the achieved speed is of ±5%. For other speed ranges, the
tolerance on the achieved speed is ±2%. These variations depend on the accuracy of the external
components used to design the application.
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Electrical characteristics
STM32L151xD STM32L152xD
SPI characteristics
Unless otherwise specified, the parameters given in the following table are derived from
tests performed under the conditions summarized in Table 13.
Refer to Section 6.3.13: I/O current injection characteristics for more details on the
input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 57. SPI characteristics(1)
Symbol
Min
Max(2)
Master mode
-
16
Slave mode
-
16
Slave transmitter
-
12(3)
-
6
ns
%
Parameter
Conditions
fSCK
1/tc(SCK)
SPI clock frequency
tr(SCK)(2)
tf(SCK)(2)
SPI clock rise and fall time
Capacitive load: C = 30 pF
SPI slave input clock duty cycle
Slave mode
30
70
tsu(NSS)
NSS setup time
Slave mode
4tHCLK
-
th(NSS)
NSS hold time
Slave mode
2tHCLK
-
SCK high and low time
Master mode
tSCK/2−5
tSCK/2+3
Master mode
5
-
Slave mode
6
-
Master mode
5
-
Slave mode
5
-
DuCy(SCK)
tw(SCKH)(2)
tw(SCKL)(2)
tsu(MI)(2)
tsu(SI)(2)
th(MI)
th(SI)
Data input setup time
(2)
(2)
Data input hold time
ta(SO)(4)
Data output access time
Slave mode
0
3tHCLK
tv(SO) (2)
Data output valid time
Slave mode
-
33
(2)
Data output valid time
Master mode
-
6.5
Slave mode
17
-
Master mode
0.5
-
tv(MO)
th(SO)
(2)
th(MO)(2)
Data output hold time
Unit
MHz
ns
1. The characteristics above are given for voltage range 1.
2. Guaranteed by characterization results, not tested in production.
3. The maximum SPI clock frequency in slave transmitter mode is given for an SPI slave input clock duty cycle (DuCy(SCK))
ranging between 40 to 60%.
4. Min time is for the minimum time to drive the output and max time is for the maximum time to validate the data.
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Electrical characteristics
Figure 29. SPI timing diagram - slave mode and CPHA = 0
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Figure 30. SPI timing diagram - slave mode and CPHA = 1(1)
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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130
Electrical characteristics
STM32L151xD STM32L152xD
Figure 31. SPI timing diagram - master mode(1)
(IGH
.33INPUT
3#+/UTPUT
#0(! #0/,
3#+/UTPUT
TC3#+
#0(!
#0/,
#0(! #0/,
#0(!
#0/,
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1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Electrical characteristics
USB characteristics
The USB interface is USB-IF certified (full speed).
Table 58. USB startup time
Symbol
tSTARTUP
Parameter
(1)
USB transceiver startup time
Max
Unit
1
µs
1. Guaranteed by design, not tested in production.
Table 59. USB DC electrical characteristics
Symbol
Parameter
Conditions
Min.(1)
Max.(1)
Unit
-
3.0
3.6
V
0.2
-
Input levels
VDD
USB operating voltage
VDI(2)
Differential input sensitivity
VCM(2)
Differential common mode range Includes VDI range
0.8
2.5
VSE(2)
Single ended receiver threshold
1.3
2.0
-
0.3
2.8
3.6
I(USB_DP, USB_DM)
-
V
Output levels
VOL(3)
VOH
RL of 1.5 kΩ to 3.6 V(4)
Static output level low
(3)
Static output level high
RL of 15 kΩ to VSS
(4)
V
1. All the voltages are measured from the local ground potential.
2. Guaranteed by characterization results, not tested in production.
3. Guaranteed by test in production.
4. RL is the load connected on the USB drivers.
Figure 32. USB timings: definition of data signal rise and fall time
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Table 60. USB: full speed electrical characteristics
Driver characteristics(1)
Symbol
Parameter
Conditions
Min
Max
Unit
tr
Rise time(2)
CL = 50 pF
4
20
ns
tf
Time(2)
CL = 50 pF
4
20
ns
Fall
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Electrical characteristics
STM32L151xD STM32L152xD
Table 60. USB: full speed electrical characteristics (continued)
Driver characteristics(1)
Symbol
trfm
VCRS
Parameter
Conditions
Min
Max
Unit
tr/tf
90
110
%
1.3
2.0
V
Rise/ fall time matching
Output signal crossover voltage
1. Guaranteed by design, not tested in production.
2. Measured from 10% to 90% of the data signal. For more detailed informations, please refer to USB
Specification - Chapter 7 (version 2.0).
I2S characteristics
Table 61. I2S characteristics
Symbol
fMCK
Parameter
Conditions
Min
Max
256 x 8K 256xFs (1)
I2S Main Clock Output
Master data: 32 bits
-
64xFs
Slave data: 32 bits
-
64xFs
30
70
fCK
I2S clock frequency
DCK
I2S clock frequency duty cycle Slave receiver, 48KHz
tr(CK)
I2S clock rise time
tf(CK)
I2S clock fall time
tv(WS)
-
WS valid time
Master mode
4
24
th(WS)
WS hold time
Master mode
0
-
tsu(WS)
WS setup time
Slave mode
15
-
th(WS)
WS hold time
Slave mode
0
-
tsu(SD_MR) Data input setup time
Master receiver
8
-
tsu(SD_SR) Data input setup time
Slave receiver
9
-
th(SD_MR)
Master receiver
5
-
Slave receiver
4
-
th(SD_SR)
MHz
MHz
%
8
Capacitive load CL=30pF
Data input hold time
Unit
8
tv(SD_ST)
Data output valid time
Slave transmitter
(after enable edge)
-
64
th(SD_ST)
Data output hold time
Slave transmitter
(after enable edge)
22
-
tv(SD_MT) Data output valid time
Master transmitter
(after enable edge)
-
12
th(SD_MT) Data output hold time
Master transmitter
(after enable edge)
8
-
ns
1. The maximum for 256xFs is 8 MHz
Note:
116/154
Refer to the I2S section of the product reference manual for more details about the sampling
frequency (Fs), fMCK, fCK and DCK values. These values reflect only the digital peripheral
behavior, source clock precision might slightly change them. DCK depends mainly on the
DocID022027 Rev 10
STM32L151xD STM32L152xD
Electrical characteristics
ODD bit value, digital contribution leads to a min of (I2SDIV/(2*I2SDIV+ODD) and a max of
(I2SDIV+ODD)/(2*I2SDIV+ODD). Fs max is supported for each mode/condition.
Figure 33. I2S slave timing diagram (Philips protocol)(1)
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1. Measurement points are done at CMOS levels: 0.3 × VDD and 0.7 × VDD.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
Figure 34. I2S master timing diagram (Philips protocol)(1)
TF#+
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TC#+
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TW#+(
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TV73
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AIB
1. Guaranteed by characterization results, not tested in production.
2. LSB transmit/receive of the previously transmitted byte. No LSB transmit/receive is sent before the first
byte.
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130
Electrical characteristics
6.3.18
STM32L151xD STM32L152xD
SDIO characteristics
Table 62. SDIO characteristics(1)
Symbol
fPP
tW(CKL)
Parameter
Conditions
Min
Max
Unit
Clock frequency in data transfer mode
CL ≤30 pF
0
24
MHz
Clock low time, fPP = 24 MHz
CL ≤30 pF
tW(CKH) Clock high time, fPP = 24 MHz
(2)
-
CL ≤30 pF
(2)
18
-
20
tr
Clock rise time, fPP = 24 MHz
CL ≤30 pF
-
5
tf
Clock fall time, fPP = 24 MHz
CL ≤30 pF
-
5
ns
CMD, D inputs (referenced to CK) in SD default mode
-
From 2.8
to 3.6 V
-
tISU
Input setup time, fPP = 24 MHz
CL ≤30 pF
2
-
tIH
Input hold time, fPP = 24 MHz
CL ≤30 pF
1.6
-
ns
CMD, D outputs (referenced to CK) in SD default mode
tOVD
Output valid default time, fPP = 24 MHz
CL ≤30 pF
0
14
tOHD
Output hold default time, fPP = 24 MHz
CL ≤30 pF
0
-
ns
1. Guaranteed by characterization results, not tested in production.
2. Values measured with a threshold level equal to VDD/2.
Figure 35. SDIO timings
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6.3.19
Electrical characteristics
12-bit ADC characteristics
Unless otherwise specified, the parameters given in Table 64 are guaranteed by design.
Table 63. ADC clock frequency
Symbol
fADC
Parameter
ADC clock
frequency
Conditions
2.4 V ≤VDDA ≤3.6 V
Voltage
range 1 & 2
Min
VREF+ = VDDA
16
VREF+ < VDDA
VREF+ > 2.4 V
8
VREF+ < VDDA
VREF+ ≤2.4 V
1.8 V ≤VDDA ≤2.4 V
Max
0.480
4
VREF+ = VDDA
8
VREF+ < VDDA
4
Voltage range 3
Unit
MHz
4
Table 64. ADC characteristics
Symbol
VDDA
Parameter
Power supply
Conditions
Min
Typ
Max
-
1.8
-
3.6
-
VDDA
VREF+
Positive reference voltage
-
1.8(1)
VREF-
Negative reference voltage
-
-
VSSA
-
IVDDA
Current on the VDDA input pin
-
-
1000
1450
Peak
-
Average
-
-
0(4)
-
VREF+
Direct channels
-
-
1
Multiplexed channels
-
-
0.76
Direct channels
-
-
1.07
Multiplexed channels
-
-
0.8
Direct channels
-
-
1.23
Multiplexed channels
-
-
0.89
Direct channels
-
-
1.45
Multiplexed channels
-
-
1
IVREF(2)
VAIN
Current on the VREF input pin
Conversion voltage range(3)
12-bit sampling rate
10-bit sampling rate
fS
8-bit sampling rate
6-bit sampling rate
DocID022027 Rev 10
400
700
Unit
V
µA
450
V
Msps
Msps
Msps
Msps
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Electrical characteristics
STM32L151xD STM32L152xD
Table 64. ADC characteristics (continued)
Symbol
tS(5)
Parameter
Sampling time
tCONV
Total conversion time
(including sampling time)
CADC
Internal sample and hold
capacitor
fTRIG
External trigger frequency
Regular sequencer
fTRIG
External trigger frequency
Injected sequencer
RAIN(6)
Signal source impedance
Conditions
Min
Typ
Max
Direct channels
2.4 V ≤VDDA ≤3.6 V
0.25
-
-
Multiplexed channels
2.4 V ≤VDDA ≤3.6 V
0.56
-
-
Direct channels
1.8 V ≤VDDA ≤2.4 V
0.56
-
-
Multiplexed channels
1.8 V ≤VDDA ≤2.4 V
1
-
-
-
4
-
384
1/fADC
fADC = 16 MHz
1
-
24.75
µs
-
Unit
µs
4 to 384 (sampling phase) +12
(successive approximation)
1/fADC
Direct channels
-
Multiplexed channels
-
12-bit conversions
-
-
6/8/10-bit conversions
-
-
12-bit conversions
-
-
Tconv+2 1/fADC
6/8/10-bit conversions
-
-
Tconv+1 1/fADC
-
-
50
kΩ
16
-
pF
-
Tconv+1 1/fADC
Tconv
1/fADC
tlat
Injection trigger conversion
latency
fADC = 16 MHz
219
-
281
ns
-
3.5
-
4.5
1/fADC
tlatr
Regular trigger conversion
latency
fADC = 16 MHz
156
-
219
ns
-
2.5
-
3.5
1/fADC
-
-
-
3.5
µs
tSTAB
Power-up time
1. The Vref+ input can be grounded if neither the ADC nor the DAC are used (this allows to shut down an external voltage
reference).
2. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
3. VREF+ can be internally connected to VDDA and VREF- can be internally connected to VSSA, depending on the package.
Refer to Section 4: Pin descriptions for further details.
4. VSSA or VREF- must be tied to ground.
5. Minimum sampling time is reached for an external input impedance limited to a value as defined in Table 66: Maximum
source impedance RAIN max
6. External impedance has another high value limitation when using short sampling time as defined in Table 66: Maximum
source impedance RAIN max
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Electrical characteristics
Table 65. ADC accuracy(1)(2)
Symbol
Parameter
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
ENOB
Effective number of bits
SINAD
Signal-to-noise and
distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
ENOB
Effective number of bits
SINAD
Signal-to-noise and
distortion ratio
SNR
Signal-to-noise ratio
THD
Total harmonic distortion
Test conditions
2.4 V ≤ VDDA ≤ 3.6 V
2.4 V ≤ VREF+ ≤ 3.6 V
fADC = 8 MHz, RAIN = 50 Ω
TA = -40 to 105 ° C
2.4 V ≤ VDDA ≤ 3.6 V
VDDA = VREF+
fADC = 16 MHz, RAIN = 50 Ω
TA = -40 to 105 ° C
Finput=10kHz
1.8 V ≤ VDDA ≤ 2.4 V
VDDA = VREF+
fADC = 8 MHz or 4 MHz, RAIN = 50 Ω
TA = -40 to 105 ° C
Finput=10kHz
Min(3)
Typ
Max(3)
-
2
4
-
1
2
-
1.5
3.5
-
1
2
-
1.7
3
9.2
10
-
57.5
62
-
57.5
62
-
-
-70
-65
9.2
10
-
57.5
62
-
57.5
62
-
-
-70
-65
-
4
6.5
-
2
4
-
4
6
-
1
2
ET
Total unadjusted error
EO
Offset error
EG
Gain error
ED
Differential linearity error
EL
Integral linearity error
-
1.5
3
ET
Total unadjusted error
-
2
3
EO
Offset error
-
1
1.5
EG
Gain error
-
1.5
2
ED
Differential linearity error
-
1
2
EL
Integral linearity error
-
1
1.5
2.4 V ≤ VDDA ≤ 3.6 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 ° C
1.8 V ≤ VDDA ≤ 2.4 V
1.8 V ≤ VREF+ ≤ 2.4 V
fADC = 4 MHz, RAIN = 50 Ω
TA = -40 to 105 ° C
Unit
LSB
bits
dB
bits
dB
LSB
LSB
1. ADC DC accuracy values are measured after internal calibration.
2. ADC accuracy vs. negative injection current: Injecting a negative current on any analog input pins should be avoided as
this significantly reduces the accuracy of the conversion being performed on another analog input. It is recommended to
add a Schottky diode (pin to ground) to analog pins which may potentially inject negative currents.
Any positive injection current within the limits specified for IINJ(PIN) and ΣIINJ(PIN) in Section 6.3.13 does not affect the ADC
accuracy.
3. Guaranteed by characterization results, not tested in production.
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Electrical characteristics
STM32L151xD STM32L152xD
Figure 36. ADC accuracy characteristics
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Figure 37. Typical connection diagram using the ADC
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1. Refer to Table 66: Maximum source impedance RAIN max for the value of RAIN and Table 64: ADC
characteristics for the value of CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
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Electrical characteristics
Figure 38. Maximum dynamic current consumption on VREF+ supply pin during ADC
conversion
Sampling (n cycles)
Conversion (12 cycles)
ADC clock
Iref+
700µA
300µA
MS36686V1
Table 66. Maximum source impedance RAIN max(1)
RAIN max (kΩ)
Ts
(µs)
Multiplexed channels
Ts (cycles)
Direct channels
fADC=16 MHz(2)
2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V 2.4 V < VDDA < 3.6 V 1.8 V < VDDA < 2.4 V
0.25
Not allowed
Not allowed
0.7
Not allowed
4
0.5625
0.8
Not allowed
2.0
1.0
9
1
2.0
0.8
4.0
3.0
16
1.5
3.0
1.8
6.0
4.5
24
3
6.8
4.0
15.0
10.0
48
6
15.0
10.0
30.0
20.0
96
12
32.0
25.0
50.0
40.0
192
24
50.0
50.0
50.0
50.0
384
1. Guaranteed by design, not tested in production.
2. Number of samples calculated for fADC = 16 MHz. For fADC = 8 and 4 MHz the number of sampling cycles can be reduced
with respect to the minimum sampling time Ts (µs),
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 11. The applicable
procedure depends on whether VREF+ is connected to VDDA or not. The 100 nF capacitors
should be ceramic (good quality). They should be placed as close as possible to the chip.
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Electrical characteristics
6.3.20
STM32L151xD STM32L152xD
DAC electrical specifications
Data guaranteed by design, not tested in production, unless otherwise specified.
Table 67. DAC characteristics
Symbol
Parameter
Conditions
VDDA
Analog supply voltage
VREF+
Reference supply
voltage
VREF-
Lower reference voltage
IDDVREF+(1)
Current consumption on No load, middle code (0x800)
VREF+ supply
No load, worst code (0x000)
VREF+ = 3.3 V
IDDA(1)
Current consumption on No load, middle code (0x800)
VDDA supply
No load, worst code (0xF1C)
VDDA = 3.3 V
RL(2)
Resistive load
CL
(2)
Capacitive load
Output impedance
RO
VDAC_OUT
DNL
(1)
(1)
INL
Offset(1)
Offset1(1)
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VREF+ must always be below
VDDA
Min
Typ
Max
1.8
-
3.6
1.8
-
3.6
Unit
V
VSSA
-
130
220
-
220
350
-
210
320
-
320
520
5
-
-
kΩ
-
-
50
pF
DAC output buffer OFF
12
16
20
kΩ
DAC output buffer ON
0.2
-
VDDA – 0.2
V
DAC output buffer OFF
0.5
-
VREF+ –
1LSB
mV
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
1.5
3
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
1.5
3
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
2
4
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
2
4
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
±10
±25
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
±5
±8
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
±1.5
±5
DAC output buffer ON
µA
Voltage on DAC_OUT
output
Differential non
linearity(3)
Integral non
linearity(4)
Offset error at code
0x800 (5)
Offset error at code
0x001(6)
DocID022027 Rev 10
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STM32L151xD STM32L152xD
Electrical characteristics
Table 67. DAC characteristics (continued)
Symbol
Parameter
Conditions
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer OFF
Offset
error
temperature
dOffset/dT(1)
coefficient (code 0x800) V
= 3.3V
Min
Typ
Max
-20
-10
0
Unit
µV/°C
DDA
VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer ON
0
20
50
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
+0.1 / -0.2%
+0.2 / -0.5%
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
+0 / -0.2%
+0 / -0.4%
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer OFF
-10
-2
0
VDDA = 3.3V
VREF+ = 3.0V
TA = 0 to 50 ° C
DAC output buffer ON
-40
-8
0
CL ≤ 50 pF, RL ≥ 5 kΩ
DAC output buffer ON
-
12
30
No RL, CL ≤ 50 pF
DAC output buffer OFF
-
8
12
tSETTLING
Settling time (full scale:
for a 12-bit code
transition between the
lowest and the highest
CL ≤ 50 pF, RL ≥ 5 kΩ
input codes till
DAC_OUT reaches final
value ±1LSB
-
7
12
µs
Update rate
Max frequency for a
correct DAC_OUT
change (95% of final
value) with 1 LSB
variation in the input
code
CL ≤ 50 pF, RL ≥ 5 kΩ
-
-
1
Msps
tWAKEUP
Wakeup time from off
state (setting the ENx bit
CL ≤ 50 pF, RL ≥ 5 kΩ
in the DAC Control
(8)
register)
-
9
15
µs
PSRR+
VDDA supply rejection
ratio (static DC
measurement)
-
-60
-35
dB
Gain(1)
dGain/dT(1)
TUE(1)
Gain error(7)
Gain error temperature
coefficient
Total unadjusted error
CL ≤ 50 pF, RL ≥ 5 kΩ
%
µV/°C
LSB
1. Data based on characterization results.
2. Connected between DAC_OUT and VSSA.
3. Difference between two consecutive codes - 1 LSB.
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Electrical characteristics
STM32L151xD STM32L152xD
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 4095.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between ideal slope of the transfer function and measured slope computed from code 0x000 and 0xFFF when
buffer is OFF, and from code giving 0.2 V and (VDDA – 0.2) V when buffer is ON.
8. In buffered mode, the output can overshoot above the final value for low input code (starting from min value).
Figure 39. 12-bit buffered /non-buffered DAC
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1. The DAC integrates an output buffer that can be used to reduce the output impedance and to drive external
loads directly without the use of an external operational amplifier. The buffer can be bypassed by
configuring the BOFFx bit in the DAC_CR register.
6.3.21
Operational amplifier characteristics
Table 68. Operational amplifier characteristics
Symbol
CMIR
VIOFFSET
Condition(1)
Min(2)
Typ
Max(2)
-
0
-
VDD
Maximum
calibration range
-
-
-
±15
After offset
calibration
-
-
-
±1.5
-
-
-
±40
-
-
-
±80
-
-
1
-
-
10
Parameter
Common mode input range
Input offset voltage
ΔVIOFFSET
Input offset voltage Normal mode
drift
Low-power mode
IIB
Input current bias
ILOAD
Drive current
IDD
Consumption
CMRR
Common mode
rejection ration
mV
Dedicated input
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General purpose
input
75 °C
Normal mode
-
-
-
500
Low-power mode
-
-
-
100
-
100
220
-
30
60
Normal mode
Low-power mode
Unit
No load,
quiescent mode
Normal mode
-
-
-85
-
Low-power mode
-
-
-90
-
DocID022027 Rev 10
µV/°C
nA
µA
µA
dB
STM32L151xD STM32L152xD
Electrical characteristics
Table 68. Operational amplifier characteristics (continued)
Symbol
PSRR
Condition(1)
Parameter
Power supply
rejection ratio
Normal mode
Low-power mode
Normal mode
GBW
Bandwidth
Low-power mode
Normal mode
Low-power mode
SR
Slew rate
RL
Resistive load
CL
Capacitive load
VOHSAT
High saturation
voltage
VDD<2.4 V
Max(2)
-
-85
-
-
-90
-
400
1000
3000
150
300
800
200
500
2200
70
150
800
VDD>2.4 V
(between 0.1 V and
VDD-0.1 V)
-
700
-
Low-power mode
VDD>2.4 V
-
100
-
-
300
-
-
50
-
Normal mode
55
100
-
Low-power mode
65
110
-
4
-
-
20
-
-
-
-
50
VDD100
-
-
VDD-50
-
-
-
-
100
-
-
50
Low-power mode
Open loop gain
VDD>2.4 V
Typ
Normal mode
Normal mode
AO
DC
Min(2)
Normal mode
Low-power mode
VDD<2.4 V
VDD<2.4 V
-
Normal mode
Low-power mode
Normal mode
ILOAD = max or
RL = min
Unit
dB
kHZ
V/ms
dB
kΩ
pF
mV
VOLSAT
Low saturation
voltage
ϕm
Phase margin
-
-
60
-
°
GM
Gain margin
-
-
-12
-
dB
tOFFTRIM
Offset trim time: during calibration,
minimum time needed between two
steps to have 1 mV accuracy
-
-
1
-
ms
10
-
tWAKEUP
Low-power mode
Normal mode
CL ≤50 pf,
RL ≥ 4 kΩ
-
Low-power mode
CL ≤50 pf,
RL ≥ 20 kΩ
-
Wakeup time
µs
30
-
1. Operating conditions are limited to junction temperature (0 °C to 105 °C) when VDD is below 2 V. Otherwise to the full
ambient temperature range (-40 °C to 85 °C, -40 °C to 105 °C).
2. Guaranteed by characterization results, not tested in production.
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Electrical characteristics
6.3.22
STM32L151xD STM32L152xD
Temperature sensor characteristics
Table 69. Temperature sensor calibration values
Calibration value name
Description
Memory address
TS_CAL1
TS ADC raw data acquired at
temperature of 30 °C ±5 °C
VDDA= 3 V ±10 mV
0x1FF8 00FA - 0x1FF8 00FB
TS_CAL2
TS ADC raw data acquired at
temperature of 110 °C ±5 °C
VDDA= 3 V ±10 mV
0x1FF8 00FE - 0x1FF8 00FF
Table 70. Temperature sensor characteristics
Symbol
Parameter
TL(1)
VSENSE linearity with temperature
Avg_Slope(1)
Average slope
V110
Voltage at 110°C
I
±5°C(2)
Min
Typ
Max
Unit
-
±1
±2
°C
1.48
1.61
1.75
mV/°C
612
626.8
641.5
mV
µA
Current consumption
-
3.4
6
tSTART(3)
Startup time
-
-
10
TS_temp(3)
ADC sampling time when reading the
temperature
4
-
-
(3)
DDA(TEMP)
µs
1. Guaranteed by characterization results, not tested in production.
2. Measured at VDD = 3 V ±10 mV. V110 ADC conversion result is stored in the TS_CAL2 byte.
3. Guaranteed by design, not tested in production.
6.3.23
Comparator
Table 71. Comparator 1 characteristics
Symbol
Conditions
Min(1)
Typ
Max(1)
Unit
3.6
V
VDDA
Analog supply voltage
-
1.65
R400K
R400K value
-
-
400
-
R10K
R10K value
-
-
10
-
Comparator 1 input
voltage range
-
0.6
-
VDDA
Comparator startup time
-
-
7
10
VIN
tSTART
(2)
kΩ
V
µs
td
Propagation delay
-
-
3
10
Voffset
Comparator offset
-
-
±3
±10
mV
VDDA = 3.6 V
Comparator offset
VIN+ = 0 V
variation in worst voltage
VIN- = VREFINT
stress conditions
TA = 25 ° C
0
1.5
10
mV/1000 h
Current consumption(3)
-
160
260
nA
dVoffset/dt
ICOMP1
128/154
Parameter
-
DocID022027 Rev 10
STM32L151xD STM32L152xD
Electrical characteristics
1. Guaranteed by characterization results, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage not included.
Table 72. Comparator 2 characteristics
Symbol
VDDA
VIN
Parameter
Min
Analog supply voltage
-
1.65
-
3.6
V
Comparator 2 input voltage range
-
0
-
VDDA
V
Fast mode
-
15
20
Slow mode
-
20
25
1.65 V ≤VDDA ≤2.7 V
-
1.8
3.5
2.7 V ≤VDDA ≤3.6 V
-
2.5
6
1.65 V ≤VDDA ≤2.7 V
-
0.8
2
2.7 V ≤VDDA ≤3.6 V
-
1.2
4
-
±4
±20
mV
VDDA = 3.3V
TA = 0 to 50 ° C
V- =VREFINT,
3/4 VREFINT,
1/2 VREFINT,
1/4 VREFINT.
-
15
100
ppm
/°C
Fast mode
-
3.5
5
Slow mode
-
0.5
2
tSTART
Comparator startup time
td slow
Propagation delay(2) in slow mode
td fast
Propagation delay(2) in fast mode
Voffset
Comparator offset error
dThreshold/ Threshold voltage temperature
dt
coefficient
ICOMP2
Typ Max(1) Unit
Conditions
Current consumption(3)
µs
µA
1. Guaranteed by characterization results, not tested in production.
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the noninverting input set to the reference.
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
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Electrical characteristics
6.3.24
STM32L151xD STM32L152xD
LCD controller
The device embeds a built-in step-up converter to provide a constant LCD reference voltage
independently from the VDD voltage. An external capacitor Cext must be connected to the
VLCD pin to decouple this converter.
Table 73. LCD controller characteristics
Symbol
Parameter
Min
Typ
Max
Unit
VLCD
LCD external voltage
-
-
3.6
VLCD0
LCD internal reference voltage 0
-
2.6
-
VLCD1
LCD internal reference voltage 1
-
2.73
-
VLCD2
LCD internal reference voltage 2
-
2.86
-
VLCD3
LCD internal reference voltage 3
-
2.98
-
VLCD4
LCD internal reference voltage 4
-
3.12
-
VLCD5
LCD internal reference voltage 5
-
3.26
-
VLCD6
LCD internal reference voltage 6
-
3.4
-
VLCD7
LCD internal reference voltage 7
-
3.55
-
0.1
-
2
Supply current at VDD = 2.2 V
-
3.3
-
Supply current at VDD = 3.0 V
-
3.1
-
Low drive resistive network overall value
5.28
6.6
7.92
MΩ
High drive resistive network total value
192
240
288
kΩ
V
Cext
ILCD(1)
RHtot(2)
RL
(2)
VLCD external capacitance
V44
Segment/Common highest level voltage
-
-
VLCD
V34
Segment/Common 3/4 level voltage
-
3/4 VLCD
-
V23
Segment/Common 2/3 level voltage
-
2/3 VLCD
-
V12
Segment/Common 1/2 level voltage
-
1/2 VLCD
-
V13
Segment/Common 1/3 level voltage
-
1/3 VLCD
-
V14
Segment/Common 1/4 level voltage
-
1/4 VLCD
-
V0
Segment/Common lowest level voltage
0
-
-
Segment/Common level voltage error
TA = -40 to 105 ° C
-
-
± 50
ΔVxx(3)
V
µF
µA
V
mV
1. LCD enabled with 3 V internal step-up active, 1/8 duty, 1/4 bias, division ratio= 64, all pixels active, no LCD
connected.
2. Guaranteed by design, not tested in production.
3. Guaranteed by characterization results, not tested in production.
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7
Package information
Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
information
Figure 40. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package outline
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1. Drawing is not to scale.
DocID022027 Rev 10
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153
Package information
STM32L151xD STM32L152xD
Table 74. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package mechanical
data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
21.800
22.000
22.200
0.8583
0.8661
0.8740
D1
19.800
20.000
20.200
0.7795
0.7874
0.7953
D3
-
17.500
-
-
0.6890
-
E
21.800
22.000
22.200
0.8583
0.8661
0.8740
E1
19.800
20.000
20.200
0.7795
0.7874
0.7953
E3
-
17.500
-
-
0.6890
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0°
3.5°
7°
0°
3.5°
7°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
132/154
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Package information
Figure 41. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package
recommended footprint
DLH
1. Dimensions are in millimeters.
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 42. LQFP144, 20 x 20 mm, 144-pin low-profile quad flat package top view
example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
DocID022027 Rev 10
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153
Package information
7.2
STM32L151xD STM32L152xD
LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
information
Figure 43. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package outline
MM
C
!
!
!
3%!4).'0,!.%
#
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+
CCC #
,
$
,
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0).
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%
%
%
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1. Drawing is not to scale.
Table 75. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical
data
inches(1)
millimeters
Symbol
134/154
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
15.800
16.000
16.200
0.6220
0.6299
0.6378
D1
13.800
14.000
14.200
0.5433
0.5512
0.5591
D3
-
12.000
-
-
0.4724
-
E
15.800
16.000
16.200
0.6220
0.6299
0.6378
E1
13.800
14.000
14.200
0.5433
0.5512
0.5591
DocID022027 Rev 10
STM32L151xD STM32L152xD
Package information
Table 75. LQPF100, 14 x 14 mm, 100-pin low-profile quad flat package mechanical
data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E3
-
12.000
-
-
0.4724
-
e
-
0.500
-
-
0.0197
-
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
k
0.0°
3.5°
7.0°
0.0°
3.5°
7.0°
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 44. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package
recommended footprint
069
1. Dimensions are in millimeters.
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153
Package information
STM32L151xD STM32L152xD
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 45. LQFP100, 14 x 14 mm, 100-pin low-profile quad flat package top view
example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
136/154
DocID022027 Rev 10
STM32L151xD STM32L152xD
LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
information
Figure 46. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package outline
PP
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Package information
H
:B0(B9
1. Drawing is not to scale.
Table 76. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical
data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
-
-
1.600
-
-
0.0630
A1
0.050
-
0.150
0.0020
-
0.0059
A2
1.350
1.400
1.450
0.0531
0.0551
0.0571
b
0.170
0.220
0.270
0.0067
0.0087
0.0106
c
0.090
-
0.200
0.0035
-
0.0079
D
-
12.000
-
-
0.4724
-
D1
-
10.000
-
-
0.3937
-
D3
-
7.500
-
-
0.2953
-
E
-
12.000
-
-
0.4724
-
E1
-
10.000
-
-
0.3937
-
DocID022027 Rev 10
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153
Package information
STM32L151xD STM32L152xD
Table 76. LQFP64, 10 x 10 mm 64-pin low-profile quad flat package mechanical data
(continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
E3
-
7.500
-
-
0.2953
-
e
-
0.500
-
-
0.0197
-
K
0°
3.5°
7°
0°
3.5°
7°
L
0.450
0.600
0.750
0.0177
0.0236
0.0295
L1
-
1.000
-
-
0.0394
-
ccc
-
-
0.080
-
-
0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 47. LQFP64, 10 x 10 mm, 64-pin low-profile quad flat package
recommended footprint
AIC
1. Dimensions are in millimeters.
138/154
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STM32L151xD STM32L152xD
Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Figure 48. LQFP64 10 x 10 mm, 64-pin low-profile quad flat package top view example
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1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
DocID022027 Rev 10
139/154
153
Package information
7.4
STM32L151xD STM32L152xD
UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid
array package information
Figure 49. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
outline
= 6HDWLQJSODQH
GGG =
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1. Drawing is not to scale.
Table 77. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array
package mechanical data
inches(1)
millimeters
Symbol
140/154
Min
Typ
Max
Min
Typ
Max
A
0.460
0.530
0.600
0.0181
0.0209
0.0236
A1
0.050
0.080
0.110
0.0020
0.0031
0.0043
A2
0.400
0.450
0.500
0.0157
0.0177
0.0197
A3
0.270
0.320
0.370
0.0106
0.0126
0.0146
b
0.170
0.280
0.330
0.0067
0.0110
0.0130
D
6.950
7.000
7.050
0.2736
0.2756
0.2776
E
6.950
7.000
7.050
0.2736
0.2756
0.2776
e
-
0.500
-
-
0.0197
-
F
0.700
0.750
0.800
0.0276
0.0295
0.0315
ddd
-
-
0.080
-
-
0.0031
DocID022027 Rev 10
STM32L151xD STM32L152xD
Package information
Table 77. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array
package mechanical data (continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
eee
-
-
0.150
-
-
0.0059
fff
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Figure 50. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
recommended footprint
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DocID022027 Rev 10
141/154
153
Package information
STM32L151xD STM32L152xD
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 51. UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch ball grid array package
top view example
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5
06Y9
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
142/154
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STM32L151xD STM32L152xD
7.5
Package information
WLCSP64, 0.4 mm pitch wafer level chip scale package
information
Figure 52. WLCSP64, 0.4 mm pitch wafer level chip scale package outline
H
EEE =
)
*
$
'HWDLO$
H
H
+
*
H
$
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1. Drawing is not to scale.
Table 78. WLCSP64, 0.4 mm pitch wafer level chip scale package mechanical
data
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
A
0.540
0.570
0.600
0.0205
0.0224
0.0236
A1
-
0.190
-
-
0.0075
-
A2
-
0.380
-
-
0.0150
-
DocID022027 Rev 10
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153
Package information
STM32L151xD STM32L152xD
Table 78. WLCSP64, 0.4 mm pitch wafer level chip scale package mechanical data
(continued)
inches(1)
millimeters
Symbol
Min
Typ
Max
Min
Typ
Max
b(2)
0.240
0.270
0.300
0.0094
0.0106
0.0118
D
4.504
4.539
4.574
0.1773
0.1787
0.1801
E
4.876
4.911
4.946
0.1920
0.1933
0.1947
e
-
0.400
-
-
0.0157
-
e1
-
2.800
-
-
0.1102
-
F
-
0.870
-
-
0.0343
-
G
-
1.056
-
-
0.0416
-
aaa
-
-
0.100
-
-
0.0039
bbb
-
-
0.100
-
-
0.0039
ccc
-
-
0.100
-
-
0.0039
ddd
-
-
0.050
-
-
0.0020
eee
-
-
0.050
-
-
0.0020
1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
Figure 53. WLCSP64, 0.4 mm pitch wafer level chip scale package
recommended footprint
'SDG
'VP
069
Table 79. WLCSP64, 0.4 mm pitch package recommended PCB design rules
Dimension
Recommended values
Pitch
0.4
Dpad
144/154
260 µm max. (circular)
220 µm recommended
Dsm
300 µm min. (for 260 µm diameter pad)
PCB pad design
Non-solder mask defined via underbump allowed.
DocID022027 Rev 10
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Package information
Marking of engineering samples
The following figure gives an example of topside marking orientation versus ball A1 identifier
location.
Figure 54. WLCSP64, 0.4 mm pitch wafer level chip scale package top view example
3URGXFWLGHQWLILFDWLRQ
-3%
'DWHFRGH
5HYLVLRQFRGH
: 88 3
%DOO$
LGHQWLILHU
069
1. Parts marked as “ES”, “E” or accompanied by an Engineering Sample notification letter, are not yet
qualified and therefore not yet ready to be used in production and any consequences deriving from such
usage will not be at ST charge. In no event, ST will be liable for any customer usage of these engineering
samples in production. ST Quality has to be contacted prior to any decision to use these Engineering
samples to run qualification activity
DocID022027 Rev 10
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153
Package information
7.6
STM32L151xD STM32L152xD
Thermal characteristics
The maximum chip-junction temperature, TJ max, in degrees Celsius, may be calculated
using the following equation:
TJ max = TA max + (PD max × ΘJA)
Where:
•
TA max is the maximum ambient temperature in ° C,
•
ΘJA is the package junction-to-ambient thermal resistance, in ° C/W,
•
PD max is the sum of PINT max and PI/O max (PD max = PINT max + PI/Omax),
•
PINT max is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
PI/O max represents the maximum power dissipation on output pins where:
PI/O max = Σ (VOL × IOL) + Σ((VDD – VOH) × IOH),
taking into account the actual VOL / IOL and VOH / IOH of the I/Os at low and high level in the
application.
Table 80. Thermal characteristics
Symbol
ΘJA
146/154
Parameter
Value
Thermal resistance junction-ambient
LQFP144 - 20 x 20 mm / 0.5 mm pitch
40
Thermal resistance junction-ambient
UFBGA132 - 7 x 7 mm
60
Thermal resistance junction-ambient
LQFP100 - 14 x 14 mm / 0.5 mm pitch
43
Thermal resistance junction-ambient
LQFP64 - 10 x 10 mm / 0.5 mm pitch
46
Thermal resistance junction-ambient
WLCSP64 - 0.400 mm pitch
46
DocID022027 Rev 10
Unit
°C/W
STM32L151xD STM32L152xD
Package information
Figure 55. Thermal resistance suffix 6
&ŽƌďŝĚĚĞŶĂƌĞĂd:хd:ŵĂdž
3'P:
/4)3[PP:/&63
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069
Figure 56. Thermal resistance suffix 7
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/4)3[PP:/&63
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7.6.1
Reference document
JESD51-2 Integrated Circuits Thermal Test Method Environment Conditions - Natural
Convection (Still Air). Available from www.jedec.org.
DocID022027 Rev 10
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153
Part numbering
8
STM32L151xD STM32L152xD
Part numbering
Table 81. Ordering information scheme
Example:
STM32
L 151 R
D
T
6
D TR
Device family
STM32 = ARM-based 32-bit microcontroller
Product type
L = Low-power
Device subfamily
151: Devices without LCD
152: Devices with LCD
Pin count
R = 64 pins
V = 100 pins
Z = 144 pins
Q = 132 pins
Flash memory size
D=384 Kbytes of Flash memory
Package
H = BGA
T = LQFP
Y = WLCSP
Temperature range
6 = Industrial temperature range, –40 to 85 °C
7 = Industrial temperature range, –40 to 105 °C
Options
No character = VDD range: 1.8 to 3.6 V and BOR enabled
D = VDD range: 1.65 to 3.6 V and BOR disabled
Packing
TR = tape and reel
No character = tray or tube
For a list of available options (speed, package, etc.) or for further information on any aspect
of this device, please contact your nearest ST sales office.
148/154
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9
Revision History
Revision History
Table 82. Document revision history
Date
Revision
03-Oct-2011
1
Initial release.
2
Status of the document changed (datasheet instead of preliminary
data).
Updated low power features on page 1.
Removed references to devices with 256 KB of Flash memory.
GPIOF replaced with GIOPH.
Added SDIO in Table 4: Ultra-low-power STM32L15xxD device
features and peripheral counts on page 12 and in Table 19: ction
input/output on page 86 (FSMC/SDIO instead of FSMC).
Table 4: Ultra-low-power STM32L15xxD device features and
peripheral counts: replaced STM32L15xWx with STM32L15xQx.
Figure 1: Ultra-low-power STM32L162xC block diagram: updated
legend.
Modified Section 3.4: Clock management on page 20.
Table 4: STM32L15xQD STM32L162QD UFBGA132 ballout: replaced
STM32L15xWC/D with STM32L15xQD.
Figure 3, Figure 3, Figure 4: updated titles.
Table 14: STM32L15xxD pin definitions: updated title, updated pins
PF0, PF1, PH2, PF12, PF13, PF14, PF15, PG0, PG1, PG12, PG15,
PD0, and PD1.
Table 19: ction input/output: Modified ction for PA13 and PA14;
removed EVENT OUT for PH2.
Figure 5: Memory map: removed the text “APB memory space”.
Modified Figure 8: Power supply scheme on page 46.
Modified Table 2: Functionalities depending on the operating power
supply range on page 15.
Table 18: Current consumption in Run mode, code with data
processing running from RAM: added footnote 3.
Table 19: Current consumption in Sleep mode: updated condition for
fHSE; added footnote 3.
Table 23: Typical and maximum current consumptions in Standby
mode: modified max values.
Table 64: USB DC electrical characteristics: removed two footnotes.
Modified Table 38: Flash memory and data EEPROM characteristics
on page 83.
Table 73: Thermal characteristics: updated “TBDs” with values.
Modified tables in Section 6.3.4: Supply current characteristics on
page 54.
03-Feb-2012
Changes
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153
Revision History
STM32L151xD STM32L152xD
Table 82. Document revision history (continued)
Date
18-Apr-2012
15-Jun-2012
150/154
Revision
Changes
3
Added WLCSP64 package.
Section 3: Functional overview: changed ‘128 kHz’ to ‘131 kHz’ in
section “Low power run mode”.
Section 3.17.1: General-purpose timers (TIM2, TIM3, TIM4, TIM5,
TIM9, TIM10 and TIM11): changed ‘six’ to ‘seven’ synchronizable
general-purpose timers.
Table 14: STM32L15xxD pin definitions on page 52: updated name of
reference manual in footnote 5.
I2C updated: footnote 3. from Table 58
Note about I2C clock updated: footnote 2. from Table 58 modified.
Note [non-robust] updated: footnote 2. from Table 68 modified.
GPIOs high current capability updated: Section 3.6: GPIOs (generalpurpose inputs/outputs) ‘except for analog inputs’ was removed.
4
Changed maximum number of touch sensing channels to 34, and
updated Table 4: Ultra-low-power STM32L15xxD device features and
peripheral counts.
Updated Section 3.10: ADC (analog-to-digital converter) to add
Section 3.10.1: Temperature sensor and Section 3.10.2: Internal
voltage reference (VREFINT).
Removed caution note below Figure 8: Power supply scheme.
Added note below Table 4: STM32L15xQD STM32L162QD
UFBGA132 ballout.
Modified Table 8: STM32L15xRDSTM32L162RD WLCSP64 ballout to
match top view.
Changed FSMC_LBAR into FSMC_NADV, and I2C1_SMBAI into
I2C1_SMBA in Table 14: STM32L15xxD pin definitions.
Modified PB10/11/12 for AFIO4 ction, and replaced LBAR by NADV for
AFIO12 in Table 19: ction input/output.
Updated Table 22: Typical and maximum current consumptions in Stop
mode and added Note 6. Updated Table 23: Typical and maximum
current consumptions in Standby mode. Updated tWUSTOP in Table : .
Updated Table 27: Peripheral current consumption.
Updated Table 60: SPI characteristics, added Note 1 and Note 3, and
applied Note 2 to tr(SCK), tf(SCK), tw(SCKH), tw(SCKL), tsu(MI), tsu(SI), th(MI),
and th(SI).
Updated IDD maximum value in Table 38: Flash memory and data
EEPROM characteristics.
DocID022027 Rev 10
STM32L151xD STM32L152xD
Revision History
Table 82. Document revision history (continued)
Date
25-Oct-2012
01-Feb-2013
Revision
Changes
5
Updated Features
Updated Figure 1: Ultra-low-power STM32L162xC block diagram
Added Table 4: Functionalities depending on the working mode (from
Run/active down to standby), and Table 3: ange depending on
dynamic voltage scaling
Updated Figure 3: STM32L162VC LQFP100 pinout
Updated Table 14: STM32L15xxD pin definitions
Added Note 2 in Table 15: Embedded reset and power control block
characteristics
Replaced TBD values in Table 30: Low-speed external user clock
characteristics, Table 38: Flash memory and data EEPROM
characteristics and Table 55: I/O AC characteristics
Added Table 61: I2S characteristics, Figure 29: I2S slave timing
diagram (Philips protocol)(1) and Figure 30: I2S master timing diagram
(Philips protocol)(1)
Added Table 62: SDIO characteristics
Added Figure 31: SDIO timings
Updated Section 6.3.9: FSMC characteristics
Updated Table 72: Temperature sensor characteristics
Added Figure 40: Thermal resistance
6
Removed AHB1/AHB2 and corrected typo on APB1/APB2 in Figure 1:
Ultra-low-power STM32L162xC block diagram
Updated “OP amp” line in Table 4: Functionalities depending on the
working mode (from Run/active down to standby)
Added IWDG and WWDG rows in Table 4: Functionalities depending
on the working mode (from Run/active down to standby)
Added OneNAND support in Section 3.8: FSMC (flexible static
memory controller)
The comment "HSE = 16 MHz(2) (PLL ON for fHCLK above 16 MHz)"
replaced by "fHSE = fHCLK up to 16 MHz included, fHSE = fHCLK/2
above 16 MHz (PLL ON)(2)” in table Table 19: Current consumption in
Sleep mode
Updated Stop mode current to 1.5 µA in Ultra low power platform
Replaced BGA132 by UFBGA132 in Table 4: Ultra-low-power
STM32L15xxD device features and peripheral counts
Replaced BGA132 by UFBGA132 in Figure 4:
STM32L15xQD STM32L162QD UFBGA132 ballout
Updated entire Section 7: Package characteristics
DocID022027 Rev 10
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153
Revision History
STM32L151xD STM32L152xD
Table 82. Document revision history (continued)
Date
07-Apr-2014
152/154
Revision
Changes
7
Updated current consumption in Section : Features.
Updated Section 2.2: Ultra-low-power device continuum.
Updated Table 3: Functionalities depending on the operating power
supply range..
Added VDD= 1.71 to 1.8 V operating power supply range in Table 5:
Functionalities depending on the working mode (from Run/active down
to standby).
Updated Section 3.10: LCD (liquid crystal display) to remove VLCD rail
decoupling.
Updated Section 3.16: Touch sensing.
Updated Figure 5: Pin loading conditions.
Updated Figure 6: Pin input voltage.
Updated Figure 11: Power supply scheme.
Updated Table 10: Voltage characteristics (added row).
Updated Table 11: Current characteristics.
Updated Table 13: General operating conditions. Removed figures
“Power supply and reference decoupling (VREF+ not connected to
VDDA) and “Power supply and reference decoupling (VREF+ connected
to VDDA).
Updated Table 15: Embedded internal reference voltage calibration
values and moved inside Section 6.3.3: Embedded internal reference
voltage.
Updated Section 6.3.4: Supply current characteristics.
Updated Table 17: Current consumption in Run mode, code with data
processing running from Flash, Table 18: Current consumption in Run
mode, code with data processing running from RAM, Table 19: Current
consumption in Sleep mode, Table 20: Current consumption in Lowpower run mode, Table 21: Current consumption in Low-power sleep
mode, Table 22: Typical and maximum current consumptions in Stop
mode, and Table 23: Typical and maximum current consumptions in
Standby mode.
Added Section 6.3.5: Wakeup time from low-power mode.
Updated Section 6.3.6: External clock source characteristics.
Moved Figure 14: High-speed external clock source AC timing diagram
after Table 26: High-speed external user clock characteristics.
Updated Figure 17: Typical application with a 32.768 kHz crystal.
Updated Table 28: HSE oscillator characteristics.
Updated Section 6.3.12: Electrical sensitivity characteristics (title).
Updated Section 6.3.13: I/O current injection characteristics. Updated
Table 49: I/O current injection susceptibility and added footnote.
Updated conditions in Table 51: Output voltage characteristics.
Updated Section 6.3.15: NRST pin characteristics.Updated Figure 27:
Recommended NRST pin protection. Updated Table 53: NRST pin
characteristics.
DocID022027 Rev 10
STM32L151xD STM32L152xD
Revision History
Table 82. Document revision history (continued)
Date
07-Apr-2014
Revision
Changes
Updated Figure 28: I2C bus AC waveforms and measurement circuit.
Updated “SDA data hold time” and “SDA and SCL rise time” values
and added “Pulse width of spikes that are suppressed by the analog
filter” row in Table 55: I2C characteristics.
Updated Table 64: ADC characteristics and Table 65: ADC accuracy.
Updated Table 67: DAC characteristics.
Updated Table 69: Temperature sensor calibration values and moved
7
inside Section 6.3.22: Temperature sensor characteristics. Removed
(continued)
note 4 in Table 70: Temperature sensor characteristics.
Updated Table 76: LQFP64, 10 x 10 mm 64-pin low-profile quad flat
package mechanical data and Table 77: UFBGA132, 7 x 7 mm, 132ball ultra thin, fine-pitch ball grid array package mechanical data.
Updated Section 8: Part numbering (title).
Added Table 50: UFBGA132, 7 x 7 mm, 132-ball ultra thin, fine-pitch
ball grid array package recommended footprint..
23-Oct-2014
8
Updated Section 3.18: Communication interfaces putting I2S
characteristics inside.
Updated DMIPS features in cover page and Section 2: Description.
Updated max temperature at 105°C instead of 85°C in the whole
datasheet.
Updated currents consumption in Table 19: Current consumption in
Sleep mode.
Updated Table 24: Peripheral current consumption with new measured
current values.
Updated Table 66: Maximum source impedance RAIN max adding
note 2.
04-Feb-2015
9
Updated Section 7: Package information with new package device
marking.
Updated Figure 8: Memory map.
10
Updated Section 7: Package information with new package paragraph
structure (paragraph title and heading level) and adding note for device
orientation versus pin 1/ ball A1 identifier.
Updated Figure 42: LQFP144, 20 x 20 mm, 144-pin low-profile quad
flat package top view example and Figure 45: LQFP100, 14 x 14 mm,
100-pin low-profile quad flat package top view example removing gate
mark.
Added Figure 53: WLCSP64, 0.4 mm pitch wafer level chip scale
package recommended footprint and Table 79: WLCSP64, 0.4 mm
pitch package recommended PCB design rules.
Updated Table 8: STM32L151xD and STM32L152xD pin definitions
ADC inputs.
Updated Table 16: Embedded internal reference voltage temperature
coefficient at 100ppm/°C.
Updated Table 72: Comparator 2 characteristics new maximum
threshold voltage temperature coefficient at 100ppm/°C.
02-Apr-2015
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