S i 5 3 3 11 1:6 L O W J I T T E R U NIVERSAL B UFFER /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX (<1.25 GH Z ) Features Ordering Information: See page 25. Applications Q2 Q3 Q3 Q4 Q4 27 26 25 DIVA 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 22 SFOUTB[0] Q0 4 Q0 5 GND 6 19 V DDOB VDD 7 18 VDDOA 8 17 V REF 14 15 16 CLK1 NC OEB 13 CLK_SEL GND PAD CLK1 The Si53311 is an ultra low jitter six output differential buffer with pin-selectable output clock signal format and divider selection. The Si53311 features a 2:1 mux, making it ideal for redundant clocking applications. The Si53311 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from 1 MHz to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53311 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. 28 Description 29 30 31 Si53311 32 Storage Telecom Industrial Servers Backplane clock distribution Q2 11 Pin Assignments High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 OEA 12 CLK0 Q1 Q1 9 Low output-output skew: <50 ps Low propagation delay variation: <400 ps Independent VDD and VDDO : 1.8/2.5/3.3 V Excellent power supply noise rejection (PSRR) Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 32-QFN (5 mm x 5 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C 10 6 differential or 12 LVCMOS outputs Ultra-low additive jitter: 100 fs rms Wide frequency range: 1 MHz to 1.25 GHz Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 mux with hot-swappable inputs Asynchronous output enable Output clock division: /1, /2, /4 NC CLK0 21 Q5 20 Q5 Patents pending Functional Block Diagram VREF Vref Generator Power Supply Filtering DIVA VDDOA SFOUTA[1:0] OEA Q0, Q1, Q2 DivA Q0, Q1, Q2 CLK0 CLK0 DIVB VDDOB SFOUTB[1:0] OEB Q3, Q4, Q5 CLK1 CLK1 CLK_SEL Preliminary Rev. 0.4 10/12 Switching Logic DivB Q3, Q4, Q5 Copyright © 2012 by Silicon Laboratories Si53311 This information applies to a product under development. Its characteristics and specifications are subject to change without notice. Si53311 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.3. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.4. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.5. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.6. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.7. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 2.10. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.11. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.12. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3. Pin Description: 32-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 5.1. 5x5 mm 32-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 6.1. 5x5 mm 32-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.1. Si53311 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 2 Preliminary Rev. 0.4 Si53311 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Range* Output Buffer Supply Voltage* Symbol Test Condition Min Typ Max Unit –40 — 85 °C LVDS, CML, HCSL, LVCMOS 1.71 1.8 1.89 V LVPECL, low power LVPECL, LVDS, CML, HCSL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVDS, CML, HCSL, LVCMOS 1.71 — 1.89 V LVPECL, low power LVPECL, LVDS, CML, HCSL, LVCMOS 2.38 — 2.63 V 2.97 — 3.63 V TA VDD VDDO *Note: Core supply VDD and output buffer supplies VDDO are independent. Table 2. Input Clock Specifications (VDD=1.8 V 5%, 2.5 V 5%, or 3.3 V 10%, TA=–40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V 5%, 3.3 V 10% 0.05 — — V Input Swing (single-ended, peak-topeak) VIN 0.1 — 1.1 V Input Voltage High VIH VDD x 0.7 — — V Input Voltage Low VIL — — VDD x 0.3 V Input Capacitance CIN — 5 — pF Preliminary Rev. 0.4 3 Si53311 Table 3. DC Common Characteristics (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Supply Current Output Buffer Supply Current (Per Clock Output) @100 MHz Leakage Current Symbol Test Condition Min Typ Max Unit — TBD 100 mA LVPECL (3.3 V) — 35 — mA Low Power LVPECL (3.3 V) — 30 — mA LVDS (3.3 V) — 20 — mA CML (3.3 V) — 30 — mA HCSL, 100 MHz, 2 pF load (3.3 V) — 35 — mA CMOS (1.8 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 5 — mA CMOS (2.5 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 8 — mA CMOS (3.3 V, SFOUT = 0/1), per output, CL = 5 pF, 200 MHz — 15 — mA Input leakage at all inputs except CLKIN, VIN = 0 V — — TBD µA Input leakage at CLKIN VIN = 0 V — — TBD µA IDD IDDOX IL Voltage Reference VREF VREF pin — VDD/2 — V Input High Voltage VIH SFOUTX, DIVX 3-level input pins 0.85 x VDD — — V Input Mid Voltage VIM SFOUTX, DIVX 3-level input pins 0.45 x VDD 0.5 x VDD 0.55 x VDD V Input Low Voltage VIL SFOUTX, DIVXpin 3-level input pins — — 0.15 x VDD V Internal Pull-down Resistor RDOWN CLK_SEL, DIVA, DIVB, SFOUTA[1], SFOUTB[1] — 25 — kΩ RUP SFOUTA[1], SFOUTB[1], DIVA, DIVB, OEA, OEB — 25 — kΩ Internal Pull-up Resistor 4 Preliminary Rev. 0.4 Si53311 Table 4. DC Characteristics—LVPECL and Low Power LVPECL (VDD = 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High VOH RL = 50 Ω to VDDOX – 2 V VDDOX – 1.145 — VDDOX – 0.895 V Output Voltage Low VOL RL = 50 Ω to VDDOX – 2 V VDDOX – 1.945 — VDDOX – 1.695 V Output DC Common Mode Voltage VCOM VDDOX – 1.895 — VDDOX – 1.425 V 0.25 0.60 0.85 V Single-Ended Output Swing VSE Terminate unused outputs to RL = 50 Ω to VDDOX – 2 V Table 5. DC Characteristics—CML (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE Terminated as shown in Figure 6 (CML termination). 300 400 500 mV Table 6. DC Characteristics—LVDS (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE RL = 100 Ω across QN and QN 247 — 454 mV Output Common Mode Voltage (VDDO=2.5V or 3.3V) VCOM1 VDDOX = 2.38 to 2.63 V, 2.97 to 3.63 V, RL = 100 Ω across QN and QN 1.10 1.25 1.35 V Output Common Mode Voltage (VDDO=1.8V) VCOM2 VDDOX = 1.71 to 1.89 V, RL = 100 Ω across QN and QN 0.85 0.97 1.10 V Preliminary Rev. 0.4 5 Si53311 Table 7. DC Characteristics—LVCMOS (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Symbol * Output Voltage Low* Output Voltage High Test Condition Min Typ Max Unit VOH 0.85 x VDDOX — — V VOL — — 0.15 x VDDOX V *Note: IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTX settings. Table 8. DC Characteristics—HCSL (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High VOH RL = 50 Ω to GND 550 700 850 mV Output Voltage Low VOL RL = 50 Ω to GND –150 0 150 mV Single-Ended Output Swing VSE RL = 50 Ω to GND — 700 — mV Crossing Voltage VC RL = 50 Ω to GND 250 350 550 mV 6 Preliminary Rev. 0.4 Si53311 Table 9. AC Characteristics (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Frequency Symbol Test Condition Min Typ Max Unit F LVPECL, low power LVPECL, LVDS, CML, HCSL 1 — 1250 MHz LVCMOS 1 — 200 MHz 200 MHz, 50 toVDD/220/80% TR/TF<10% of period (LVCMOS) TBD TBD TBD % 20/80% TR/TF<10% of period (Differential) 48 50 52 % 0.75 — — V/ns 350 ps DC Duty Cycle Note: 50% input duty cycle. Minimum Input Clock Slew Rate1 SR Required to meet prop delay and additive jitter specifications (20–80%) Output Rise/Fall Time TR/TF LVPECL, LVDS, CML, HCSL, 20/80% 200 MHz, 50 20/80%, 2 pF load (LVCMOS) Minimum Input Pulse Width TW TBD TBD 750 ps 500 — — ps Additive Jitter (Differential Clock Input) J VDD = 2.5/3.3 V, LVPECL/LVDS, F = 725 MHz, 0.75 V/ns input slew rate — 60 80 fs Propagation Delay TPLH, TPHL Low to high, high to low Single-ended TBD — TBD ns Low to high, high to low Differential TBD — TBD ns F = 1 MHz — 2 — s F = 100 MHz — 60 — ns F = 725 MHz — 50 — ns F = 1 MHz — 2 — s F = 100 MHz — 25 — ns F = 725 MHz — 15 — ns Output Enable Time2 Output Disable Time 2 TEN TDIS Notes: 1. For clock division applications, a minimum input clock slew rate of 30 mV/ns is required. 2. See Figure 4. 3. Defined as skew between outputs on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (1.8V=50mVPP, 2.5/3.3V=100mVPP) and noise spur amplitude measured. See AN491 for further details. Preliminary Rev. 0.4 7 Si53311 Table 9. AC Characteristics (Continued) (VDD = 1.8 V 5%, 2.5 V 5%, or 3.3 V 10%,TA = –40 to 85 C) Parameter Output to Output Skew Part to Part Skew3 Power Supply Noise Rejection4 Symbol Test Condition Min Typ Max Unit TSK Identical Configuration, Singleended (QN to QM) — — 100 ps Identical Configuration, Differential (QN to QM) — — 50 ps TPS Identical configuration — 50 — ps PSRR 10 kHz sinusoidal noise — –90 — dBc 100 kHz sinusoidal noise — –90 — dBc 500 kHz sinusoidal noise — –80 — dBc 1 MHz sinusoidal noise — –70 — dBc Notes: 1. For clock division applications, a minimum input clock slew rate of 30 mV/ns is required. 2. See Figure 4. 3. Defined as skew between outputs on different devices operating at the same supply voltages, temperatures, and equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (1.8V=50mVPP, 2.5/3.3V=100mVPP) and noise spur amplitude measured. See AN491 for further details. 8 Preliminary Rev. 0.4 Si53311 Table 10. Thermal Conditions Parameter Symbol Test Condition Value Unit Thermal Resistance, Junction to Ambient JA Still air 49.6 °C/W Thermal Resistance, Junction to Case JC Still air 32.3 °C/W Table 11. Absolute Maximum Ratings Parameter Min Typ Max Unit TS –55 — 150 C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD+ 0.3 V Output Voltage VOUT — — VDD+ 0.3 V ESD Sensitivity HBM 2000 — — V ESD Sensitivity CDM 500 — — V Peak Soldering Reflow Temperature TPEAK — — 260 C — — 125 C Storage Temperature Maximum Junction Temperature Symbol Test Condition HBM, 100 pF, 1.5 kΩ Pb-Free; Solder reflow profile per JEDEC J-STD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. Preliminary Rev. 0.4 9 Si53311 2. Functional Description The Si53311 is a low jitter, low skew 1:6 differential buffer with an integrated 2:1 input mux. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select the active input clock. The selected clock input is routed to two independent banks of outputs. Each output bank features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength. 2.1. Universal, Any-Format Input The Si53311 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 12 and 13 summarize the various input ac- and dc-coupling options supported by the device. Figures 3 and 4 show the recommended input clock termination options. Table 12. LVPECL, LVCMOS, and LVDS LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No Yes Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 13. HCSL and CML HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V No Yes (3.3 V) Yes No Si533xx 0.1 uF CLKx 100 /CLKx 0.1 uF Figure 1. Differential LVPECL, LVDS, CML AC-Coupled Input Termination V D D O = 3 .3 V , 2 .5 V , 1 .8 V V DD S i5 3 3 x x CMOS D riv e r Rs CLKx 50 /C L K x 0 .1 u F V REF N o te : V D D O a n d V D D m u s t b e a t th e sa m e vo lta g e le ve l. Figure 2. LVCMOS DC-Coupled Input Termination 10 Preliminary Rev. 0.4 Si53311 VDDO DC Coupled LVPECL Termination Scheme 1 R1 VDD R1 VDDO = 3.3V or 2.5V Si533xx CLKx 50 “Standard” LVPECL Driver /CLKx 50 R2 R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm VTERM = VDDO – 2V R1 // R2 = 50 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD VDDO = 3.3V or 2.5V Si533xx 50 “Standard” LVPECL Driver CLKx /CLKx 50 50 50 VTERM = VDDO – 2V DC Coupled LVDS Termination VDD VDDO = 3.3V or 2.5V Si533xx CLKx 50 Standard LVDS Driver /CLKx 50 100 DC Coupled HCSL Termination Scheme VDDO = 3.3V 33 Si533xx 50 Standard HCSL Driver VDD CLKx /CLKx 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 3. Differential DC-Coupled Input Terminations Preliminary Rev. 0.4 11 Si53311 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The noninverting input is biased with a 18.75 k pulldown to GND and a 75 k pullup to VDD. The inverting input is biased with a 75 k pullup to VDD. VDD RPU RPU + RPD CLK0 or CLK1 – RPU = 75 kohm RPD = 18.75 kohm Figure 4. Input Bias Resistors 2.3. Universal, Any-Format Output Buffer The Si53311 has highly flexible output drivers that support a wide range of clock signal formats, including LVPECL, low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUTX[1] and SFOUTX[0] are 3-level inputs that can be pin-strapped to select the Bank A and Bank B clock signal formats, respectively. This feature enables the device to be used for format/level translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive strength options are available for each VDDO setting. Table 14. Output Signal Format Selection SFOUTX[1] SFOUTX[0] VDDOX = 3.3 V VDDOX = 2.5 V VDDOX = 1.8 V Open* Open* LVPECL LVPECL N/A 0 0 LVDS LVDS LVDS 0 1 LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive 1 0 LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive 1 1 LVCMOS, 12 mA drive LVCMOS, 9 mA drive LVCMOS, 6 mA drive Open* 0 LVCMOS, 6 mA drive LVCMOS, 4 mA drive LVCMOS, 2 mA drive Open* 1 LVPECL Low power LVPECL Low power N/A 0 Open* CML CML CML 1 Open* HCSL HCSL HCSL *Note: SFOUTX[1:0] are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to VDD/2. 12 Preliminary Rev. 0.4 Si53311 2.4. Input Mux and Output Enable Logic The Si53311 provides two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the input mux and output enable pin settings. Table 15. Input Mux and Output Enable Logic CLK_SEL CLK0 CLK1 OE1 Q2 L L X H L L H X H H H X L H L H X H H H X X X L L3 Notes: 1. Output enable active high 2. On the next negative transition of CLK0 or CLK1. 3. Single-end: Q=low, Q=high Differential: Q=low, Q=high 2.5. Flexible Output Divider The Si53311 provides optional clock division in addition to clock distribution. The divider setting for each bank of output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVX pins open will force a divider value of 1 which is the default mode of operation. Table 16. Divider Selection DIVX Divider Value Open* 1 (default) 0 2 1 4 *Note: DIVX are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin floats to VDD/2. Preliminary Rev. 0.4 13 Si53311 2.6. Input Mux and Output Enable Logic The Si53311 provides two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the input mux and output enable pin settings. Table 17. Input Mux and Output Enable Logic CLK_SEL CLK0 CLK1 OE1 Q2 L L X H L L H X H H H X L H L H X H H H X X X L L3 Notes: 1. Output enable active high 2. On the next negative transition of CLK0 or CLK1. 3. Single-end: Q=low, Q=high Differential: Q=low, Q=high 2.7. Power Supply (VDD and VDDOX) The device includes separate core (VDD) and output driver supplies (VDDOX). This feature allows the core to operate at a lower voltage than VDDO, reducing current consumption in mixed supply applications. The core VDD supports 3.3, 2.5, or 1.8 V. Each output bank has its own VDDOX supply, supporting 3.3, 2.5, or 1.8 V. 14 Preliminary Rev. 0.4 Si53311 2.8. Output Clock Termination Options The recommended output clock termination options are shown below. Unused output clocks should be left floating. VDDO DC Coupled LVPECL Termination Scheme 1 R1 R1 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si533xx VDD = VDDO 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDDO – 2V VDDO AC Coupled LVPECL Termination Scheme 1 R1 VDDO = 3.3V or 2.5V Si533xx R1 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb R2 VBIAS = VDD – 1.3V R1 // R2 = 50 Ohm 3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm 2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm AC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si533xx 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb 50 Rb 50 3.3V LVPECL: Rb = 120 Ohm 2.5V LVPECL: Rb = 90 Ohm Figure 5. LVPECL Output Termination Preliminary Rev. 0.4 15 Si53311 DC Coupled LVDS and Low-Power LVPECL Termination VDDO= 3.3V or 2.5V or 1.8V Si533xx VDD 50 Q LVDS Receiver Qn 50 100 AC Coupled LVDS Termination VDDO = 3.3V or 2.5V or 1.8V Si533xx 0.1 uF VDD 50 Q LVDS Receiver Qn 50 0.1 uF 50 50 AC Coupled CML Termination VDDO = 3.3V or 2.5V or 1.8V Si533xx 0.1 uF VDD 50 Q CML Receiver 100 Qn 50 0.1 uF DC Coupled HCSL Receiver Termination VDDO = 3.3V Si533xx VDD 50 Q Standard HCSL Receiver Qn 50 50 50 DC Coupled HCSL Source Termination VDDO = 3.3V Si533xx VDD 42.2 50 Q Qn 42.2 50 86.6 86.6 Figure 6. LVDS, CML, and HCSL Output Termination 16 Preliminary Rev. 0.4 Standard HCSL Receiver Si53311 CMOS Receivers Si533xx CMOS Driver Zo Rs Zout 50 CL = 15 pF Figure 7. LVCMOS Output Termination Table 18. Recommended LVCMOS RS Series Termination SFOUTX[1] SFOUTX[0] RS (ohms) 3.3 V 2.5 V 1.8 V 0 1 33 33 33 1 0 33 33 33 1 1 0 0 0 Open 0 0 0 0 Preliminary Rev. 0.4 17 Si53311 2.9. AC Timing Waveforms TPHL TSK CLK QN VPP/2 Q VPP/2 QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP Q 20% VPP TR Rise/Fall Time Figure 8. AC Waveforms 18 Preliminary Rev. 0.4 Si53311 2.10. Typical Phase Noise Performance 22.77fs @625MHz 30.26fs @312.5MHz 39.34fs @156.25MHz Source Jitter 55.00fs @625MHz 106.37fs @312.5MHz 191.58fs @156.25MHz Total Jitter Figure 9. Si53311 Phase Noise Note: Measured single-endedly. Preliminary Rev. 0.4 19 Si53311 Table 19. Si53311 Additive Jitter Frequency (MHz) Source Jitter (fs) Total Jitter (fs) Additive Jitter (fs) 156.25 39.34 191.58 187.50 312.5 30.26 106.37 101.98 625 22.77 55.00 50.07 2.11. Input Mux Noise Isolation LVPECL [email protected]; Selected clk is active Unselected clk is static Mux Isolation = 61dB LVPECL [email protected]; Selected clk is static Unselected clk is active Figure 10. Input Mux Noise Isolation 20 Preliminary Rev. 0.4 Si53311 2.12. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. For more information, see “AN491: Power Supply Rejection for Low Jitter Clocks.” Spur A Amplitude (dB Bc) )F 0+] Figure 11. Power Supply Noise Rejection (100mVpp Sinusoidal Power Supply Noise Applied) Preliminary Rev. 0.4 21 Si53311 Q1 Q1 Q2 Q2 Q3 Q3 Q4 Q4 3. Pin Description: 32-Pin QFN 32 31 30 29 28 27 26 25 DIVA 1 24 DIVB SFOUTA[1] 2 23 SFOUTB[1] SFOUTA[0] 3 22 SFOUTB[0] Q0 4 21 Q5 Q0 5 20 Q5 GND 6 19 V DDOB VDD 7 18 V DDOA 8 17 V REF 15 16 CLK1 NC 14 CLK1 11 CLK0 OEB 13 10 CLK0 OEA 12 9 NC CLK_SEL GND PAD Table 20. Pin Description 22 Pin Name Description 1 DIVA Output divider control pin for Bank A Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 2 SFOUTA[1] Output signal format control pin for Bank A Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 3 SFOUTA[0] Output signal format control pin for Bank A Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 4 Q0 Output clock 0 (complement) 5 Q0 Output clock 0 6 GND Ground 7 VDD Core voltage supply. Bypass with 1.0 F capacitor and place as close to the VDD pin as possible. Preliminary Rev. 0.4 Si53311 Table 20. Pin Description (Continued) Pin Name Description 8 CLK_SEL 9 NC No connect. 10 CLK0 Input clock 0 11 CLK0 Input clock 0 (complement) When the CLK0 is driven by a single-end input, connect VREF to CLK0. CLK0 contains an internal pull-up resistor. 12 OEA Output enable—Bank A When OE=high, the Bank A outputs are enabled. When OE=low, Q is held low, and Q is held high for differential formats. For LVCMOS, both Q and Q are held low when OE is set low. OEA contains an internal pull-up resistor. 13 OEB Output enable—Bank B When OE=high, the Bank B outputs are enabled. When OE=low, Q is held low, and Q is held high for differential formats. For LVCMOS, both Q and Q are held low when OE is set low. OEB contains an internal pull-up resistor. 14 CLK1 Input clock 1 15 CLK1 Input clock 1 (complement) When the CLK1 is driven by a single-end input, connect VREF to CLK1. CLK1 contains an internal pull-up resistor. 16 NC 17 VREF 18 VDDOA Output voltage supply—Bank A (Outputs: Q0 to Q2) Bypass with 1.0 F capacitor and place as close to the VDDOA pin as possible. 19 VDDOB Output voltage supply—Bank B (Outputs: Q3 to Q5) Bypass with 1.0 F capacitor and place as close to the VDDOB pin as possible. 20 Q5 Output clock 5 (complement) 21 Q5 Output clock 5 Mux input select pin (LVCMOS) Clock inputs are switched without the introduction of glitches. When CLK_SEL is high, CLK1 is selected. When CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor. No connect. Input reference voltage When driven by a LVCMOS clock input, connect the unused clock input to VREF and a 0.1µF cap to ground. When driven by a differential clock, do not connect the VREF pin. Preliminary Rev. 0.4 23 Si53311 Table 20. Pin Description (Continued) Pin Name 22 SFOUTB[0] Output signal format control pin for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 23 SFOUTB[1] Output signal format control pin for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 24 DIVB Output divider configuration bit for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 25 Q4 Output clock 4 (complement) 26 Q4 Output clock 4 27 Q3 Output clock 3 (complement) 28 Q3 Output clock 3 29 Q2 Output clock 2 (complement) 30 Q2 Output clock 2 31 Q1 Output clock 1 (complement) 32 Q1 Output clock 1 GND Pad GND 24 Description Ground Pad. Power supply ground and thermal relief. Preliminary Rev. 0.4 Si53311 4. Ordering Guide Part Number Package PB-Free, RoHS-6 Temperature Si53311-B-GM 32-QFN Yes –40 to 85 C Preliminary Rev. 0.4 25 Si53311 5. Package Outline 5.1. 5x5 mm 32-QFN Package Diagram Figure 12. Si53311 5x5 mm 32-QFN Package Diagram Table 21. Package Dimensions Dimension Min Nom Max A 0.80 0.85 1.00 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 c 0.20 0.25 0.30 D D2 5.00 BSC 2.00 2.15 e 0.50 BSC E 5.00 BSC E2 2.00 2.15 2.30 L 0.30 0.40 0.50 aaa 0.10 bbb 0.10 ccc 0.08 ddd 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 26 2.30 Preliminary Rev. 0.4 Si53311 6. PCB Land Pattern 6.1. 5x5 mm 32-QFN Package Land Pattern Figure 13. Si53311 5x5 mm 32-QFN Package Land Pattern Table 22. PCB Land Pattern Dimension Min Max Dimension Min Max C1 4.52 4.62 X2 2.20 2.30 C2 4.52 4.62 Y1 0.59 0.69 Y2 2.20 2.30 E X1 0.50 BSC 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 m minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2x2 array of 0.75 mm square openings on 1.15 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Preliminary Rev. 0.4 27 Si53311 7. Top Marking 7.1. Si53311 Top Marking 7.2. Top Marking Explanation Mark Method: Laser Font Size: 2.0 Point (28 mils) Center-Justified Line 1 Marking: Device Part Number 53311 Line 2 Marking: Device Revision/Type B-GM Line 3 Marking: YY=Year WW=Work Week Assigned by the Assembly House. Corresponds to the year and work week of the mold date. Line 4 Marking 28 R=Die Rev F=Wafer Fab First two characters of the Manufacturing Code from the Assembly Purchase Order form. Circle=0.5 mm Diameter Lower-Left Justified Pin 1 Identifier A=Assembly Site I=Internal Code XX=Serial Lot Number Last four characters of the Manufacturing Code from the Assembly Purchase Order form. Preliminary Rev. 0.4 Si53311 NOTES: Preliminary Rev. 0.4 29 Si53311 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. 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