Si53312 1 : 1 0 L OW J I T T E R U NIVERSAL B U FF E R /L EVEL T RANSLATOR WITH 2 : 1 I NPUT M UX (<1.25 GH Z ) Features Ordering Information: See page 28. Applications Q6 Q6 VDDOB 34 37 35 38 39 DIVA 1 33 SFOUTA[1] SFOUTA[0] 2 32 3 31 DIVB SFOUTB[1] SFOUTB[0] Q2 4 Q2 5 GND 6 Q1 7 Q1 8 Q0 9 25 Q0 10 24 Q9 NC 11 23 CLK_SEL 30 27 Q8 26 Q8 20 21 NC GND Q9 22 CLK1 17 19 16 18 28 Q7 Q7 NC 29 GND PAD OEB CLK1 The Si53312 is an ultra low jitter ten output differential buffer with pin-selectable output clock signal format and divider selection. The Si53312 features a 2:1 mux, making it ideal for redundant clocking applications. The Si53312 utilizes Silicon Laboratories' advanced CMOS technology to fanout clocks from dc to 1.25 GHz with guaranteed low additive jitter, low skew, and low propagation delay variability. The Si53312 features minimal cross-talk and provides superior supply noise rejection, simplifying low jitter clock distribution in noisy environments. Independent core and output bank supply pins provide integrated level translation without the need for external circuitry. 40 Description 41 36 42 Si53312 43 Storage Telecom Industrial Servers Backplane clock distribution 44 15 Pin Assignments High-speed clock distribution Ethernet switch/router Optical Transport Network (OTN) SONET/SDH PCI Express Gen 1/2/3 VDDOA Q3 Q3 Q4 Q4 GND Q5 Q5 14 CLK0 CLK0 OEA VREF 12 Low output-output skew: <70 ps Low propagation delay variation: <400 ps Independent VDD and VDDO : 1.8/2.5/3.3 V Excellent power supply noise rejection (PSRR) Selectable LVCMOS drive strength to tailor jitter and EMI performance Small size: 44-QFN (7 mm x 7 mm) RoHS compliant, Pb-free Industrial temperature range: –40 to +85 °C 13 10 differential or 20 LVCMOS outputs Ultra-low additive jitter: 45 fs rms Wide frequency range: dc to 1.25 GHz Any-format input with pin selectable output formats: LVPECL, Low Power LVPECL, LVDS, CML, HCSL, LVCMOS 2:1 mux with hot-swappable inputs Asynchronous output enable Output clock division: /1, /2, /4 (/2 and /4 for dc to 725 MHz) NC VDD Patents pending Functional Block Diagram VREF Vref Generator Power Supply Filtering DIVA VDDOA SFOUTA[1:0] OEA Q0, Q1, Q2, Q3, Q4 DivA Q0, Q1, Q2, Q3, Q4 CLK0 /CLK0 DIVB VDDOB SFOUTB[1:0] OEB CLK1 /CLK1 Q5, Q6, Q7, Q8, Q9 DivB CLK_SEL Rev. 1.0 9/15 Switching Logic Q5, Q6, Q7, Q8, Q9 Copyright © 2015 by Silicon Laboratories Si53312 Si53312 TABLE O F C ONTENTS Section Page 1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 2. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.1. Universal, Any-Format Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2.2. Input Bias Resistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.3. Voltage Reference (VREF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.4. Universal, Any-Format Output Buffer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 2.5. Input Mux and Output Enable Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.6. Flexible Output Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.7. Power Supply (VDD and VDDOX) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.8. Output Clock Termination Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 2.9. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 2.10. AC Timing Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 2.11. Typical Phase Noise Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 2.12. Input Mux Noise Isolation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 2.13. Power Supply Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 3. Pin Description: 44-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5. Package Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.1. 7x7 mm 44-QFN Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 6. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 6.1. 7x7 mm 44-QFN Package Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7. Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.1. Si53312 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 7.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 2 Rev. 1.0 Si53312 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Ambient Operating Temperature Supply Voltage Range* Output Buffer Supply Voltage* Symbol Test Condition Min Typ Max Unit –40 — 85 °C 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V LVPECL, low power LVPECL, LVCMOS 2.38 2.5 2.63 V 2.97 3.3 3.63 V HCSL 2.97 3.3 3.63 V LVDS, CML, LVCMOS 1.71 1.8 1.89 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V 2.38 2.5 2.63 V 2.97 3.3 3.63 V 2.97 3.3 3.63 V TA VDD VDDOX LVDS, CML LVPECL, low power LVPECL HCSL *Note: Core supply VDD and output buffer supplies VDDO are independent. LVCMOS clock input is not supported for VDD = 1.8V but is supported for LVCMOS clock output for VDDOX = 1.8V. LVCMOS outputs at 1.5V and 1.2V can be supported via a simple resistor divider network. See “2.8.1. LVCMOS Output Termination To Support 1.5 V and 1.2 V” Table 2. Input Clock Specifications (VDD=1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%, TA=–40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Differential Input Common Mode Voltage VCM VDD = 2.5 V± 5%, 3.3 V± 10% 0.05 — — V Differential Input Swing (peak-to-peak) VIN 0.2 — 2.2 V LVCMOS Input High Voltage VIH VDD = 2.5 V± 5%, 3.3 V± 10% VDD x 0.7 — — V LVCMOS Input Low Voltage VIL VDD = 2.5 V± 5%, 3.3 V± 10% — — VDD x 0.3 V Input Capacitance CIN CLK0 and CLK1 pins with respect to GND — 5 — pF Rev. 1.0 3 Si53312 Table 3. DC Common Characteristics (VDD = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Supply Current Output Buffer Supply Current (Per Clock Output) @100 MHz Symbol Test Condition Min Typ Max Unit — 65 100 mA LVPECL (3.3 V) — 35 — mA Low Power LVPECL (3.3 V) — 35 — mA LVDS (3.3 V) — 20 — mA CML (3.3 V) — 30 — mA HCSL, 100 MHz, 2 pF load (3.3 V) — 35 — mA CMOS (1.8 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 5 — mA CMOS (2.5 V, SFOUT = Open/0), per output, CL = 5 pF, 200 MHz — 8 — mA CMOS (3.3 V, SFOUT = 0/1), per output, CL = 5 pF, 200 MHz — 15 — mA IDD IDDOX Voltage Reference VREF VREF pin — VDD/2 — V Input High Voltage VIH SFOUTx, DIVx, CLK_SEL, OEx 0.8 x VDD — — V Input Mid Voltage VIM SFOUTx, DIVx 3-level input pins 0.45 x VDD 0.5 x VDD 0.55 x VDD V Input Low Voltage VIL SFOUTx, DIVx, CLK_SEL, OEx — — 0.2 x VDD V Internal Pull-down Resistor RDOWN CLK_SEL, DIVx, SFOUTx, — 25 — kΩ RUP OEx, DIVx, SFOUTx — 25 — kΩ Internal Pull-up Resistor Table 4. Output Characteristics (LVPECL) (VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output DC Common Mode Voltage Single-Ended Output Swing Test Condition Min Typ Max Unit VCOM VDDOX – 1.595 — VDDOX – 1.245 V VSE 0.40 0.80 1.050 V *Note: Unused outputs can be left floating. Do not short unused outputs to ground. 4 Rev. 1.0 Si53312 Table 5. Output Characteristics (Low Power LVPECL) (VDDOX = 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Output DC Common Mode Voltage VCOM RL = 100 Ω across Qn and Qn VDDOX – 1.895 VSE RL = 100 Ω across Qn and Qn 0.20 Single-Ended Output Swing Typ Max Unit VDDOX – 1.275 V 0.85 V 0.60 Table 6. Output Characteristics—CML (VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE Terminated as shown in Figure 8 (CML termination). 200 400 550 mV Table 7. Output Characteristics—LVDS (VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Test Condition Min Typ Max Unit Single-Ended Output Swing VSE RL = 100 Ω across QN and QN 200 — 490 mV Output Common Mode Voltage (VDDO = 2.5 V or 3.3V) VCOM1 VDDOX = 2.38 to 2.63 V, 2.97 to 3.63 V, RL = 100 Ω across QN and QN 1.10 1.25 1.35 V Output Common Mode Voltage (VDDO = 1.8 V) VCOM2 VDDOX = 1.71 to 1.89 V, RL = 100 Ω across QN and QN 0.85 0.97 1.25 V Table 8. Output Characteristics—LVCMOS (VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Symbol Output Voltage High Output Voltage Low Test Condition Min Typ Max Unit VOH 0.75 x VDDOX — — V VOL — — 0.25 x VDDOX V *Note: IOH and IOL per the Output Signal Format Table for specific VDDOX and SFOUTx settings. Rev. 1.0 5 Si53312 Table 9. Output Characteristics—HCSL (VDDOX = 3.3 V ± 10%, TA = –40 to 85 °C)) Parameter Symbol Test Condition Min Typ Max Unit Output Voltage High VOH RL = 50 Ω to GND 550 700 900 mV Output Voltage Low VOL RL = 50 Ω to GND –150 0 150 mV Single-Ended Output Swing VSE RL = 50 Ω to GND 450 700 850 mV Crossing Voltage VC RL = 50 Ω to GND 250 350 550 mV Table 10. AC Characteristics (VDD = VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Frequency Duty Cycle6 Symbol Test Condition Min Typ Max Unit F LVPECL, low power LVPECL, LVDS, CML, HCSL dc — 1250 GHz LVCMOS dc — 200 MHz 200 MHz, 20/80% TR/TF<10% of period (LVCMOS) (12 mA drive) 40 50 60 % 20/80% TR/TF<10% of period (Differential) 47 50 53 % DC Minimum Input Clock Slew Rate5 SR Required to meet prop delay and additive jitter specifications (20–80%) 0.75 — — V/ns Output Rise/Fall Time TR/TF LVDS, 20/80% — — 325 ps LVPECL, 20/80% — — 350 ps HCSL1, 20/80% — — 280 ps CML, 20/80% — — 350 ps Low-Power LVPECL, 20/80% — — 325 ps LVCMOS 200 MHz, 20/80%, 2 pF load — — 750 ps Notes: 1. HCSL measurements were made with receiver termination. See Figure 8 on page 17. 2. Output to Output skew specified for outputs with an identical configuration. 3. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. 5. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required. 6. 50% input duty cycle. 6 Rev. 1.0 Si53312 Table 10. AC Characteristics (Continued) (VDD = VDDOX = 1.8 V ± 5%, 2.5 V ± 5%, or 3.3 V ± 10%,TA = –40 to 85 °C) Parameter Minimum Input Pulse Width Propagation Delay Output Enable Time Output Disable Time Output to Output Skew2 Part to Part Skew3 Power Supply Noise Rejection4 Symbol Test Condition Min Typ Max Unit 360 — — ps LVCMOS (12mA drive with no load) 1250 2000 2750 ps LVPECL 600 800 1000 ps LVDS 600 800 1000 ps F = 1 MHz — 2500 — ns F = 100 MHz — 30 — ns F = 725 MHz — 5 — ns F = 1 MHz — 2000 — ns F = 100 MHz — 30 — ns F = 725 MHz — 5 — ns LVCMOS (12 mA drive to no load) — 50 120 ps LVPECL — 35 70 ps LVDS — 35 70 ps TPS Differential — — 150 ps PSRR 10 kHz sinusoidal noise — –63 — dBc 100 kHz sinusoidal noise — –62 — dBc 500 kHz sinusoidal noise — –58 — dBc 1 MHz sinusoidal noise — –55 — dBc TW TPLH, TPHL TEN TDIS TSK Notes: 1. HCSL measurements were made with receiver termination. See Figure 8 on page 17. 2. Output to Output skew specified for outputs with an identical configuration. 3. Defined as skew between any output on different devices operating at the same supply voltage, temperature, and and equal load condition. Using the same type of inputs on each device, the outputs are measured at the differential cross points. 4. Measured for 156.25 MHz carrier frequency. Sine-wave noise added to VDDOX (3.3 V = 100 mVPP) and noise spur amplitude measured. See “AN491: Power Supply Rejection for Low-Jitter Clocks” for further details. 5. When using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required. 6. 50% input duty cycle. Rev. 1.0 7 Si53312 Table 11. Additive Jitter, Differential Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (Single-Ended, Peak-to-Peak) Differential Clock Format 20%-80% Slew Rate (V/ns) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 Typ Max 3.3 725 Differential 0.15 0.637 LVPECL 45 65 3.3 725 Differential 0.15 0.637 LVDS 50 65 3.3 156.25 Differential 0.5 0.458 LVPECL 160 185 3.3 156.25 Differential 0.5 0.458 LVDS 150 200 2.5 725 Differential 0.15 0.637 LVPECL 45 65 2.5 725 Differential 0.15 0.637 LVDS 50 65 2.5 156.25 Differential 0.5 0.458 LVPECL 145 185 2.5 156.25 Differential 0.5 0.458 LVDS 145 195 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. AC-coupled differential inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. 8 Rev. 1.0 Si53312 Table 12. Additive Jitter, Single-Ended Clock Input VDD Output Input1,2 Freq (MHz) Clock Format Amplitude VIN (single-ended, peak to peak) Additive Jitter (fs rms, 12 kHz to 20 MHz)3 SE 20%-80% Slew Rate (V/ns) Clock Format Typ Max 3.3 200 Single-ended 1.70 1 LVCMOS4 120 160 3.3 156.25 Single-ended 2.18 1 LVPECL 160 185 3.3 156.25 Single-ended 2.18 1 LVDS 150 200 3.3 156.25 Single-ended 2.18 1 LVCMOS4 130 180 2.5 200 Single-ended 1.70 1 LVCMOS5 120 160 2.5 156.25 Single-ended 2.18 1 LVPECL 145 185 2.5 156.25 Single-ended 2.18 1 LVDS 145 195 2.5 156.25 Single-ended 2.18 1 LVCMOS5 140 180 Notes: 1. For best additive jitter results, use the fastest slew rate possible. See “AN766: Understanding and Optimizing Clock Buffer’s Additive Jitter Performance” for more information. 2. DC-coupled single-ended inputs. 3. Measured differentially using a balun at the phase noise analyzer input. See Figure 1. 4. Drive Strength: 12 mA, 3.3 V (SFOUT = 11). LVCMOS jitter is measured single-ended. 5. Drive Strength: 9 mA, 2.5 V (SFOUT = 11). LVCMOS jitter is measured single-ended. PSPL 5310A CLK SYNTH SMA103A 50 Si53312 DUT Balun PSPL 5310A CLKx AG E5052 Phase Noise Analyzer 50ohm /CLKx 50 Balun Figure 1. Differential Measurement Method Using a Balun Rev. 1.0 9 Si53312 Table 13. Thermal Conditions Parameter Symbol Test Condition Value Unit Thermal Resistance, Junction to Ambient θJA Still air 49.6 °C/W Thermal Resistance, Junction to Case θJC Still air 32.3 °C/W Table 14. Absolute Maximum Ratings Parameter Symbol Storage Temperature Min Typ Max Unit TS –55 — 150 °C Supply Voltage VDD –0.5 — 3.8 V Input Voltage VIN –0.5 — VDD+ 0.3 V Output Voltage VOUT — — VDD+ 0.3 V ESD Sensitivity HBM — — 2000 V ESD Sensitivity CDM — — 500 V Peak Soldering Reflow Temperature TPEAK — — 260 °C — — 125 °C Maximum Junction Temperature Test Condition HBM, 100 pF, 1.5 kΩ Pb-Free; Solder reflow profile per JEDEC J-STD-020 TJ Note: Stresses beyond those listed in this table may cause permanent damage to the device. Functional operation specification compliance is not implied at these conditions. Exposure to maximum rating conditions for extended periods may affect device reliability. 10 Rev. 1.0 Si53312 2. Functional Description The Si53312 is a low jitter, low skew 1:10 differential buffer with an integrated 2:1 input mux. The device has a universal input that accepts most common differential or LVCMOS input signals. A clock select pin is used to select the active input clock. The selected clock input is routed to two independent banks of outputs. Each output bank features control pins to select signal format, output enable, output divider setting and LVCMOS drive strength. 2.1. Universal, Any-Format Input The Si53312 has a universal input stage that enables simple interfacing to a wide variety of clock formats, including LVPECL, LVCMOS, LVDS, HCSL, and CML. Tables 15 and 16 summarize the various input ac- and dc-coupling options supported by the device. Figures 3 and 4 show the recommended input clock termination options. Table 15. LVPECL, LVCMOS, and LVDS LVPECL LVCMOS LVDS AC-Couple DC-Couple AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V N/A N/A No No Yes No 2.5/3.3 V Yes Yes No Yes Yes Yes Table 16. HCSL and CML HCSL CML AC-Couple DC-Couple AC-Couple DC-Couple 1.8 V No No Yes No 2.5/3.3 V Yes Yes (3.3 V) Yes No 0.1 µF CLKx 100 Ω Si53312 /CLKx 0.1 µF Figure 2. Differential LVPECL, LVDS, CML AC-Coupled Input Termination VDD CMOS Driver VDD 1 kΩ VDDO = 3. 3 V or 2. 5 V Si53312 CLKx 50 CLKx Rs VTERM = VDD/2 1 kΩ VREF Figure 3. LVCMOS DC-Coupled Input Termination Rev. 1.0 11 Si53312 VDDO DC Coupled LVPECL Termination Scheme 1 R1 VDD R1 VDDO = 3.3V or 2.5V Si53312 “Standard” LVPECL Driver CLKx 50 /CLKx 50 R2 R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm VTERM = VDDO – 2V R1 // R2 = 50 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDD VDDO = 3.3V or 2.5V Si53312 50 “Standard” LVPECL Driver CLKx /CLKx 50 50 50 VTERM = VDDO – 2V DC Coupled LVDS Termination VDD VDDO = 3.3V or 2.5V Si53312 CLKx 50 Standard LVDS Driver /CLKx 50 100 DC Coupled HCSL Termination Scheme VDDO = 3.3V Standard HCSL Driver VDD 33 Si53312 50 CLKx /CLKx 33 50 50 50 Note: 33 Ohm series termination is optional depending on the location of the receiver. Figure 4. Differential DC-Coupled Input Terminations 12 Rev. 1.0 Si53312 2.2. Input Bias Resistors Internal bias resistors ensure a differential output low condition in the event that the clock inputs are not connected. The noninverting input is biased with a 18.75 kΩ pulldown to GND and a 75 kΩ pullup to VDD. The inverting input is biased with a 75 kΩ pullup to VDD. VDD RPU RPU + RPD CLK0 or CLK1 – RPU = 75 kohm RPD = 18.75 kohm Figure 5. Input Bias Resistors 2.3. Voltage Reference (VREF) The VREF pin can be used to bias the input receiver, as shown in Figure 6 when a single-ended input clock (such as LVCMOS) is used. Note that VREF = VDD/2 and should be compatible with the VCM rating of the single-ended input clock driving the CLK0 or CLK1 inputs. To optimize jitter and duty cycle performance, use the circuit in Figure 3. VREF pin should be left floating when differential clocks are used. VDDO =3.3V, 2.5V, 1.8V Rs CMOSDriver CLKx 50 Si53312 /CLKx VREF 100nF Figure 6. Using Voltage Reference with Single-Ended Input Clock Rev. 1.0 13 Si53312 2.4. Universal, Any-Format Output Buffer The highly flexible output drivers support a wide range of clock signal formats, including LVPECL, low power LVPECL, LVDS, CML, HCSL, and LVCMOS. SFOUTx[1] and SFOUTx[0] are 3-level inputs that can be pinstrapped to select the Bank A and Bank B clock signal formats independently. This feature enables the device to be used for format/level translation in addition to clock distribution, minimizing the number of unique buffer part numbers required in a typical application and simplifying design reuse. For EMI reduction applications, four LVCMOS drive strength options are available for each VDDO setting. Table 17. Output Signal Format Selection SFOUTx[1] SFOUTx[0] VDDOX = 3.3 V VDDOX = 2.5 V VDDOX = 1.8 V Open* Open* LVPECL LVPECL N/A 0 0 LVDS LVDS LVDS 0 1 LVCMOS, 24 mA drive LVCMOS, 18 mA drive LVCMOS, 12 mA drive 1 0 LVCMOS, 18 mA drive LVCMOS, 12 mA drive LVCMOS, 9 mA drive 1 1 LVCMOS, 12 mA drive LVCMOS, 9 mA drive LVCMOS, 6 mA drive Open* 0 LVCMOS, 6 mA drive LVCMOS, 4 mA drive LVCMOS, 2 mA drive Open* 1 LVPECL Low power LVPECL Low power N/A 0 Open* CML CML CML 1 Open* HCSL HCSL HCSL *Note: SFOUTx[1:0] are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin is internally biased to VDD/2. 14 Rev. 1.0 Si53312 2.5. Input Mux and Output Enable Logic The Si53312 provides two clock inputs for applications that need to select between one of two clock sources. The CLK_SEL pin selects the active clock input. The table below summarizes the input and output clock based on the input mux and output enable pin settings. Table 18. Input Mux and Output Enable Logic CLK_SEL CLK0 CLK1 OE1 Q2 L L X H L L H X H H H X L H L H X H H H X X X L L3 Notes: 1. Output enable active high 2. On the next negative transition of CLK0 or CLK1. 3. Single-end: Q=low, Q=high Differential: Q=low, Q=high 2.6. Flexible Output Divider The Si53312 provides optional clock division in addition to clock distribution. The divider setting for each bank of output clocks is selected via 3-level control pins as shown in the table below. Leaving the DIVx pins open will force a divider value of 1, which is the default mode of operation. Note that when using the on-chip clock divider, a minimum input clock slew rate of 30 mV/ns is required. Table 19. Divider Selection DIVx1 Divider Value Open2 ÷1 (default) 03 ÷2 13 ÷4 Notes: 1. DIVx are 3-level input pins. Tie low for “0” setting. Tie high for “1” setting. When left open, the pin is internally biased to VDD/2. 2. For frequency range dc to 1.25 GHz. 3. For frequency range dc to 725 MHz. 2.7. Power Supply (VDD and VDDOX) The device includes separate core (VDD) and output driver supplies (VDDOX). This feature allows the core to operate at a lower voltage than VDDO, reducing current consumption in mixed supply applications. The core VDD supports 3.3, 2.5, or 1.8 V. Each output bank has its own VDDOX supply, supporting 3.3, 2.5, or 1.8 V as defined in Table 1. Rev. 1.0 15 Si53312 2.8. Output Clock Termination Options The recommended output clock termination options are shown below. VDDO DC Coupled LVPECL Termination Scheme 1 R1 R1 VDDO = 3.3V or 2.5V Si53312 VDD = VDDO 50 Q LVPECL Receiver Qn 50 R2 VTERM = VDDO – 2V R1 // R2 = 50 Ohm R2 3.3V LVPECL: R1 = 127 Ohm, R2 = 82.5 Ohm 2.5V LVPECL: R1 = 250 Ohm, R2 = 62.5 Ohm DC Coupled LVPECL Termination Scheme 2 VDDO = 3.3V or 2.5V Si53312 VDD = VDDO 50 Q LVPECL Receiver Qn 50 50 50 VTERM = VDDO – 2V VDDO AC Coupled LVPECL Termination Scheme 1 R1 VDDO = 3.3V or 2.5V Si53312 R1 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb R2 Rb R2 VBIAS = VDD – 1.3V R1 // R2 = 50 Ohm 3.3V LVPECL: R1 = 82.5 Ohm, R2 = 127 Ohm, Rb = 120 Ohm 2.5V LVPECL: R1 = 62.5 Ohm, R2 = 250 Ohm, Rb = 90 Ohm AC Coupled LVPECL Termination Scheme 2 V DDO = 3.3V or 2.5V Si53312 0.1 uF VDD = 3.3V or 2.5V 50 Q LVPECL Receiver Qn 50 0.1 uF Rb Rb 50 50 V BIAS = V DD – 1.3 V 3.3V LVPECL: Rb = 120 Ohm 2.5V LVPECL: Rb = 90 Ohm Figure 7. LVPECL Output Termination 16 Rev. 1.0 Si53312 DC Coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V or 2.5 V, or 1.8 V (LVDS only) Si53312 VDD 50 Q Standard LVDS Receiver Qn 50 100 AC Coupled LVDS and Low-Power LVPECL Termination VDDO = 3.3 V or 2.5 V or 1.8 V (LVDS only) Si53312 0.1 uF VDD 50 Q Standard LVDS Receiver Qn 50 0.1 uF 100 AC Coupled CML Termination VDDO = 3.3V or 2.5V or 1.8V Si53312 0.1 uF VDD 50 Q Standard CML Receiver 100 Qn 50 0.1 uF DC Coupled HCSL Receiver Termination VDDO = 3.3V Si53312 VDD 50 Q Standard HCSL Receiver Qn 50 50 50 DC Coupled HCSL Source Termination VDDO = 3.3V Si53312 VDD 42.2 50 Q Qn 42.2 50 86.6 Standard HCSL Receiver 86.6 Figure 8. LVDS, CML, HCSL, and Low-Power LVPECL Output Termination Rev. 1.0 17 Si53312 CMOS Receivers Si53312 CMOS Driver Zout Zo Rs 50 Figure 9. LVCMOS Output Termination Table 20. Recommended LVCMOS RS Series Termination SFOUTx[1] SFOUTx[0] RS (ohms) 3.3 V 2.5 V 1.8 V 0 1 33 33 33 1 0 33 33 33 1 1 33 33 0 Open 0 0 0 0 2.8.1. LVCMOS Output Termination To Support 1.5 V and 1.2 V LVCMOS clock outputs are natively supported at 1.8 V, 2.5 V, and 3.3 V. However, 1.2 V and 1.5 V LVCMOS clock outputs can be supported via a simple resistor divider network that will translate the buffer’s 1.8 V output to a lower voltage as shown in Figure 10. VDDOx= 1.8V R1 50 R2 LVCMOS 1.5V LVCMOS: R1 = 43 ohms, R2 = 300 ohms, IOUT = 12mA 1.2V LVCMOS: R1 = 58 ohms, R2 = 150 ohms, IOUT = 12mA R1 50 R2 Figure 10. 1.5V and 1.2V LVCMOS Low-Voltage Output Termination 18 Rev. 1.0 Si53312 2.9. AC Timing Waveforms TPHL TSK VPP/2 CLK Q VPP/2 QN QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP 20% VPP Q Rise/Fall Time TR Figure 11. AC Waveforms Rev. 1.0 19 Si53312 2.10. AC Timing Waveforms TPHL TSK CLK QN VPP/2 Q VPP/2 QM VPP/2 VPP/2 TPLH TSK Propagation Delay Output-Output Skew TF Q 80% VPP 20% VPP 80% VPP Q 20% VPP TR Rise/Fall Time Figure 12. AC Waveforms 20 Rev. 1.0 Si53312 2.11. Typical Phase Noise Performance Each of the following three figures shows three phase noise plots superimposed on the same diagram. Source Jitter: Reference clock phase noise. Total Jitter (SE): Combined source and clock buffer phase noise measured as a single-ended output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. Total Jitter (Diff): Combined source and clock buffer phase noise measured as a differential output to the phase noise analyzer and integrated from 12 kHz to 20 MHz. The differential measurement as shown in each figure is made using a balun. See Figure 1 on page 9. Note: To calculate the total RMS phase jitter when adding a buffer to your clock tree, use the root-sum-square (RSS). The total jitter is a measure of the source plus the buffer's additive phase jitter. The additive jitter (rms) of the buffer can then be calculated (via root-sum-square addition). Figure 13. Source Jitter (156.25 MHz) Table 21. Source Jitter (156.25 MHz) Frequency (MHz) Diff’l Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Diff’l) (fs) Additive Jitter (Diff’l) (fs) 156.25 1.0 38.2 147.8 142.8 118.3 112.0 Rev. 1.0 21 Si53312 Figure 14. Single-ended Total Jitter (312.5 MHz) Table 22. Single-ended Total Jitter (312.5 MHz) 22 Frequency (MHz) Diff’l Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Diff’l) (fs) Additive Jitter (Diff’l) (fs) 312.5 1.0 33.10 94.39 88.39 83.80 76.99 Rev. 1.0 Si53312 Figure 15. Differential Total Jitter (625 MHz) Table 23. Differential Total Jitter (625 MHz) Frequency (MHz) Diff’l Input Slew Rate (V/ns) Source Jitter (fs) Total Jitter (SE) (fs) Additive Jitter (SE) (fs) Total Jitter (Diff’l) (fs) Additive Jitter (Diff’l) (fs) 625 1.0 23.4 56.5 51.5 58.5 53.6 Rev. 1.0 23 Si53312 2.12. Input Mux Noise Isolation LVPECL [email protected]; Selected clk is active Unselected clk is static Mux Isolation = 61dB LVPECL [email protected]; Selected clk is static Unselected clk is active Figure 16. Input Mux Noise Isolation 2.13. Power Supply Noise Rejection The device supports on-chip supply voltage regulation to reject noise present on the power supply, simplifying low jitter operation in real-world environments. This feature enables robust operation alongside FPGAs, ASICs and SoCs and may reduce board-level filtering requirements. For more information, see AN491: “Power Supply Rejection for Low Jitter Clocks”. 24 Rev. 1.0 Si53312 VDDOA Q3 Q3 Q4 Q4 GND Q5 Q5 Q6 Q6 VDDOB 3. Pin Description: 44-Pin QFN 34 35 36 37 38 39 40 41 42 43 44 DIVA 1 33 SFOUTA[1] SFOUTA[0] 2 32 3 31 Q2 4 30 Q2 5 29 GND 6 Q1 7 Q1 Q0 Q0 NC DIVB SFOUTB[1] SFOUTB[0] 28 Q7 Q7 NC 27 Q8 8 26 Q8 9 25 Q9 10 24 Q9 11 23 CLK_SEL 22 21 20 19 18 17 16 15 14 13 NC CLK0 CLK0 OEA VREF OEB CLK1 CLK1 NC GND VDD 12 GND PAD Table 24. Si53312 44-Pin QFN Descriptions Pin # Name Description 1 DIVA Output divider control pin for Bank A. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 2 SFOUTA[1] Output signal format control pin for Bank A. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 3 SFOUTA[0] Output signal format control pin for Bank A. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 4 Q2 Output clock 2 (complement). 5 Q2 Output clock 2. 6 GND 7 Q1 Output clock 1 (complement). 8 Q1 Output clock 1. Ground. Rev. 1.0 25 Si53312 Table 24. Si53312 44-Pin QFN Descriptions (Continued) Pin # Name 9 Q0 Output clock 0 (complement). 10 Q0 Output clock 0. 11 NC No connect. 12 VDD Core voltage supply. Bypass with a 1.0 µF capacitor placed as close to the pin as possible. 13 NC No connect. 14 CLK0 Input clock 0. 15 CLK0 Input clock 0 (complement). When the CLK0 is driven by a single-end LVCMOS input, connect CLK0 to Vdd/2. CLK0 contains an internal pull-up resistor. 16 OEA Output enable—Bank A. When OEA = high, the Bank A outputs are enabled. When OEA = low, Q is held low and Q is held high for differential formats. For LVCMOS, both Q and Q are held low when OEA is set low. OEA contains an internal pull-up resistor. 17 VREF Reference voltage for single-ended CMOS clocks. VREF is an output voltage and is equal to VDD/2. It can be used to bias the /CLK input for single ended input clocks. See Section 2.3 for more details. 18 OEB Output enable—Bank B. When OEB = high, the Bank B outputs are enabled. When OEB = low, Q is held low and Q is held high for differential formats. For LVCMOS, both Q and Q are held low when OEB is set low. OEB contains an internal pull-up resistor. 19 CLK1 Input clock 1. 20 CLK1 Input clock 1 (complement). When the CLK1 is driven by a single-end LVCMOS input, connect CLK1 to Vdd/2. CLK1 contains an internal pull-up resistor. 21 NC 22 GND 23 CLK_SEL 24 Q9 Output clock 9 (complement). 25 Q9 Output clock 9. 26 Q8 Output clock 8 (complement). 26 Description No connect. Ground. MUX input select pin (LVCMOS). When CLK_SEL is high, CLK1 is selected. When CLK_SEL is low, CLK0 is selected. CLK_SEL contains an internal pull-down resistor. Rev. 1.0 Si53312 Table 24. Si53312 44-Pin QFN Descriptions (Continued) Pin # Name Description 27 Q8 Output clock 8. 28 NC No connect. 29 Q7 Output clock 7 (complement). 30 Q7 Output clock 7. 31 SFOUTB[0] Output signal format control pin for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 32 SFOUTB[1] Output signal format control pin for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 33 DIVB Output divider configuration bit for Bank B. Three-level input control. Internally biased at VDD/2. Can be left floating or tied to ground or VDD. 34 VDDOB 35 Q6 Output clock 6 (complement). 36 Q6 Output clock 6. 37 Q5 Output clock 5 (complement). 38 Q5 Output clock 5. 39 GND 40 Q4 Output clock 4 (complement). 41 Q4 Output clock 4. 42 Q3 Output clock 3 (complement). 43 Q3 Output clock 3. 44 VDDOA GND Pad GND Output Clock Voltage Supply—Bank B (Outputs: Q5 to Q9). Bypass with a 1.0 µF capacitor placed as close to the pin as possible. Ground. Output Voltage Supply—Bank A (Outputs: Q0 to Q4). Bypass with a 1.0 µF capacitor placed as close to the pin as possible. Ground Pad. Power supply ground and thermal relief. Rev. 1.0 27 Si53312 4. Ordering Guide 28 Part Number Package PB-Free, ROHS-6 Temperature Si53312-B-GM 44-QFN Yes –40 to 85 °C Rev. 1.0 Si53312 5. Package Outline 5.1. 7x7 mm 44-QFN Package Diagram Figure 17. Si53312 7x7 mm 44-QFN Package Diagram Table 25. Package Diagram Dimensions Dimension MIN NOM MAX A 0.80 0.85 0.90 A1 0.00 0.02 0.05 b 0.18 0.25 0.30 D D2 7.00 BSC 2.65 e 2.80 2.95 0.50 BSC E 7.00 BSC E2 2.65 2.80 2.95 L 0.30 0.40 0.50 aaa — — 0.10 bbb — — 0.10 ccc — — 0.08 ddd — — 0.10 Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-220. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. Rev. 1.0 29 Si53312 6. PCB Land Pattern 6.1. 7x7 mm 44-QFN Package Land Pattern Figure 18. Si53312 7x7 mm 44-QFN Package Land Pattern Table 26. PCB Land Pattern Dimension Min Max Dimension Min Max C1 6.80 6.90 X2 2.85 2.95 C2 6.80 6.90 Y1 0.75 0.85 Y2 2.85 2.95 E X1 0.50 BSC 0.20 0.30 Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. This Land Pattern Design is based on the IPC-7351 guidelines. Solder Mask Design 1. All metal pads are to be non-solder mask defined (NSMD). Clearance between the solder mask and the metal pad is to be 60 μm minimum, all the way around the pad. Stencil Design 1. A stainless steel, laser-cut and electro-polished stencil with trapezoidal walls should be used to assure good solder paste release. 2. The stencil thickness should be 0.125 mm (5 mils). 3. The ratio of stencil aperture to land pad size should be 1:1 for all perimeter pads. 4. A 2x2 array of 1.0 mm square openings on 1.45 mm pitch should be used for the center ground pad. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020 specification for Small Body Components. 30 Rev. 1.0 Si53312 7. Top Marking 7.1. Si53312 Top Marking 7.2. Top Marking Explanation Mark Method: Laser Font Size: 1.9 Point (26 mils) Right-Justified Line 1 Marking: Device Part Number 53312-B-GM Line 2 Marking: YY=Year WW=Work Week Assigned by Assembly Supplier. Corresponds to the year and work week of the mold date. TTTTTT=Mfg Code Line 3 Marking: Circle=1.3 mm Diameter Center-Justified Line 4 Marking Manufacturing Code from the Assembly Purchase Order form. “e3” Pb-Free Symbol Country of Origin ISO Code Abbreviation TW Circle = 0.75 mm Diameter Filled Pin 1 Identification Rev. 1.0 31 Si53312 DOCUMENT CHANGE LIST Revision 0.4 to Revision 1.0 32 Updated frequency spec from 1MHz to dc. Updated operating conditions, including LVCMOS and HCSL voltage support. Updated tables 1-11. Fixed package error to reflect 44-pin instead of 32pin throughout document. Updated section 2.1-2.12 text descriptions and diagrams. Improved data for additive jitter specifications. Improved typical phase noise plots. Improved performance specifications with more detail. Rev. 1.0 Si53312 CONTACT INFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. Patent Notice Silicon Labs invests in research and development to help our customers differentiate in the market with innovative low-power, small size, analogintensive mixed-signal solutions. Silicon Labs' extensive patent portfolio is a testament to our unique approach and world-class engineering team. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. 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